Squashed 'external/ircolib/' changes from ce3cd726c..de6e324bd

de6e324bd separate emu thread 10d3daf86 Roms List improvements 95d202f37 Let's make the rom list process on a separate thread so the emulator doesnt take ages to load. fc306967f Wow the ROM Header was just completely busted. Game list view works now bad1691ee fuck this shit 2b59e5f46 game list in progress d26417b83 remappable inputs in progress ac4af8106 input e72abc240 update readme 430139dc9 Qt6 frontend 3080d4d45 Fix this small bug too 08cd13b85 Cop0 unused functions do not actually pose a threat (as per manual). They don't do anything, so shall we. 61bb4fb44 make idle loop detection a little more specific with where the load goes b037de4c3 SAZDFsdff 12e81e73e need to figure out why n64-systemtest loops indefinitely at some address that appears to be valid (i think it's me not invalidating the cache properly) 204f0e13b idle skipping seems to work! cb8bb634a sdkfjlasdf 58e5c89c1 Fix compilation issue on my machine (no idea) 24fb2898e attempting more serious idle skipping 214719577 Place rsp.Step inside cached interpreter. Gains about 3 more fps bb97dcc23 mmmmm 920b77d38 wjkhasdfjhkasdf 430ccdab4 it's a start... 4f42a673a Cached interpreter plays Mario 64. Start looking into RSP as well c9a030787 idle skipping works! 5fbda03ce new idea 366637aba Idle skipping... maybe? 609fa2fb0 Cache instructions implemented but broken lmao. Commented out for now e140a6d12 - Stop using inheritance for CPU, instead use composition. - Introduce KAIZEN_JIT_ENABLED optional define instead of relying on __aarch64__ and the like. - More cache work 68e613057 prep cache impl 811b4d809 fix clang format fda755f7d idk d5024ebbf small MI refactor in preparation of (eventually) implementing the RDRAM interface properly 694b45341 Merge commit '206dcdedf195fb320913584180edb12c7731e396' as 'external/SDL' 206dcdedf Squashed 'external/SDL/' content from commit 4d17b99d0a 4d16e1cb4 need to update sdl 848b19920 Fix compilation error db61b5299 Merge commit 'e94a94559f28e49678fbcf72199a5258137b0fe9' as 'external/imgui' e94a94559 Squashed 'external/imgui/' content from commit 02e9b8cac 52edb3757 need to update imgui c1a705e86 Emulate weird JALR behaviour 4b4c32f4b Fix exception for "unusable COP1" in 4 instructions i missed accidentally (again) df5828142 Bug putting 0s in the log everywhere f8b580048 Make isviewer a sink to file 8241e9735 Fix exception for "unusable COP1" in 4 instructions i missed accidentally b29715f20 small changes d9a620bc1 make use of my new small utility library 0d1aa938e Add 'external/ircolib/' from commit 'ce3cd726c8df8388d554abf8bb55d55020eb4450' e64eb40b3 Fuck git git-subtree-dir: external/ircolib git-subtree-split: de6e324bde
2026-06-15 11:56:38 +02:00
parent ce3cd726c8
commit 00cc9309cb
4479 changed files with 2943227 additions and 7 deletions
@@ -0,0 +1,628 @@
+/* Capstone Disassembly Engine */
+/* TMS320C64x Backend by Fotis Loukos <me@fotisl.com> 2016 */
+
+#ifdef CAPSTONE_HAS_TMS320C64X
+
+#include <string.h>
+
+#include "../../cs_priv.h"
+#include "../../utils.h"
+
+#include "TMS320C64xDisassembler.h"
+
+#include "../../MCInst.h"
+#include "../../MCInstrDesc.h"
+#include "../../MCFixedLenDisassembler.h"
+#include "../../MCRegisterInfo.h"
+#include "../../MCDisassembler.h"
+#include "../../MathExtras.h"
+
+static uint64_t getFeatureBits(int mode);
+
+static DecodeStatus DecodeGPRegsRegisterClass(MCInst *Inst, unsigned RegNo,
+		uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeControlRegsRegisterClass(MCInst *Inst, unsigned RegNo,
+		uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeScst5(MCInst *Inst, unsigned Val,
+		uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeScst16(MCInst *Inst, unsigned Val,
+		uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodePCRelScst7(MCInst *Inst, unsigned Val,
+		uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodePCRelScst10(MCInst *Inst, unsigned Val,
+		uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodePCRelScst12(MCInst *Inst, unsigned Val,
+		uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodePCRelScst21(MCInst *Inst, unsigned Val,
+		uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeMemOperand(MCInst *Inst, unsigned Val,
+		uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeMemOperandSc(MCInst *Inst, unsigned Val,
+		uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeMemOperand2(MCInst *Inst, unsigned Val,
+		uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeRegPair5(MCInst *Inst, unsigned RegNo,
+		uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeRegPair4(MCInst *Inst, unsigned RegNo,
+		uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeCondRegister(MCInst *Inst, unsigned Val,
+		uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeCondRegisterZero(MCInst *Inst, unsigned Val,
+		uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeSide(MCInst *Inst, unsigned Val,
+		uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeParallel(MCInst *Inst, unsigned Val,
+		uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeCrosspathX1(MCInst *Inst, unsigned Val,
+		uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeCrosspathX2(MCInst *Inst, unsigned Val,
+		uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeCrosspathX3(MCInst *Inst, unsigned Val,
+		uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeNop(MCInst *Inst, unsigned Val,
+		uint64_t Address, void *Decoder);
+
+#include "TMS320C64xGenDisassemblerTables.inc"
+
+#define GET_REGINFO_ENUM
+#define GET_REGINFO_MC_DESC
+#include "TMS320C64xGenRegisterInfo.inc"
+
+static const unsigned GPRegsDecoderTable[] = {
+	TMS320C64x_A0,  TMS320C64x_A1,  TMS320C64x_A2,  TMS320C64x_A3,
+	TMS320C64x_A4,  TMS320C64x_A5,  TMS320C64x_A6,  TMS320C64x_A7,
+	TMS320C64x_A8,  TMS320C64x_A9,  TMS320C64x_A10, TMS320C64x_A11,
+	TMS320C64x_A12, TMS320C64x_A13, TMS320C64x_A14, TMS320C64x_A15,
+	TMS320C64x_A16, TMS320C64x_A17, TMS320C64x_A18, TMS320C64x_A19,
+	TMS320C64x_A20, TMS320C64x_A21, TMS320C64x_A22, TMS320C64x_A23,
+	TMS320C64x_A24, TMS320C64x_A25, TMS320C64x_A26, TMS320C64x_A27,
+	TMS320C64x_A28, TMS320C64x_A29, TMS320C64x_A30, TMS320C64x_A31
+};
+
+static const unsigned ControlRegsDecoderTable[] = {
+	TMS320C64x_AMR,    TMS320C64x_CSR,  TMS320C64x_ISR,   TMS320C64x_ICR,
+	TMS320C64x_IER,    TMS320C64x_ISTP, TMS320C64x_IRP,   TMS320C64x_NRP,
+	~0U,               ~0U,             TMS320C64x_TSCL,  TMS320C64x_TSCH,
+	~0U,               TMS320C64x_ILC,  TMS320C64x_RILC,  TMS320C64x_REP,
+	TMS320C64x_PCE1,   TMS320C64x_DNUM, ~0U,              ~0U,
+	~0U,               TMS320C64x_SSR,  TMS320C64x_GPLYA, TMS320C64x_GPLYB,
+	TMS320C64x_GFPGFR, TMS320C64x_DIER, TMS320C64x_TSR,   TMS320C64x_ITSR,
+	TMS320C64x_NTSR,   TMS320C64x_ECR,  ~0U,              TMS320C64x_IERR
+};
+
+static uint64_t getFeatureBits(int mode)
+{
+	// support everything
+	return (uint64_t)-1;
+}
+
+static unsigned getReg(const unsigned *RegTable, unsigned RegNo)
+{
+	if(RegNo > 31)
+		return ~0U;
+	return RegTable[RegNo];
+}
+
+static DecodeStatus DecodeGPRegsRegisterClass(MCInst *Inst, unsigned RegNo,
+		uint64_t Address, void *Decoder)
+{
+	unsigned Reg;
+
+	if(RegNo > 31)
+		return MCDisassembler_Fail;
+
+	Reg = getReg(GPRegsDecoderTable, RegNo);
+	if(Reg == ~0U)
+		return MCDisassembler_Fail;
+	MCOperand_CreateReg0(Inst, Reg);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeControlRegsRegisterClass(MCInst *Inst, unsigned RegNo,
+		uint64_t Address, void *Decoder)
+{
+	unsigned Reg;
+
+	if(RegNo > 31)
+		return MCDisassembler_Fail;
+
+	Reg = getReg(ControlRegsDecoderTable, RegNo);
+	if(Reg == ~0U)
+		return MCDisassembler_Fail;
+	MCOperand_CreateReg0(Inst, Reg);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeScst5(MCInst *Inst, unsigned Val,
+		uint64_t Address, void *Decoder)
+{
+	int32_t imm;
+
+	imm = Val;
+	/* Sign extend 5 bit value */
+	if(imm & (1 << (5 - 1)))
+		imm |= ~((1 << 5) - 1);
+
+	MCOperand_CreateImm0(Inst, imm);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeScst16(MCInst *Inst, unsigned Val,
+		uint64_t Address, void *Decoder)
+{
+	int32_t imm;
+
+	imm = Val;
+	/* Sign extend 16 bit value */
+	if(imm & (1 << (16 - 1)))
+		imm |= ~((1 << 16) - 1);
+
+	MCOperand_CreateImm0(Inst, imm);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodePCRelScst7(MCInst *Inst, unsigned Val,
+		uint64_t Address, void *Decoder)
+{
+	int32_t imm;
+
+	imm = Val;
+	/* Sign extend 7 bit value */
+	if(imm & (1 << (7 - 1)))
+		imm |= ~((1 << 7) - 1);
+
+	/* Address is relative to the address of the first instruction in the fetch packet */
+	MCOperand_CreateImm0(Inst, (Address & ~31) + (imm * 4));
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodePCRelScst10(MCInst *Inst, unsigned Val,
+		uint64_t Address, void *Decoder)
+{
+	int32_t imm;
+
+	imm = Val;
+	/* Sign extend 10 bit value */
+	if(imm & (1 << (10 - 1)))
+		imm |= ~((1 << 10) - 1);
+
+	/* Address is relative to the address of the first instruction in the fetch packet */
+	MCOperand_CreateImm0(Inst, (Address & ~31) + (imm * 4));
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodePCRelScst12(MCInst *Inst, unsigned Val,
+		uint64_t Address, void *Decoder)
+{
+	int32_t imm;
+
+	imm = Val;
+	/* Sign extend 12 bit value */
+	if(imm & (1 << (12 - 1)))
+		imm |= ~((1 << 12) - 1);
+
+	/* Address is relative to the address of the first instruction in the fetch packet */
+	MCOperand_CreateImm0(Inst, (Address & ~31) + (imm * 4));
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodePCRelScst21(MCInst *Inst, unsigned Val,
+		uint64_t Address, void *Decoder)
+{
+	int32_t imm;
+
+	imm = Val;
+	/* Sign extend 21 bit value */
+	if(imm & (1 << (21 - 1)))
+		imm |= ~((1 << 21) - 1);
+
+	/* Address is relative to the address of the first instruction in the fetch packet */
+	MCOperand_CreateImm0(Inst, (Address & ~31) + (imm * 4));
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeMemOperand(MCInst *Inst, unsigned Val,
+		uint64_t Address, void *Decoder)
+{
+	return DecodeMemOperandSc(Inst, Val | (1 << 15), Address, Decoder);
+}
+
+static DecodeStatus DecodeMemOperandSc(MCInst *Inst, unsigned Val,
+		uint64_t Address, void *Decoder)
+{
+	uint8_t scaled, base, offset, mode, unit;
+	unsigned basereg, offsetreg;
+
+	scaled = (Val >> 15) & 1;
+	base = (Val >> 10) & 0x1f;
+	offset = (Val >> 5) & 0x1f;
+	mode = (Val >> 1) & 0xf;
+	unit = Val & 1;
+
+	if((base >= TMS320C64X_REG_A0) && (base <= TMS320C64X_REG_A31))
+		base = (base - TMS320C64X_REG_A0 + TMS320C64X_REG_B0);
+	// base cannot be a B register, because it was ANDed above with 0x1f.
+	// And the TMS320C64X_REG_B0 > 31
+	basereg = getReg(GPRegsDecoderTable, base);
+	if (basereg ==  ~0U)
+		return MCDisassembler_Fail;
+
+	switch(mode) {
+		case 0:
+		case 1:
+		case 8:
+		case 9:
+		case 10:
+		case 11:
+			MCOperand_CreateImm0(Inst, (scaled << 19) | (basereg << 12) | (offset << 5) | (mode << 1) | unit);
+			break;
+		case 4:
+		case 5:
+		case 12:
+		case 13:
+		case 14:
+		case 15:
+			if((offset >= TMS320C64X_REG_A0) && (offset <= TMS320C64X_REG_A31))
+				offset = (offset - TMS320C64X_REG_A0 + TMS320C64X_REG_B0);
+			// offset cannot be a B register, because it was ANDed above with 0x1f.
+			// And the TMS320C64X_REG_B0 > 31
+			offsetreg = getReg(GPRegsDecoderTable, offset);
+			if (offsetreg ==  ~0U)
+				return MCDisassembler_Fail;
+			MCOperand_CreateImm0(Inst, (scaled << 19) | (basereg << 12) | (offsetreg << 5) | (mode << 1) | unit);
+			break;
+		default:
+			return MCDisassembler_Fail;
+	}
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeMemOperand2(MCInst *Inst, unsigned Val,
+		uint64_t Address, void *Decoder)
+{
+	uint16_t offset;
+	unsigned basereg;
+
+	if(Val & 1)
+		basereg = TMS320C64X_REG_B15;
+	else
+		basereg = TMS320C64X_REG_B14;
+
+	offset = (Val >> 1) & 0x7fff;
+	MCOperand_CreateImm0(Inst, (offset << 7) | basereg);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeRegPair5(MCInst *Inst, unsigned RegNo,
+		uint64_t Address, void *Decoder)
+{
+	unsigned Reg;
+
+	if(RegNo > 31)
+		return MCDisassembler_Fail;
+
+	Reg = getReg(GPRegsDecoderTable, RegNo);
+	MCOperand_CreateReg0(Inst, Reg);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeRegPair4(MCInst *Inst, unsigned RegNo,
+		uint64_t Address, void *Decoder)
+{
+	unsigned Reg;
+
+	if(RegNo > 15)
+		return MCDisassembler_Fail;
+
+	Reg = getReg(GPRegsDecoderTable, RegNo << 1);
+	MCOperand_CreateReg0(Inst, Reg);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeCondRegister(MCInst *Inst, unsigned Val,
+		uint64_t Address, void *Decoder)
+{
+	DecodeStatus ret = MCDisassembler_Success;
+
+	if(!Inst->flat_insn->detail)
+		return MCDisassembler_Success;
+
+	switch(Val) {
+		case 0:
+		case 7:
+			Inst->flat_insn->detail->tms320c64x.condition.reg = TMS320C64X_REG_INVALID;
+			break;
+		case 1:
+			Inst->flat_insn->detail->tms320c64x.condition.reg = TMS320C64X_REG_B0;
+			break;
+		case 2:
+			Inst->flat_insn->detail->tms320c64x.condition.reg = TMS320C64X_REG_B1;
+			break;
+		case 3:
+			Inst->flat_insn->detail->tms320c64x.condition.reg = TMS320C64X_REG_B2;
+			break;
+		case 4:
+			Inst->flat_insn->detail->tms320c64x.condition.reg = TMS320C64X_REG_A1;
+			break;
+		case 5:
+			Inst->flat_insn->detail->tms320c64x.condition.reg = TMS320C64X_REG_A2;
+			break;
+		case 6:
+			Inst->flat_insn->detail->tms320c64x.condition.reg = TMS320C64X_REG_A0;
+			break;
+		default:
+			Inst->flat_insn->detail->tms320c64x.condition.reg = TMS320C64X_REG_INVALID;
+			ret = MCDisassembler_Fail;
+			break;
+	}
+
+	return ret;
+}
+
+static DecodeStatus DecodeCondRegisterZero(MCInst *Inst, unsigned Val,
+		uint64_t Address, void *Decoder)
+{
+	DecodeStatus ret = MCDisassembler_Success;
+
+	if(!Inst->flat_insn->detail)
+		return MCDisassembler_Success;
+
+	switch(Val) {
+		case 0:
+			Inst->flat_insn->detail->tms320c64x.condition.zero = 0;
+			break;
+		case 1:
+			Inst->flat_insn->detail->tms320c64x.condition.zero = 1;
+			break;
+		default:
+			Inst->flat_insn->detail->tms320c64x.condition.zero = 0;
+			ret = MCDisassembler_Fail;
+			break;
+	}
+
+	return ret;
+}
+
+static DecodeStatus DecodeSide(MCInst *Inst, unsigned Val,
+		uint64_t Address, void *Decoder)
+{
+	DecodeStatus ret = MCDisassembler_Success;
+	MCOperand *op;
+	int i;
+
+	/* This is pretty messy, probably we should find a better way */
+	if(Val == 1) {
+		for(i = 0; i < Inst->size; i++) {
+			op = &Inst->Operands[i];
+			if(op->Kind == kRegister) {
+				if((op->RegVal >= TMS320C64X_REG_A0) && (op->RegVal <= TMS320C64X_REG_A31))
+					op->RegVal = (op->RegVal - TMS320C64X_REG_A0 + TMS320C64X_REG_B0);
+				else if((op->RegVal >= TMS320C64X_REG_B0) && (op->RegVal <= TMS320C64X_REG_B31))
+					op->RegVal = (op->RegVal - TMS320C64X_REG_B0 + TMS320C64X_REG_A0);
+			}
+		}
+	}
+
+	if(!Inst->flat_insn->detail)
+		return MCDisassembler_Success;
+
+	switch(Val) {
+		case 0:
+			Inst->flat_insn->detail->tms320c64x.funit.side = 1;
+			break;
+		case 1:
+			Inst->flat_insn->detail->tms320c64x.funit.side = 2;
+			break;
+		default:
+			Inst->flat_insn->detail->tms320c64x.funit.side = 0;
+			ret = MCDisassembler_Fail;
+			break;
+	}
+
+	return ret;
+}
+
+static DecodeStatus DecodeParallel(MCInst *Inst, unsigned Val,
+		uint64_t Address, void *Decoder)
+{
+	DecodeStatus ret = MCDisassembler_Success;
+
+	if(!Inst->flat_insn->detail)
+		return MCDisassembler_Success;
+
+	switch(Val) {
+		case 0:
+			Inst->flat_insn->detail->tms320c64x.parallel = 0;
+			break;
+		case 1:
+			Inst->flat_insn->detail->tms320c64x.parallel = 1;
+			break;
+		default:
+			Inst->flat_insn->detail->tms320c64x.parallel = -1;
+			ret = MCDisassembler_Fail;
+			break;
+	}
+
+	return ret;
+}
+
+static DecodeStatus DecodeCrosspathX1(MCInst *Inst, unsigned Val,
+		uint64_t Address, void *Decoder)
+{
+	DecodeStatus ret = MCDisassembler_Success;
+	MCOperand *op;
+
+	if(!Inst->flat_insn->detail)
+		return MCDisassembler_Success;
+
+	switch(Val) {
+		case 0:
+			Inst->flat_insn->detail->tms320c64x.funit.crosspath = 0;
+			break;
+		case 1:
+			Inst->flat_insn->detail->tms320c64x.funit.crosspath = 1;
+			op = &Inst->Operands[0];
+			if(op->Kind == kRegister) {
+				if((op->RegVal >= TMS320C64X_REG_A0) && (op->RegVal <= TMS320C64X_REG_A31))
+					op->RegVal = (op->RegVal - TMS320C64X_REG_A0 + TMS320C64X_REG_B0);
+				else if((op->RegVal >= TMS320C64X_REG_B0) && (op->RegVal <= TMS320C64X_REG_B31))
+					op->RegVal = (op->RegVal - TMS320C64X_REG_B0 + TMS320C64X_REG_A0);
+			}
+			break;
+		default:
+			Inst->flat_insn->detail->tms320c64x.funit.crosspath = -1;
+			ret = MCDisassembler_Fail;
+			break;
+	}
+
+	return ret;
+}
+
+static DecodeStatus DecodeCrosspathX2(MCInst *Inst, unsigned Val,
+		uint64_t Address, void *Decoder)
+{
+	DecodeStatus ret = MCDisassembler_Success;
+	MCOperand *op;
+
+	if(!Inst->flat_insn->detail)
+		return MCDisassembler_Success;
+
+	switch(Val) {
+		case 0:
+			Inst->flat_insn->detail->tms320c64x.funit.crosspath = 0;
+			break;
+		case 1:
+			Inst->flat_insn->detail->tms320c64x.funit.crosspath = 1;
+			op = &Inst->Operands[1];
+			if(op->Kind == kRegister) {
+				if((op->RegVal >= TMS320C64X_REG_A0) && (op->RegVal <= TMS320C64X_REG_A31))
+					op->RegVal = (op->RegVal - TMS320C64X_REG_A0 + TMS320C64X_REG_B0);
+				else if((op->RegVal >= TMS320C64X_REG_B0) && (op->RegVal <= TMS320C64X_REG_B31))
+					op->RegVal = (op->RegVal - TMS320C64X_REG_B0 + TMS320C64X_REG_A0);
+			}
+			break;
+		default:
+			Inst->flat_insn->detail->tms320c64x.funit.crosspath = -1;
+			ret = MCDisassembler_Fail;
+			break;
+	}
+
+	return ret;
+}
+
+static DecodeStatus DecodeCrosspathX3(MCInst *Inst, unsigned Val,
+		uint64_t Address, void *Decoder)
+{
+	DecodeStatus ret = MCDisassembler_Success;
+	MCOperand *op;
+
+	if(!Inst->flat_insn->detail)
+		return MCDisassembler_Success;
+
+	switch(Val) {
+		case 0:
+			Inst->flat_insn->detail->tms320c64x.funit.crosspath = 0;
+			break;
+		case 1:
+			Inst->flat_insn->detail->tms320c64x.funit.crosspath = 2;
+			op = &Inst->Operands[2];
+			if(op->Kind == kRegister) {
+				if((op->RegVal >= TMS320C64X_REG_A0) && (op->RegVal <= TMS320C64X_REG_A31))
+					op->RegVal = (op->RegVal - TMS320C64X_REG_A0 + TMS320C64X_REG_B0);
+				else if((op->RegVal >= TMS320C64X_REG_B0) && (op->RegVal <= TMS320C64X_REG_B31))
+					op->RegVal = (op->RegVal - TMS320C64X_REG_B0 + TMS320C64X_REG_A0);
+			}
+			break;
+		default:
+			Inst->flat_insn->detail->tms320c64x.funit.crosspath = -1;
+			ret = MCDisassembler_Fail;
+			break;
+	}
+
+	return ret;
+}
+
+
+static DecodeStatus DecodeNop(MCInst *Inst, unsigned Val,
+		uint64_t Address, void *Decoder)
+{
+	MCOperand_CreateImm0(Inst, Val + 1);
+
+	return MCDisassembler_Success;
+}
+
+#define GET_INSTRINFO_ENUM
+#include "TMS320C64xGenInstrInfo.inc"
+
+bool TMS320C64x_getInstruction(csh ud, const uint8_t *code, size_t code_len,
+		MCInst *MI, uint16_t *size, uint64_t address, void *info)
+{
+	uint32_t insn;
+	DecodeStatus result;
+
+	if(code_len < 4) {
+		*size = 0;
+		return MCDisassembler_Fail;
+	}
+
+	if(MI->flat_insn->detail)
+		memset(MI->flat_insn->detail, 0, offsetof(cs_detail, tms320c64x)+sizeof(cs_tms320c64x));
+
+	insn = readBytes32(MI, code);
+	result = decodeInstruction_4(DecoderTable32, MI, insn, address, info, 0);
+
+	if(result == MCDisassembler_Success) {
+		*size = 4;
+		return true;
+	}
+
+	MCInst_clear(MI);
+	*size = 0;
+	return false;
+}
+
+void TMS320C64x_init(MCRegisterInfo *MRI)
+{
+	MCRegisterInfo_InitMCRegisterInfo(MRI, TMS320C64xRegDesc, 90,
+			0, 0,
+			TMS320C64xMCRegisterClasses, 7,
+			0, 0,
+			TMS320C64xRegDiffLists,
+			0,
+			TMS320C64xSubRegIdxLists, 1,
+			0);
+}
+
+#endif
@@ -0,0 +1,19 @@
+/* Capstone Disassembly Engine */
+/* TMS320C64x Backend by Fotis Loukos <me@fotisl.com> 2016 */
+
+#ifndef CS_TMS320C64XDISASSEMBLER_H
+#define CS_TMS320C64XDISASSEMBLER_H
+
+#include <stdint.h>
+
+#include "capstone/capstone.h"
+#include "../../MCRegisterInfo.h"
+#include "../../MCInst.h"
+
+void TMS320C64x_init(MCRegisterInfo *MRI);
+
+bool TMS320C64x_getInstruction(csh ud, const uint8_t *code, size_t code_len,
+		MCInst *instr, uint16_t *size, uint64_t address, void *info);
+
+#endif
+
@@ -0,0 +1,686 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|*                                                                            *|
+|*Assembly Writer Source Fragment                                             *|
+|*                                                                            *|
+|* Automatically generated file, do not edit!                                 *|
+|*                                                                            *|
+\*===----------------------------------------------------------------------===*/
+
+#include <stdio.h>
+
+/// printInstruction - This method is automatically generated by tablegen
+/// from the instruction set description.
+static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) {
+  static const uint32_t OpInfo[] = {
+    0U,	// PHI
+    0U,	// INLINEASM
+    0U,	// CFI_INSTRUCTION
+    0U,	// EH_LABEL
+    0U,	// GC_LABEL
+    0U,	// KILL
+    0U,	// EXTRACT_SUBREG
+    0U,	// INSERT_SUBREG
+    0U,	// IMPLICIT_DEF
+    0U,	// SUBREG_TO_REG
+    0U,	// COPY_TO_REGCLASS
+    882U,	// DBG_VALUE
+    0U,	// REG_SEQUENCE
+    0U,	// COPY
+    875U,	// BUNDLE
+    904U,	// LIFETIME_START
+    862U,	// LIFETIME_END
+    0U,	// STACKMAP
+    0U,	// PATCHPOINT
+    0U,	// LOAD_STACK_GUARD
+    0U,	// STATEPOINT
+    0U,	// FRAME_ALLOC
+    1126U,	// ABS2_l2_rr
+    10847U,	// ABS_l1_pp
+    1631U,	// ABS_l1_rr
+    85006U,	// ADD2_d2_rrr
+    85006U,	// ADD2_l1_rrr_x2
+    85006U,	// ADD2_s1_rrr
+    85171U,	// ADD4_l1_rrr_x2
+    91479U,	// ADDAB_d1_rir
+    91479U,	// ADDAB_d1_rrr
+    91541U,	// ADDAD_d1_rir
+    91541U,	// ADDAD_d1_rrr
+    91577U,	// ADDAH_d1_rir
+    91577U,	// ADDAH_d1_rrr
+    91937U,	// ADDAW_d1_rir
+    91937U,	// ADDAW_d1_rrr
+    132488U,	// ADDKPC_s3_iir
+    1518U,	// ADDK_s2_ir
+    233140U,	// ADDU_l1_rpp
+    216756U,	// ADDU_l1_rrp_x2
+    91555U,	// ADD_d1_rir
+    91555U,	// ADD_d1_rrr
+    91555U,	// ADD_d2_rir
+    85411U,	// ADD_d2_rrr
+    232867U,	// ADD_l1_ipp
+    85411U,	// ADD_l1_irr
+    232867U,	// ADD_l1_rpp
+    216483U,	// ADD_l1_rrp_x2
+    85411U,	// ADD_l1_rrr_x2
+    85411U,	// ADD_s1_irr
+    85411U,	// ADD_s1_rrr
+    85542U,	// ANDN_d2_rrr
+    85542U,	// ANDN_l1_rrr_x2
+    85542U,	// ANDN_s4_rrr
+    85416U,	// AND_d2_rir
+    85416U,	// AND_d2_rrr
+    85416U,	// AND_l1_irr
+    85416U,	// AND_l1_rrr_x2
+    85416U,	// AND_s1_irr
+    85416U,	// AND_s1_rrr
+    85019U,	// AVG2_m1_rrr
+    85232U,	// AVGU4_m1_rrr
+    1410U,	// BDEC_s8_ir
+    1196U,	// BITC4_m2_rr
+    307756U,	// BNOP_s10_ri
+    307756U,	// BNOP_s9_ii
+    1654U,	// BPOS_s8_ir
+    53588U,	// B_s5_i
+    53588U,	// B_s6_r
+    892U,	// B_s7_irp
+    898U,	// B_s7_nrp
+    353870U,	// CLR_s15_riir
+    91726U,	// CLR_s1_rrr
+    85080U,	// CMPEQ2_s1_rrr
+    85207U,	// CMPEQ4_s1_rrr
+    101938U,	// CMPEQ_l1_ipr
+    85554U,	// CMPEQ_l1_irr
+    101938U,	// CMPEQ_l1_rpr
+    85554U,	// CMPEQ_l1_rrr_x2
+    85109U,	// CMPGT2_s1_rrr
+    85298U,	// CMPGTU4_s1_rrr
+    102037U,	// CMPGT_l1_ipr
+    85653U,	// CMPGT_l1_irr
+    102037U,	// CMPGT_l1_rpr
+    85653U,	// CMPGT_l1_rrr_x2
+    102150U,	// CMPLTU_l1_ipr
+    85766U,	// CMPLTU_l1_irr
+    102150U,	// CMPLTU_l1_rpr
+    85766U,	// CMPLTU_l1_rrr_x2
+    102044U,	// CMPLT_l1_ipr
+    85660U,	// CMPLT_l1_irr
+    102044U,	// CMPLT_l1_rpr
+    85660U,	// CMPLT_l1_rrr_x2
+    1529U,	// DEAL_m2_rr
+    216145U,	// DOTP2_m1_rrp
+    85073U,	// DOTP2_m1_rrr
+    85065U,	// DOTPN2_m1_rrr
+    85124U,	// DOTPNRSU2_m1_rrr
+    85135U,	// DOTPRSU2_m1_rrr
+    85281U,	// DOTPSU4_m1_rrr
+    85273U,	// DOTPU4_m1_rrr
+    354062U,	// EXTU_s15_riir
+    91918U,	// EXTU_s1_rrr
+    353955U,	// EXT_s15_riir
+    91811U,	// EXT_s1_rrr
+    102142U,	// GMPGTU_l1_ipr
+    85758U,	// GMPGTU_l1_irr
+    102142U,	// GMPGTU_l1_rpr
+    85758U,	// GMPGTU_l1_rrr_x2
+    85321U,	// GMPY4_m1_rrr
+    5800U,	// LDBU_d5_mr
+    6824U,	// LDBU_d6_mr
+    5470U,	// LDB_d5_mr
+    6494U,	// LDB_d6_mr
+    14120U,	// LDDW_d7_mp
+    5818U,	// LDHU_d5_mr
+    6842U,	// LDHU_d6_mr
+    5568U,	// LDH_d5_mr
+    6592U,	// LDH_d6_mr
+    14131U,	// LDNDW_d8_mp
+    5959U,	// LDNW_d5_mr
+    5934U,	// LDW_d5_mr
+    6958U,	// LDW_d6_mr
+    85404U,	// LMBD_l1_irr
+    85404U,	// LMBD_l1_rrr_x2
+    85145U,	// MAX2_l1_rrr_x2
+    85307U,	// MAXU4_l1_rrr_x2
+    85059U,	// MIN2_l1_rrr_x2
+    85266U,	// MINU4_l1_rrr_x2
+    216224U,	// MPY2_m1_rrp
+    85566U,	// MPYHIR_m1_rrr
+    216544U,	// MPYHI_m1_rrp
+    85720U,	// MPYHLU_m4_rrr
+    85516U,	// MPYHL_m4_rrr
+    85728U,	// MPYHSLU_m4_rrr
+    85743U,	// MPYHSU_m4_rrr
+    85613U,	// MPYHULS_m4_rrr
+    85628U,	// MPYHUS_m4_rrr
+    85713U,	// MPYHU_m4_rrr
+    85466U,	// MPYH_m4_rrr
+    85696U,	// MPYLHU_m4_rrr
+    85453U,	// MPYLH_m4_rrr
+    85574U,	// MPYLIR_m1_rrr
+    216551U,	// MPYLI_m1_rrp
+    85704U,	// MPYLSHU_m4_rrr
+    85604U,	// MPYLUHS_m4_rrr
+    216362U,	// MPYSU4_m1_rrp
+    85751U,	// MPYSU_m4_irr
+    85751U,	// MPYSU_m4_rrr
+    216386U,	// MPYU4_m1_rrp
+    85636U,	// MPYUS_m4_rrr
+    85780U,	// MPYU_m4_rrr
+    85849U,	// MPY_m4_irr
+    85849U,	// MPY_m4_rrr
+    1424U,	// MVC_s1_rr
+    1424U,	// MVC_s1_rr2
+    1453U,	// MVD_m2_rr
+    1477U,	// MVKLH_s12_ir
+    1524U,	// MVKL_s12_ir
+    1524U,	// MVK_d1_rr
+    1524U,	// MVK_l2_ir
+    53249U,	// NOP_n
+    2592U,	// NORM_l1_pr
+    1568U,	// NORM_l1_rr
+    85588U,	// OR_d2_rir
+    85588U,	// OR_d2_rrr
+    85588U,	// OR_l1_irr
+    85588U,	// OR_l1_rrr_x2
+    85588U,	// OR_s1_irr
+    85588U,	// OR_s1_rrr
+    85043U,	// PACK2_l1_rrr_x2
+    85043U,	// PACK2_s4_rrr
+    85025U,	// PACKH2_l1_rrr_x2
+    85025U,	// PACKH2_s1_rrr
+    85184U,	// PACKH4_l1_rrr_x2
+    85050U,	// PACKHL2_l1_rrr_x2
+    85050U,	// PACKHL2_s1_rrr
+    85192U,	// PACKL4_l1_rrr_x2
+    85033U,	// PACKLH2_l1_rrr_x2
+    85033U,	// PACKLH2_s1_rrr
+    91667U,	// ROTL_m1_rir
+    91667U,	// ROTL_m1_rrr
+    85005U,	// SADD2_s4_rrr
+    85224U,	// SADDU4_s4_rrr
+    85100U,	// SADDUS2_s4_rrr
+    232866U,	// SADD_l1_ipp
+    85410U,	// SADD_l1_irr
+    232866U,	// SADD_l1_rpp
+    85410U,	// SADD_l1_rrr_x2
+    85410U,	// SADD_s1_rrr
+    2699U,	// SAT_l1_pr
+    353936U,	// SET_s15_riir
+    91792U,	// SET_s1_rrr
+    1535U,	// SHFL_m2_rr
+    85347U,	// SHLMB_l1_rrr_x2
+    85347U,	// SHLMB_s4_rrr
+    223750U,	// SHL_s1_pip
+    223750U,	// SHL_s1_prp
+    222726U,	// SHL_s1_rip
+    91654U,	// SHL_s1_rir
+    222726U,	// SHL_s1_rrp
+    91654U,	// SHL_s1_rrr
+    91232U,	// SHR2_s1_rir
+    91232U,	// SHR2_s4_rrr
+    85354U,	// SHRMB_l1_rrr_x2
+    85354U,	// SHRMB_s4_rrr
+    91261U,	// SHRU2_s1_rir
+    91261U,	// SHRU2_s4_rrr
+    223977U,	// SHRU_s1_pip
+    223977U,	// SHRU_s1_prp
+    91881U,	// SHRU_s1_rir
+    91881U,	// SHRU_s1_rrr
+    223801U,	// SHR_s1_pip
+    223801U,	// SHR_s1_prp
+    91705U,	// SHR_s1_rir
+    91705U,	// SHR_s1_rrr
+    216223U,	// SMPY2_m1_rrp
+    85515U,	// SMPYHL_m4_rrr
+    85465U,	// SMPYH_m4_rrr
+    85452U,	// SMPYLH_m4_rrr
+    85848U,	// SMPY_m4_rrr
+    85042U,	// SPACK2_s4_rrr
+    85248U,	// SPACKU4_s4_rrr
+    91653U,	// SSHL_s1_rir
+    91653U,	// SSHL_s1_rrr
+    85529U,	// SSHVL_m1_rrr
+    85592U,	// SSHVR_m1_rrr
+    232822U,	// SSUB_l1_ipp
+    85366U,	// SSUB_l1_irr
+    85366U,	// SSUB_l1_rrr_x1
+    85366U,	// SSUB_l1_rrr_x2
+    438641U,	// STB_d5_rm
+    504177U,	// STB_d6_rm
+    8001U,	// STDW_d7_pm
+    438740U,	// STH_d5_rm
+    504276U,	// STH_d6_rm
+    7994U,	// STNDW_d8_pm
+    439117U,	// STNW_d5_rm
+    439123U,	// STW_d5_rm
+    504659U,	// STW_d6_rm
+    84999U,	// SUB2_d2_rrr
+    84999U,	// SUB2_l1_rrr_x2
+    84999U,	// SUB2_s1_rrr
+    85158U,	// SUB4_l1_rrr_x2
+    85215U,	// SUBABS4_l1_rrr_x2
+    91472U,	// SUBAB_d1_rir
+    91472U,	// SUBAB_d1_rrr
+    91472U,	// SUBAH_d1_rir
+    91570U,	// SUBAH_d1_rrr
+    91472U,	// SUBAW_d1_rir
+    91930U,	// SUBAW_d1_rrr
+    85372U,	// SUBC_l1_rrr_x2
+    216750U,	// SUBU_l1_rrp_x1
+    216750U,	// SUBU_l1_rrp_x2
+    91511U,	// SUB_d1_rir
+    91511U,	// SUB_d1_rrr
+    85367U,	// SUB_d2_rrr
+    232823U,	// SUB_l1_ipp
+    85367U,	// SUB_l1_irr
+    216439U,	// SUB_l1_rrp_x1
+    216439U,	// SUB_l1_rrp_x2
+    85367U,	// SUB_l1_rrr_x1
+    85367U,	// SUB_l1_rrr_x2
+    85367U,	// SUB_s1_irr
+    85367U,	// SUB_s1_rrr
+    91511U,	// SUB_s4_rrr
+    1232U,	// SWAP4_l2_rr
+    1271U,	// UNPKHU4_l2_rr
+    1271U,	// UNPKHU4_s14_rr
+    1289U,	// UNPKLU4_l2_rr
+    1289U,	// UNPKLU4_s14_rr
+    85587U,	// XOR_d2_rir
+    85587U,	// XOR_d2_rrr
+    85587U,	// XOR_l1_irr
+    85587U,	// XOR_l1_rrr_x2
+    85587U,	// XOR_s1_irr
+    85587U,	// XOR_s1_rrr
+    1044U,	// XPND2_m2_rr
+    1209U,	// XPND4_m2_rr
+    0U
+  };
+
+#ifndef CAPSTONE_DIET
+  static const char AsmStrs[] = {
+  /* 0 */ 'n', 'o', 'p', 9, 9, 0,
+  /* 6 */ 's', 'u', 'b', '2', 9, 0,
+  /* 12 */ 's', 'a', 'd', 'd', '2', 9, 0,
+  /* 19 */ 'x', 'p', 'n', 'd', '2', 9, 0,
+  /* 26 */ 'a', 'v', 'g', '2', 9, 0,
+  /* 32 */ 'p', 'a', 'c', 'k', 'h', '2', 9, 0,
+  /* 40 */ 'p', 'a', 'c', 'k', 'l', 'h', '2', 9, 0,
+  /* 49 */ 's', 'p', 'a', 'c', 'k', '2', 9, 0,
+  /* 57 */ 'p', 'a', 'c', 'k', 'h', 'l', '2', 9, 0,
+  /* 66 */ 'm', 'i', 'n', '2', 9, 0,
+  /* 72 */ 'd', 'o', 't', 'p', 'n', '2', 9, 0,
+  /* 80 */ 'd', 'o', 't', 'p', '2', 9, 0,
+  /* 87 */ 'c', 'm', 'p', 'e', 'q', '2', 9, 0,
+  /* 95 */ 's', 'h', 'r', '2', 9, 0,
+  /* 101 */ 'a', 'b', 's', '2', 9, 0,
+  /* 107 */ 's', 'a', 'd', 'd', 'u', 's', '2', 9, 0,
+  /* 116 */ 'c', 'm', 'p', 'g', 't', '2', 9, 0,
+  /* 124 */ 's', 'h', 'r', 'u', '2', 9, 0,
+  /* 131 */ 'd', 'o', 't', 'p', 'n', 'r', 's', 'u', '2', 9, 0,
+  /* 142 */ 'd', 'o', 't', 'p', 'r', 's', 'u', '2', 9, 0,
+  /* 152 */ 'm', 'a', 'x', '2', 9, 0,
+  /* 158 */ 's', 'm', 'p', 'y', '2', 9, 0,
+  /* 165 */ 's', 'u', 'b', '4', 9, 0,
+  /* 171 */ 'b', 'i', 't', 'c', '4', 9, 0,
+  /* 178 */ 'a', 'd', 'd', '4', 9, 0,
+  /* 184 */ 'x', 'p', 'n', 'd', '4', 9, 0,
+  /* 191 */ 'p', 'a', 'c', 'k', 'h', '4', 9, 0,
+  /* 199 */ 'p', 'a', 'c', 'k', 'l', '4', 9, 0,
+  /* 207 */ 's', 'w', 'a', 'p', '4', 9, 0,
+  /* 214 */ 'c', 'm', 'p', 'e', 'q', '4', 9, 0,
+  /* 222 */ 's', 'u', 'b', 'a', 'b', 's', '4', 9, 0,
+  /* 231 */ 's', 'a', 'd', 'd', 'u', '4', 9, 0,
+  /* 239 */ 'a', 'v', 'g', 'u', '4', 9, 0,
+  /* 246 */ 'u', 'n', 'p', 'k', 'h', 'u', '4', 9, 0,
+  /* 255 */ 's', 'p', 'a', 'c', 'k', 'u', '4', 9, 0,
+  /* 264 */ 'u', 'n', 'p', 'k', 'l', 'u', '4', 9, 0,
+  /* 273 */ 'm', 'i', 'n', 'u', '4', 9, 0,
+  /* 280 */ 'd', 'o', 't', 'p', 'u', '4', 9, 0,
+  /* 288 */ 'd', 'o', 't', 'p', 's', 'u', '4', 9, 0,
+  /* 297 */ 'm', 'p', 'y', 's', 'u', '4', 9, 0,
+  /* 305 */ 'c', 'm', 'p', 'g', 't', 'u', '4', 9, 0,
+  /* 314 */ 'm', 'a', 'x', 'u', '4', 9, 0,
+  /* 321 */ 'm', 'p', 'y', 'u', '4', 9, 0,
+  /* 328 */ 'g', 'm', 'p', 'y', '4', 9, 0,
+  /* 335 */ 's', 'u', 'b', 'a', 'b', 9, 0,
+  /* 342 */ 'a', 'd', 'd', 'a', 'b', 9, 0,
+  /* 349 */ 'l', 'd', 'b', 9, 0,
+  /* 354 */ 's', 'h', 'l', 'm', 'b', 9, 0,
+  /* 361 */ 's', 'h', 'r', 'm', 'b', 9, 0,
+  /* 368 */ 's', 't', 'b', 9, 0,
+  /* 373 */ 's', 's', 'u', 'b', 9, 0,
+  /* 379 */ 's', 'u', 'b', 'c', 9, 0,
+  /* 385 */ 'b', 'd', 'e', 'c', 9, 0,
+  /* 391 */ 'a', 'd', 'd', 'k', 'p', 'c', 9, 0,
+  /* 399 */ 'm', 'v', 'c', 9, 0,
+  /* 404 */ 'a', 'd', 'd', 'a', 'd', 9, 0,
+  /* 411 */ 'l', 'm', 'b', 'd', 9, 0,
+  /* 417 */ 's', 'a', 'd', 'd', 9, 0,
+  /* 423 */ 'a', 'n', 'd', 9, 0,
+  /* 428 */ 'm', 'v', 'd', 9, 0,
+  /* 433 */ 's', 'u', 'b', 'a', 'h', 9, 0,
+  /* 440 */ 'a', 'd', 'd', 'a', 'h', 9, 0,
+  /* 447 */ 'l', 'd', 'h', 9, 0,
+  /* 452 */ 'm', 'v', 'k', 'l', 'h', 9, 0,
+  /* 459 */ 's', 'm', 'p', 'y', 'l', 'h', 9, 0,
+  /* 467 */ 's', 't', 'h', 9, 0,
+  /* 472 */ 's', 'm', 'p', 'y', 'h', 9, 0,
+  /* 479 */ 'm', 'p', 'y', 'h', 'i', 9, 0,
+  /* 486 */ 'm', 'p', 'y', 'l', 'i', 9, 0,
+  /* 493 */ 'a', 'd', 'd', 'k', 9, 0,
+  /* 499 */ 'm', 'v', 'k', 9, 0,
+  /* 504 */ 'd', 'e', 'a', 'l', 9, 0,
+  /* 510 */ 's', 'h', 'f', 'l', 9, 0,
+  /* 516 */ 's', 's', 'h', 'l', 9, 0,
+  /* 522 */ 's', 'm', 'p', 'y', 'h', 'l', 9, 0,
+  /* 530 */ 'r', 'o', 't', 'l', 9, 0,
+  /* 536 */ 's', 's', 'h', 'v', 'l', 9, 0,
+  /* 543 */ 'n', 'o', 'r', 'm', 9, 0,
+  /* 549 */ 'a', 'n', 'd', 'n', 9, 0,
+  /* 555 */ 'b', 'n', 'o', 'p', 9, 0,
+  /* 561 */ 'c', 'm', 'p', 'e', 'q', 9, 0,
+  /* 568 */ 's', 'h', 'r', 9, 0,
+  /* 573 */ 'm', 'p', 'y', 'h', 'i', 'r', 9, 0,
+  /* 581 */ 'm', 'p', 'y', 'l', 'i', 'r', 9, 0,
+  /* 589 */ 'c', 'l', 'r', 9, 0,
+  /* 594 */ 'x', 'o', 'r', 9, 0,
+  /* 599 */ 's', 's', 'h', 'v', 'r', 9, 0,
+  /* 606 */ 'a', 'b', 's', 9, 0,
+  /* 611 */ 'm', 'p', 'y', 'l', 'u', 'h', 's', 9, 0,
+  /* 620 */ 'm', 'p', 'y', 'h', 'u', 'l', 's', 9, 0,
+  /* 629 */ 'b', 'p', 'o', 's', 9, 0,
+  /* 635 */ 'm', 'p', 'y', 'h', 'u', 's', 9, 0,
+  /* 643 */ 'm', 'p', 'y', 'u', 's', 9, 0,
+  /* 650 */ 's', 'a', 't', 9, 0,
+  /* 655 */ 's', 'e', 't', 9, 0,
+  /* 660 */ 'c', 'm', 'p', 'g', 't', 9, 0,
+  /* 667 */ 'c', 'm', 'p', 'l', 't', 9, 0,
+  /* 674 */ 'e', 'x', 't', 9, 0,
+  /* 679 */ 'l', 'd', 'b', 'u', 9, 0,
+  /* 685 */ 's', 'u', 'b', 'u', 9, 0,
+  /* 691 */ 'a', 'd', 'd', 'u', 9, 0,
+  /* 697 */ 'l', 'd', 'h', 'u', 9, 0,
+  /* 703 */ 'm', 'p', 'y', 'l', 'h', 'u', 9, 0,
+  /* 711 */ 'm', 'p', 'y', 'l', 's', 'h', 'u', 9, 0,
+  /* 720 */ 'm', 'p', 'y', 'h', 'u', 9, 0,
+  /* 727 */ 'm', 'p', 'y', 'h', 'l', 'u', 9, 0,
+  /* 735 */ 'm', 'p', 'y', 'h', 's', 'l', 'u', 9, 0,
+  /* 744 */ 's', 'h', 'r', 'u', 9, 0,
+  /* 750 */ 'm', 'p', 'y', 'h', 's', 'u', 9, 0,
+  /* 758 */ 'm', 'p', 'y', 's', 'u', 9, 0,
+  /* 765 */ 'c', 'm', 'p', 'g', 't', 'u', 9, 0,
+  /* 773 */ 'c', 'm', 'p', 'l', 't', 'u', 9, 0,
+  /* 781 */ 'e', 'x', 't', 'u', 9, 0,
+  /* 787 */ 'm', 'p', 'y', 'u', 9, 0,
+  /* 793 */ 's', 'u', 'b', 'a', 'w', 9, 0,
+  /* 800 */ 'a', 'd', 'd', 'a', 'w', 9, 0,
+  /* 807 */ 'l', 'd', 'd', 'w', 9, 0,
+  /* 813 */ 'l', 'd', 'w', 9, 0,
+  /* 818 */ 'l', 'd', 'n', 'd', 'w', 9, 0,
+  /* 825 */ 's', 't', 'n', 'd', 'w', 9, 0,
+  /* 832 */ 's', 't', 'd', 'w', 9, 0,
+  /* 838 */ 'l', 'd', 'n', 'w', 9, 0,
+  /* 844 */ 's', 't', 'n', 'w', 9, 0,
+  /* 850 */ 's', 't', 'w', 9, 0,
+  /* 855 */ 's', 'm', 'p', 'y', 9, 0,
+  /* 861 */ 'l', 'i', 'f', 'e', 't', 'i', 'm', 'e', '_', 'e', 'n', 'd', 0,
+  /* 874 */ 'b', 'u', 'n', 'd', 'l', 'e', 0,
+  /* 881 */ 'd', 'b', 'g', '_', 'v', 'a', 'l', 'u', 'e', 0,
+  /* 891 */ 'b', 9, 'i', 'r', 'p', 0,
+  /* 897 */ 'b', 9, 'n', 'r', 'p', 0,
+  /* 903 */ 'l', 'i', 'f', 'e', 't', 'i', 'm', 'e', '_', 's', 't', 'a', 'r', 't', 0,
+  };
+#endif
+
+  // Emit the opcode for the instruction.
+  uint32_t Bits = OpInfo[MCInst_getOpcode(MI)];
+  CS_ASSERT_RET(Bits != 0 && "Cannot print this instruction.");
+#ifndef CAPSTONE_DIET
+  SStream_concat0(O, AsmStrs+(Bits & 1023)-1);
+#endif
+
+
+  // Fragment 0 encoded into 3 bits for 8 unique commands.
+  switch ((uint32_t)((Bits >> 10) & 7)) {
+  default:
+  case 0:
+    // DBG_VALUE, BUNDLE, LIFETIME_START, LIFETIME_END, B_s7_irp, B_s7_nrp
+    return;
+    break;
+  case 1:
+    // ABS2_l2_rr, ABS_l1_rr, ADDAB_d1_rir, ADDAB_d1_rrr, ADDAD_d1_rir, ADDAD...
+    printOperand(MI, 1, O); 
+    SStream_concat0(O, ", ");
+    break;
+  case 2:
+    // ABS_l1_pp, NORM_l1_pr, SAT_l1_pr, SHL_s1_pip, SHL_s1_prp, SHRU_s1_pip,...
+    printRegPair(MI, 1, O); 
+    SStream_concat0(O, ", ");
+    break;
+  case 3:
+    // ADD2_d2_rrr, ADD2_l1_rrr_x2, ADD2_s1_rrr, ADD4_l1_rrr_x2, ADDU_l1_rpp,...
+    printOperand(MI, 2, O); 
+    SStream_concat0(O, ", ");
+    break;
+  case 4:
+    // BNOP_s10_ri, BNOP_s9_ii, B_s5_i, B_s6_r, NOP_n, STB_d5_rm, STB_d6_rm, ...
+    printOperand(MI, 0, O); 
+    break;
+  case 5:
+    // LDBU_d5_mr, LDB_d5_mr, LDDW_d7_mp, LDHU_d5_mr, LDH_d5_mr, LDNDW_d8_mp,...
+    printMemOperand(MI, 1, O); 
+    SStream_concat0(O, ", ");
+    break;
+  case 6:
+    // LDBU_d6_mr, LDB_d6_mr, LDHU_d6_mr, LDH_d6_mr, LDW_d6_mr
+    printMemOperand2(MI, 1, O); 
+    SStream_concat0(O, ", ");
+    printOperand(MI, 0, O); 
+    return;
+    break;
+  case 7:
+    // STDW_d7_pm, STNDW_d8_pm
+    printRegPair(MI, 0, O); 
+    SStream_concat0(O, ", ");
+    printMemOperand(MI, 1, O); 
+    return;
+    break;
+  }
+
+
+  // Fragment 1 encoded into 3 bits for 7 unique commands.
+  switch ((uint32_t)((Bits >> 13) & 7)) {
+  default:
+  case 0:
+    // ABS2_l2_rr, ABS_l1_rr, ADDKPC_s3_iir, ADDK_s2_ir, BDEC_s8_ir, BITC4_m2...
+    printOperand(MI, 0, O); 
+    break;
+  case 1:
+    // ABS_l1_pp, LDDW_d7_mp, LDNDW_d8_mp
+    printRegPair(MI, 0, O); 
+    return;
+    break;
+  case 2:
+    // ADD2_d2_rrr, ADD2_l1_rrr_x2, ADD2_s1_rrr, ADD4_l1_rrr_x2, ADDU_l1_rrp_...
+    printOperand(MI, 1, O); 
+    SStream_concat0(O, ", ");
+    break;
+  case 3:
+    // ADDAB_d1_rir, ADDAB_d1_rrr, ADDAD_d1_rir, ADDAD_d1_rrr, ADDAH_d1_rir, ...
+    printOperand(MI, 2, O); 
+    SStream_concat0(O, ", ");
+    break;
+  case 4:
+    // ADDU_l1_rpp, ADD_l1_ipp, ADD_l1_rpp, CMPEQ_l1_ipr, CMPEQ_l1_rpr, CMPGT...
+    printRegPair(MI, 1, O); 
+    SStream_concat0(O, ", ");
+    break;
+  case 5:
+    // BNOP_s10_ri, BNOP_s9_ii, STB_d5_rm, STB_d6_rm, STH_d5_rm, STH_d6_rm, S...
+    SStream_concat0(O, ", ");
+    break;
+  case 6:
+    // B_s5_i, B_s6_r, NOP_n
+    return;
+    break;
+  }
+
+
+  // Fragment 2 encoded into 3 bits for 8 unique commands.
+  switch ((uint32_t)((Bits >> 16) & 7)) {
+  default:
+  case 0:
+    // ABS2_l2_rr, ABS_l1_rr, ADDK_s2_ir, BDEC_s8_ir, BITC4_m2_rr, BPOS_s8_ir...
+    return;
+    break;
+  case 1:
+    // ADD2_d2_rrr, ADD2_l1_rrr_x2, ADD2_s1_rrr, ADD4_l1_rrr_x2, ADDAB_d1_rir...
+    printOperand(MI, 0, O); 
+    return;
+    break;
+  case 2:
+    // ADDKPC_s3_iir
+    SStream_concat0(O, ", ");
+    printOperand(MI, 2, O); 
+    return;
+    break;
+  case 3:
+    // ADDU_l1_rpp, ADDU_l1_rrp_x2, ADD_l1_ipp, ADD_l1_rpp, ADD_l1_rrp_x2, DO...
+    printRegPair(MI, 0, O); 
+    return;
+    break;
+  case 4:
+    // BNOP_s10_ri, BNOP_s9_ii
+    printOperand(MI, 1, O); 
+    return;
+    break;
+  case 5:
+    // CLR_s15_riir, EXTU_s15_riir, EXT_s15_riir, SET_s15_riir
+    printOperand(MI, 3, O); 
+    SStream_concat0(O, ", ");
+    printOperand(MI, 0, O); 
+    return;
+    break;
+  case 6:
+    // STB_d5_rm, STH_d5_rm, STNW_d5_rm, STW_d5_rm
+    printMemOperand(MI, 1, O); 
+    return;
+    break;
+  case 7:
+    // STB_d6_rm, STH_d6_rm, STW_d6_rm
+    printMemOperand2(MI, 1, O); 
+    return;
+    break;
+  }
+
+}
+
+
+/// getRegisterName - This method is automatically generated by tblgen
+/// from the register set description.  This returns the assembler name
+/// for the specified register.
+static const char *getRegisterName(unsigned RegNo) {
+#ifndef CAPSTONE_DIET
+  static const char AsmStrs[] = {
+  /* 0 */ 'a', '1', '0', 0,
+  /* 4 */ 'b', '1', '0', 0,
+  /* 8 */ 'a', '2', '0', 0,
+  /* 12 */ 'b', '2', '0', 0,
+  /* 16 */ 'a', '3', '0', 0,
+  /* 20 */ 'b', '3', '0', 0,
+  /* 24 */ 'a', '0', 0,
+  /* 27 */ 'b', '0', 0,
+  /* 30 */ 'a', '1', '1', 0,
+  /* 34 */ 'b', '1', '1', 0,
+  /* 38 */ 'a', '2', '1', 0,
+  /* 42 */ 'b', '2', '1', 0,
+  /* 46 */ 'a', '3', '1', 0,
+  /* 50 */ 'b', '3', '1', 0,
+  /* 54 */ 'a', '1', 0,
+  /* 57 */ 'b', '1', 0,
+  /* 60 */ 'p', 'c', 'e', '1', 0,
+  /* 65 */ 'a', '1', '2', 0,
+  /* 69 */ 'b', '1', '2', 0,
+  /* 73 */ 'a', '2', '2', 0,
+  /* 77 */ 'b', '2', '2', 0,
+  /* 81 */ 'a', '2', 0,
+  /* 84 */ 'b', '2', 0,
+  /* 87 */ 'a', '1', '3', 0,
+  /* 91 */ 'b', '1', '3', 0,
+  /* 95 */ 'a', '2', '3', 0,
+  /* 99 */ 'b', '2', '3', 0,
+  /* 103 */ 'a', '3', 0,
+  /* 106 */ 'b', '3', 0,
+  /* 109 */ 'a', '1', '4', 0,
+  /* 113 */ 'b', '1', '4', 0,
+  /* 117 */ 'a', '2', '4', 0,
+  /* 121 */ 'b', '2', '4', 0,
+  /* 125 */ 'a', '4', 0,
+  /* 128 */ 'b', '4', 0,
+  /* 131 */ 'a', '1', '5', 0,
+  /* 135 */ 'b', '1', '5', 0,
+  /* 139 */ 'a', '2', '5', 0,
+  /* 143 */ 'b', '2', '5', 0,
+  /* 147 */ 'a', '5', 0,
+  /* 150 */ 'b', '5', 0,
+  /* 153 */ 'a', '1', '6', 0,
+  /* 157 */ 'b', '1', '6', 0,
+  /* 161 */ 'a', '2', '6', 0,
+  /* 165 */ 'b', '2', '6', 0,
+  /* 169 */ 'a', '6', 0,
+  /* 172 */ 'b', '6', 0,
+  /* 175 */ 'a', '1', '7', 0,
+  /* 179 */ 'b', '1', '7', 0,
+  /* 183 */ 'a', '2', '7', 0,
+  /* 187 */ 'b', '2', '7', 0,
+  /* 191 */ 'a', '7', 0,
+  /* 194 */ 'b', '7', 0,
+  /* 197 */ 'a', '1', '8', 0,
+  /* 201 */ 'b', '1', '8', 0,
+  /* 205 */ 'a', '2', '8', 0,
+  /* 209 */ 'b', '2', '8', 0,
+  /* 213 */ 'a', '8', 0,
+  /* 216 */ 'b', '8', 0,
+  /* 219 */ 'a', '1', '9', 0,
+  /* 223 */ 'b', '1', '9', 0,
+  /* 227 */ 'a', '2', '9', 0,
+  /* 231 */ 'b', '2', '9', 0,
+  /* 235 */ 'a', '9', 0,
+  /* 238 */ 'b', '9', 0,
+  /* 241 */ 'g', 'p', 'l', 'y', 'a', 0,
+  /* 247 */ 'g', 'p', 'l', 'y', 'b', 0,
+  /* 253 */ 'r', 'i', 'l', 'c', 0,
+  /* 258 */ 't', 's', 'c', 'h', 0,
+  /* 263 */ 't', 's', 'c', 'l', 0,
+  /* 268 */ 'd', 'n', 'u', 'm', 0,
+  /* 273 */ 'r', 'e', 'p', 0,
+  /* 277 */ 'i', 'r', 'p', 0,
+  /* 281 */ 'n', 'r', 'p', 0,
+  /* 285 */ 'i', 's', 't', 'p', 0,
+  /* 290 */ 'e', 'c', 'r', 0,
+  /* 294 */ 'i', 'c', 'r', 0,
+  /* 298 */ 'd', 'i', 'e', 'r', 0,
+  /* 303 */ 'g', 'f', 'p', 'g', 'f', 'r', 0,
+  /* 310 */ 'a', 'm', 'r', 0,
+  /* 314 */ 'i', 'e', 'r', 'r', 0,
+  /* 319 */ 'c', 's', 'r', 0,
+  /* 323 */ 'i', 's', 'r', 0,
+  /* 327 */ 's', 's', 'r', 0,
+  /* 331 */ 'i', 't', 's', 'r', 0,
+  /* 336 */ 'n', 't', 's', 'r', 0,
+  };
+
+  static const uint16_t RegAsmOffset[] = {
+    310, 319, 298, 268, 290, 303, 241, 247, 294, 299, 314, 254, 277, 323, 
+    285, 331, 281, 336, 273, 253, 327, 258, 263, 332, 24, 54, 81, 103, 
+    125, 147, 169, 191, 213, 235, 0, 30, 65, 87, 109, 131, 153, 175, 
+    197, 219, 8, 38, 73, 95, 117, 139, 161, 183, 205, 227, 16, 46, 
+    27, 57, 84, 106, 128, 150, 172, 194, 216, 238, 4, 34, 69, 91, 
+    113, 135, 157, 179, 201, 223, 12, 42, 77, 99, 121, 143, 165, 187, 
+    209, 231, 20, 50, 60, 
+  };
+
+  return AsmStrs+RegAsmOffset[RegNo-1];
+#else
+  return NULL;
+#endif
+}
@@ -0,0 +1,298 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|*                                                                            *|
+|*Target Instruction Enum Values                                              *|
+|*                                                                            *|
+|* Automatically generated file, do not edit!                                 *|
+|*                                                                            *|
+\*===----------------------------------------------------------------------===*/
+
+
+#ifdef GET_INSTRINFO_ENUM
+#undef GET_INSTRINFO_ENUM
+
+enum {
+  TMS320C64x_PHI	= 0,
+  TMS320C64x_INLINEASM	= 1,
+  TMS320C64x_CFI_INSTRUCTION	= 2,
+  TMS320C64x_EH_LABEL	= 3,
+  TMS320C64x_GC_LABEL	= 4,
+  TMS320C64x_KILL	= 5,
+  TMS320C64x_EXTRACT_SUBREG	= 6,
+  TMS320C64x_INSERT_SUBREG	= 7,
+  TMS320C64x_IMPLICIT_DEF	= 8,
+  TMS320C64x_SUBREG_TO_REG	= 9,
+  TMS320C64x_COPY_TO_REGCLASS	= 10,
+  TMS320C64x_DBG_VALUE	= 11,
+  TMS320C64x_REG_SEQUENCE	= 12,
+  TMS320C64x_COPY	= 13,
+  TMS320C64x_BUNDLE	= 14,
+  TMS320C64x_LIFETIME_START	= 15,
+  TMS320C64x_LIFETIME_END	= 16,
+  TMS320C64x_STACKMAP	= 17,
+  TMS320C64x_PATCHPOINT	= 18,
+  TMS320C64x_LOAD_STACK_GUARD	= 19,
+  TMS320C64x_STATEPOINT	= 20,
+  TMS320C64x_FRAME_ALLOC	= 21,
+  TMS320C64x_ABS2_l2_rr	= 22,
+  TMS320C64x_ABS_l1_pp	= 23,
+  TMS320C64x_ABS_l1_rr	= 24,
+  TMS320C64x_ADD2_d2_rrr	= 25,
+  TMS320C64x_ADD2_l1_rrr_x2	= 26,
+  TMS320C64x_ADD2_s1_rrr	= 27,
+  TMS320C64x_ADD4_l1_rrr_x2	= 28,
+  TMS320C64x_ADDAB_d1_rir	= 29,
+  TMS320C64x_ADDAB_d1_rrr	= 30,
+  TMS320C64x_ADDAD_d1_rir	= 31,
+  TMS320C64x_ADDAD_d1_rrr	= 32,
+  TMS320C64x_ADDAH_d1_rir	= 33,
+  TMS320C64x_ADDAH_d1_rrr	= 34,
+  TMS320C64x_ADDAW_d1_rir	= 35,
+  TMS320C64x_ADDAW_d1_rrr	= 36,
+  TMS320C64x_ADDKPC_s3_iir	= 37,
+  TMS320C64x_ADDK_s2_ir	= 38,
+  TMS320C64x_ADDU_l1_rpp	= 39,
+  TMS320C64x_ADDU_l1_rrp_x2	= 40,
+  TMS320C64x_ADD_d1_rir	= 41,
+  TMS320C64x_ADD_d1_rrr	= 42,
+  TMS320C64x_ADD_d2_rir	= 43,
+  TMS320C64x_ADD_d2_rrr	= 44,
+  TMS320C64x_ADD_l1_ipp	= 45,
+  TMS320C64x_ADD_l1_irr	= 46,
+  TMS320C64x_ADD_l1_rpp	= 47,
+  TMS320C64x_ADD_l1_rrp_x2	= 48,
+  TMS320C64x_ADD_l1_rrr_x2	= 49,
+  TMS320C64x_ADD_s1_irr	= 50,
+  TMS320C64x_ADD_s1_rrr	= 51,
+  TMS320C64x_ANDN_d2_rrr	= 52,
+  TMS320C64x_ANDN_l1_rrr_x2	= 53,
+  TMS320C64x_ANDN_s4_rrr	= 54,
+  TMS320C64x_AND_d2_rir	= 55,
+  TMS320C64x_AND_d2_rrr	= 56,
+  TMS320C64x_AND_l1_irr	= 57,
+  TMS320C64x_AND_l1_rrr_x2	= 58,
+  TMS320C64x_AND_s1_irr	= 59,
+  TMS320C64x_AND_s1_rrr	= 60,
+  TMS320C64x_AVG2_m1_rrr	= 61,
+  TMS320C64x_AVGU4_m1_rrr	= 62,
+  TMS320C64x_BDEC_s8_ir	= 63,
+  TMS320C64x_BITC4_m2_rr	= 64,
+  TMS320C64x_BNOP_s10_ri	= 65,
+  TMS320C64x_BNOP_s9_ii	= 66,
+  TMS320C64x_BPOS_s8_ir	= 67,
+  TMS320C64x_B_s5_i	= 68,
+  TMS320C64x_B_s6_r	= 69,
+  TMS320C64x_B_s7_irp	= 70,
+  TMS320C64x_B_s7_nrp	= 71,
+  TMS320C64x_CLR_s15_riir	= 72,
+  TMS320C64x_CLR_s1_rrr	= 73,
+  TMS320C64x_CMPEQ2_s1_rrr	= 74,
+  TMS320C64x_CMPEQ4_s1_rrr	= 75,
+  TMS320C64x_CMPEQ_l1_ipr	= 76,
+  TMS320C64x_CMPEQ_l1_irr	= 77,
+  TMS320C64x_CMPEQ_l1_rpr	= 78,
+  TMS320C64x_CMPEQ_l1_rrr_x2	= 79,
+  TMS320C64x_CMPGT2_s1_rrr	= 80,
+  TMS320C64x_CMPGTU4_s1_rrr	= 81,
+  TMS320C64x_CMPGT_l1_ipr	= 82,
+  TMS320C64x_CMPGT_l1_irr	= 83,
+  TMS320C64x_CMPGT_l1_rpr	= 84,
+  TMS320C64x_CMPGT_l1_rrr_x2	= 85,
+  TMS320C64x_CMPLTU_l1_ipr	= 86,
+  TMS320C64x_CMPLTU_l1_irr	= 87,
+  TMS320C64x_CMPLTU_l1_rpr	= 88,
+  TMS320C64x_CMPLTU_l1_rrr_x2	= 89,
+  TMS320C64x_CMPLT_l1_ipr	= 90,
+  TMS320C64x_CMPLT_l1_irr	= 91,
+  TMS320C64x_CMPLT_l1_rpr	= 92,
+  TMS320C64x_CMPLT_l1_rrr_x2	= 93,
+  TMS320C64x_DEAL_m2_rr	= 94,
+  TMS320C64x_DOTP2_m1_rrp	= 95,
+  TMS320C64x_DOTP2_m1_rrr	= 96,
+  TMS320C64x_DOTPN2_m1_rrr	= 97,
+  TMS320C64x_DOTPNRSU2_m1_rrr	= 98,
+  TMS320C64x_DOTPRSU2_m1_rrr	= 99,
+  TMS320C64x_DOTPSU4_m1_rrr	= 100,
+  TMS320C64x_DOTPU4_m1_rrr	= 101,
+  TMS320C64x_EXTU_s15_riir	= 102,
+  TMS320C64x_EXTU_s1_rrr	= 103,
+  TMS320C64x_EXT_s15_riir	= 104,
+  TMS320C64x_EXT_s1_rrr	= 105,
+  TMS320C64x_GMPGTU_l1_ipr	= 106,
+  TMS320C64x_GMPGTU_l1_irr	= 107,
+  TMS320C64x_GMPGTU_l1_rpr	= 108,
+  TMS320C64x_GMPGTU_l1_rrr_x2	= 109,
+  TMS320C64x_GMPY4_m1_rrr	= 110,
+  TMS320C64x_LDBU_d5_mr	= 111,
+  TMS320C64x_LDBU_d6_mr	= 112,
+  TMS320C64x_LDB_d5_mr	= 113,
+  TMS320C64x_LDB_d6_mr	= 114,
+  TMS320C64x_LDDW_d7_mp	= 115,
+  TMS320C64x_LDHU_d5_mr	= 116,
+  TMS320C64x_LDHU_d6_mr	= 117,
+  TMS320C64x_LDH_d5_mr	= 118,
+  TMS320C64x_LDH_d6_mr	= 119,
+  TMS320C64x_LDNDW_d8_mp	= 120,
+  TMS320C64x_LDNW_d5_mr	= 121,
+  TMS320C64x_LDW_d5_mr	= 122,
+  TMS320C64x_LDW_d6_mr	= 123,
+  TMS320C64x_LMBD_l1_irr	= 124,
+  TMS320C64x_LMBD_l1_rrr_x2	= 125,
+  TMS320C64x_MAX2_l1_rrr_x2	= 126,
+  TMS320C64x_MAXU4_l1_rrr_x2	= 127,
+  TMS320C64x_MIN2_l1_rrr_x2	= 128,
+  TMS320C64x_MINU4_l1_rrr_x2	= 129,
+  TMS320C64x_MPY2_m1_rrp	= 130,
+  TMS320C64x_MPYHIR_m1_rrr	= 131,
+  TMS320C64x_MPYHI_m1_rrp	= 132,
+  TMS320C64x_MPYHLU_m4_rrr	= 133,
+  TMS320C64x_MPYHL_m4_rrr	= 134,
+  TMS320C64x_MPYHSLU_m4_rrr	= 135,
+  TMS320C64x_MPYHSU_m4_rrr	= 136,
+  TMS320C64x_MPYHULS_m4_rrr	= 137,
+  TMS320C64x_MPYHUS_m4_rrr	= 138,
+  TMS320C64x_MPYHU_m4_rrr	= 139,
+  TMS320C64x_MPYH_m4_rrr	= 140,
+  TMS320C64x_MPYLHU_m4_rrr	= 141,
+  TMS320C64x_MPYLH_m4_rrr	= 142,
+  TMS320C64x_MPYLIR_m1_rrr	= 143,
+  TMS320C64x_MPYLI_m1_rrp	= 144,
+  TMS320C64x_MPYLSHU_m4_rrr	= 145,
+  TMS320C64x_MPYLUHS_m4_rrr	= 146,
+  TMS320C64x_MPYSU4_m1_rrp	= 147,
+  TMS320C64x_MPYSU_m4_irr	= 148,
+  TMS320C64x_MPYSU_m4_rrr	= 149,
+  TMS320C64x_MPYU4_m1_rrp	= 150,
+  TMS320C64x_MPYUS_m4_rrr	= 151,
+  TMS320C64x_MPYU_m4_rrr	= 152,
+  TMS320C64x_MPY_m4_irr	= 153,
+  TMS320C64x_MPY_m4_rrr	= 154,
+  TMS320C64x_MVC_s1_rr	= 155,
+  TMS320C64x_MVC_s1_rr2	= 156,
+  TMS320C64x_MVD_m2_rr	= 157,
+  TMS320C64x_MVKLH_s12_ir	= 158,
+  TMS320C64x_MVKL_s12_ir	= 159,
+  TMS320C64x_MVK_d1_rr	= 160,
+  TMS320C64x_MVK_l2_ir	= 161,
+  TMS320C64x_NOP_n	= 162,
+  TMS320C64x_NORM_l1_pr	= 163,
+  TMS320C64x_NORM_l1_rr	= 164,
+  TMS320C64x_OR_d2_rir	= 165,
+  TMS320C64x_OR_d2_rrr	= 166,
+  TMS320C64x_OR_l1_irr	= 167,
+  TMS320C64x_OR_l1_rrr_x2	= 168,
+  TMS320C64x_OR_s1_irr	= 169,
+  TMS320C64x_OR_s1_rrr	= 170,
+  TMS320C64x_PACK2_l1_rrr_x2	= 171,
+  TMS320C64x_PACK2_s4_rrr	= 172,
+  TMS320C64x_PACKH2_l1_rrr_x2	= 173,
+  TMS320C64x_PACKH2_s1_rrr	= 174,
+  TMS320C64x_PACKH4_l1_rrr_x2	= 175,
+  TMS320C64x_PACKHL2_l1_rrr_x2	= 176,
+  TMS320C64x_PACKHL2_s1_rrr	= 177,
+  TMS320C64x_PACKL4_l1_rrr_x2	= 178,
+  TMS320C64x_PACKLH2_l1_rrr_x2	= 179,
+  TMS320C64x_PACKLH2_s1_rrr	= 180,
+  TMS320C64x_ROTL_m1_rir	= 181,
+  TMS320C64x_ROTL_m1_rrr	= 182,
+  TMS320C64x_SADD2_s4_rrr	= 183,
+  TMS320C64x_SADDU4_s4_rrr	= 184,
+  TMS320C64x_SADDUS2_s4_rrr	= 185,
+  TMS320C64x_SADD_l1_ipp	= 186,
+  TMS320C64x_SADD_l1_irr	= 187,
+  TMS320C64x_SADD_l1_rpp	= 188,
+  TMS320C64x_SADD_l1_rrr_x2	= 189,
+  TMS320C64x_SADD_s1_rrr	= 190,
+  TMS320C64x_SAT_l1_pr	= 191,
+  TMS320C64x_SET_s15_riir	= 192,
+  TMS320C64x_SET_s1_rrr	= 193,
+  TMS320C64x_SHFL_m2_rr	= 194,
+  TMS320C64x_SHLMB_l1_rrr_x2	= 195,
+  TMS320C64x_SHLMB_s4_rrr	= 196,
+  TMS320C64x_SHL_s1_pip	= 197,
+  TMS320C64x_SHL_s1_prp	= 198,
+  TMS320C64x_SHL_s1_rip	= 199,
+  TMS320C64x_SHL_s1_rir	= 200,
+  TMS320C64x_SHL_s1_rrp	= 201,
+  TMS320C64x_SHL_s1_rrr	= 202,
+  TMS320C64x_SHR2_s1_rir	= 203,
+  TMS320C64x_SHR2_s4_rrr	= 204,
+  TMS320C64x_SHRMB_l1_rrr_x2	= 205,
+  TMS320C64x_SHRMB_s4_rrr	= 206,
+  TMS320C64x_SHRU2_s1_rir	= 207,
+  TMS320C64x_SHRU2_s4_rrr	= 208,
+  TMS320C64x_SHRU_s1_pip	= 209,
+  TMS320C64x_SHRU_s1_prp	= 210,
+  TMS320C64x_SHRU_s1_rir	= 211,
+  TMS320C64x_SHRU_s1_rrr	= 212,
+  TMS320C64x_SHR_s1_pip	= 213,
+  TMS320C64x_SHR_s1_prp	= 214,
+  TMS320C64x_SHR_s1_rir	= 215,
+  TMS320C64x_SHR_s1_rrr	= 216,
+  TMS320C64x_SMPY2_m1_rrp	= 217,
+  TMS320C64x_SMPYHL_m4_rrr	= 218,
+  TMS320C64x_SMPYH_m4_rrr	= 219,
+  TMS320C64x_SMPYLH_m4_rrr	= 220,
+  TMS320C64x_SMPY_m4_rrr	= 221,
+  TMS320C64x_SPACK2_s4_rrr	= 222,
+  TMS320C64x_SPACKU4_s4_rrr	= 223,
+  TMS320C64x_SSHL_s1_rir	= 224,
+  TMS320C64x_SSHL_s1_rrr	= 225,
+  TMS320C64x_SSHVL_m1_rrr	= 226,
+  TMS320C64x_SSHVR_m1_rrr	= 227,
+  TMS320C64x_SSUB_l1_ipp	= 228,
+  TMS320C64x_SSUB_l1_irr	= 229,
+  TMS320C64x_SSUB_l1_rrr_x1	= 230,
+  TMS320C64x_SSUB_l1_rrr_x2	= 231,
+  TMS320C64x_STB_d5_rm	= 232,
+  TMS320C64x_STB_d6_rm	= 233,
+  TMS320C64x_STDW_d7_pm	= 234,
+  TMS320C64x_STH_d5_rm	= 235,
+  TMS320C64x_STH_d6_rm	= 236,
+  TMS320C64x_STNDW_d8_pm	= 237,
+  TMS320C64x_STNW_d5_rm	= 238,
+  TMS320C64x_STW_d5_rm	= 239,
+  TMS320C64x_STW_d6_rm	= 240,
+  TMS320C64x_SUB2_d2_rrr	= 241,
+  TMS320C64x_SUB2_l1_rrr_x2	= 242,
+  TMS320C64x_SUB2_s1_rrr	= 243,
+  TMS320C64x_SUB4_l1_rrr_x2	= 244,
+  TMS320C64x_SUBABS4_l1_rrr_x2	= 245,
+  TMS320C64x_SUBAB_d1_rir	= 246,
+  TMS320C64x_SUBAB_d1_rrr	= 247,
+  TMS320C64x_SUBAH_d1_rir	= 248,
+  TMS320C64x_SUBAH_d1_rrr	= 249,
+  TMS320C64x_SUBAW_d1_rir	= 250,
+  TMS320C64x_SUBAW_d1_rrr	= 251,
+  TMS320C64x_SUBC_l1_rrr_x2	= 252,
+  TMS320C64x_SUBU_l1_rrp_x1	= 253,
+  TMS320C64x_SUBU_l1_rrp_x2	= 254,
+  TMS320C64x_SUB_d1_rir	= 255,
+  TMS320C64x_SUB_d1_rrr	= 256,
+  TMS320C64x_SUB_d2_rrr	= 257,
+  TMS320C64x_SUB_l1_ipp	= 258,
+  TMS320C64x_SUB_l1_irr	= 259,
+  TMS320C64x_SUB_l1_rrp_x1	= 260,
+  TMS320C64x_SUB_l1_rrp_x2	= 261,
+  TMS320C64x_SUB_l1_rrr_x1	= 262,
+  TMS320C64x_SUB_l1_rrr_x2	= 263,
+  TMS320C64x_SUB_s1_irr	= 264,
+  TMS320C64x_SUB_s1_rrr	= 265,
+  TMS320C64x_SUB_s4_rrr	= 266,
+  TMS320C64x_SWAP4_l2_rr	= 267,
+  TMS320C64x_UNPKHU4_l2_rr	= 268,
+  TMS320C64x_UNPKHU4_s14_rr	= 269,
+  TMS320C64x_UNPKLU4_l2_rr	= 270,
+  TMS320C64x_UNPKLU4_s14_rr	= 271,
+  TMS320C64x_XOR_d2_rir	= 272,
+  TMS320C64x_XOR_d2_rrr	= 273,
+  TMS320C64x_XOR_l1_irr	= 274,
+  TMS320C64x_XOR_l1_rrr_x2	= 275,
+  TMS320C64x_XOR_s1_irr	= 276,
+  TMS320C64x_XOR_s1_rrr	= 277,
+  TMS320C64x_XPND2_m2_rr	= 278,
+  TMS320C64x_XPND4_m2_rr	= 279,
+  TMS320C64x_INSTRUCTION_LIST_END = 280
+};
+
+#endif // GET_INSTRINFO_ENUM
+
@@ -0,0 +1,277 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|*                                                                            *|
+|*Target Register Enum Values                                                 *|
+|*                                                                            *|
+|* Automatically generated file, do not edit!                                 *|
+|*                                                                            *|
+\*===----------------------------------------------------------------------===*/
+
+
+#ifdef GET_REGINFO_ENUM
+#undef GET_REGINFO_ENUM
+
+enum {
+  TMS320C64x_NoRegister,
+  TMS320C64x_AMR = 1,
+  TMS320C64x_CSR = 2,
+  TMS320C64x_DIER = 3,
+  TMS320C64x_DNUM = 4,
+  TMS320C64x_ECR = 5,
+  TMS320C64x_GFPGFR = 6,
+  TMS320C64x_GPLYA = 7,
+  TMS320C64x_GPLYB = 8,
+  TMS320C64x_ICR = 9,
+  TMS320C64x_IER = 10,
+  TMS320C64x_IERR = 11,
+  TMS320C64x_ILC = 12,
+  TMS320C64x_IRP = 13,
+  TMS320C64x_ISR = 14,
+  TMS320C64x_ISTP = 15,
+  TMS320C64x_ITSR = 16,
+  TMS320C64x_NRP = 17,
+  TMS320C64x_NTSR = 18,
+  TMS320C64x_REP = 19,
+  TMS320C64x_RILC = 20,
+  TMS320C64x_SSR = 21,
+  TMS320C64x_TSCH = 22,
+  TMS320C64x_TSCL = 23,
+  TMS320C64x_TSR = 24,
+  TMS320C64x_A0 = 25,
+  TMS320C64x_A1 = 26,
+  TMS320C64x_A2 = 27,
+  TMS320C64x_A3 = 28,
+  TMS320C64x_A4 = 29,
+  TMS320C64x_A5 = 30,
+  TMS320C64x_A6 = 31,
+  TMS320C64x_A7 = 32,
+  TMS320C64x_A8 = 33,
+  TMS320C64x_A9 = 34,
+  TMS320C64x_A10 = 35,
+  TMS320C64x_A11 = 36,
+  TMS320C64x_A12 = 37,
+  TMS320C64x_A13 = 38,
+  TMS320C64x_A14 = 39,
+  TMS320C64x_A15 = 40,
+  TMS320C64x_A16 = 41,
+  TMS320C64x_A17 = 42,
+  TMS320C64x_A18 = 43,
+  TMS320C64x_A19 = 44,
+  TMS320C64x_A20 = 45,
+  TMS320C64x_A21 = 46,
+  TMS320C64x_A22 = 47,
+  TMS320C64x_A23 = 48,
+  TMS320C64x_A24 = 49,
+  TMS320C64x_A25 = 50,
+  TMS320C64x_A26 = 51,
+  TMS320C64x_A27 = 52,
+  TMS320C64x_A28 = 53,
+  TMS320C64x_A29 = 54,
+  TMS320C64x_A30 = 55,
+  TMS320C64x_A31 = 56,
+  TMS320C64x_B0 = 57,
+  TMS320C64x_B1 = 58,
+  TMS320C64x_B2 = 59,
+  TMS320C64x_B3 = 60,
+  TMS320C64x_B4 = 61,
+  TMS320C64x_B5 = 62,
+  TMS320C64x_B6 = 63,
+  TMS320C64x_B7 = 64,
+  TMS320C64x_B8 = 65,
+  TMS320C64x_B9 = 66,
+  TMS320C64x_B10 = 67,
+  TMS320C64x_B11 = 68,
+  TMS320C64x_B12 = 69,
+  TMS320C64x_B13 = 70,
+  TMS320C64x_B14 = 71,
+  TMS320C64x_B15 = 72,
+  TMS320C64x_B16 = 73,
+  TMS320C64x_B17 = 74,
+  TMS320C64x_B18 = 75,
+  TMS320C64x_B19 = 76,
+  TMS320C64x_B20 = 77,
+  TMS320C64x_B21 = 78,
+  TMS320C64x_B22 = 79,
+  TMS320C64x_B23 = 80,
+  TMS320C64x_B24 = 81,
+  TMS320C64x_B25 = 82,
+  TMS320C64x_B26 = 83,
+  TMS320C64x_B27 = 84,
+  TMS320C64x_B28 = 85,
+  TMS320C64x_B29 = 86,
+  TMS320C64x_B30 = 87,
+  TMS320C64x_B31 = 88,
+  TMS320C64x_PCE1 = 89,
+  TMS320C64x_NUM_TARGET_REGS 	// 90
+};
+
+// Register classes
+enum {
+  TMS320C64x_GPRegsRegClassID = 0,
+  TMS320C64x_AFRegsRegClassID = 1,
+  TMS320C64x_BFRegsRegClassID = 2,
+  TMS320C64x_ControlRegsRegClassID = 3,
+
+  };
+#endif // GET_REGINFO_ENUM
+
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|*                                                                            *|
+|*MC Register Information                                                     *|
+|*                                                                            *|
+|* Automatically generated file, do not edit!                                 *|
+|*                                                                            *|
+\*===----------------------------------------------------------------------===*/
+
+
+#ifdef GET_REGINFO_MC_DESC
+#undef GET_REGINFO_MC_DESC
+
+static const MCPhysReg TMS320C64xRegDiffLists[] = {
+  /* 0 */ -1, 0,
+};
+
+static const uint16_t TMS320C64xSubRegIdxLists[] = {
+  /* 0 */ 0,
+};
+
+static const MCRegisterDesc TMS320C64xRegDesc[] = { // Descriptors
+  { 3, 0, 0, 0, 0 },
+  { 310, 1, 1, 0, 1 },
+  { 319, 1, 1, 0, 1 },
+  { 298, 1, 1, 0, 1 },
+  { 268, 1, 1, 0, 1 },
+  { 290, 1, 1, 0, 1 },
+  { 303, 1, 1, 0, 1 },
+  { 241, 1, 1, 0, 1 },
+  { 247, 1, 1, 0, 1 },
+  { 294, 1, 1, 0, 1 },
+  { 299, 1, 1, 0, 1 },
+  { 314, 1, 1, 0, 1 },
+  { 254, 1, 1, 0, 1 },
+  { 277, 1, 1, 0, 1 },
+  { 323, 1, 1, 0, 1 },
+  { 285, 1, 1, 0, 1 },
+  { 331, 1, 1, 0, 1 },
+  { 281, 1, 1, 0, 1 },
+  { 336, 1, 1, 0, 1 },
+  { 273, 1, 1, 0, 1 },
+  { 253, 1, 1, 0, 1 },
+  { 327, 1, 1, 0, 1 },
+  { 258, 1, 1, 0, 1 },
+  { 263, 1, 1, 0, 1 },
+  { 332, 1, 1, 0, 1 },
+  { 24, 1, 1, 0, 1 },
+  { 54, 1, 1, 0, 1 },
+  { 81, 1, 1, 0, 1 },
+  { 103, 1, 1, 0, 1 },
+  { 125, 1, 1, 0, 1 },
+  { 147, 1, 1, 0, 1 },
+  { 169, 1, 1, 0, 1 },
+  { 191, 1, 1, 0, 1 },
+  { 213, 1, 1, 0, 1 },
+  { 235, 1, 1, 0, 1 },
+  { 0, 1, 1, 0, 1 },
+  { 30, 1, 1, 0, 1 },
+  { 65, 1, 1, 0, 1 },
+  { 87, 1, 1, 0, 1 },
+  { 109, 1, 1, 0, 1 },
+  { 131, 1, 1, 0, 1 },
+  { 153, 1, 1, 0, 1 },
+  { 175, 1, 1, 0, 1 },
+  { 197, 1, 1, 0, 1 },
+  { 219, 1, 1, 0, 1 },
+  { 8, 1, 1, 0, 1 },
+  { 38, 1, 1, 0, 1 },
+  { 73, 1, 1, 0, 1 },
+  { 95, 1, 1, 0, 1 },
+  { 117, 1, 1, 0, 1 },
+  { 139, 1, 1, 0, 1 },
+  { 161, 1, 1, 0, 1 },
+  { 183, 1, 1, 0, 1 },
+  { 205, 1, 1, 0, 1 },
+  { 227, 1, 1, 0, 1 },
+  { 16, 1, 1, 0, 1 },
+  { 46, 1, 1, 0, 1 },
+  { 27, 1, 1, 0, 1 },
+  { 57, 1, 1, 0, 1 },
+  { 84, 1, 1, 0, 1 },
+  { 106, 1, 1, 0, 1 },
+  { 128, 1, 1, 0, 1 },
+  { 150, 1, 1, 0, 1 },
+  { 172, 1, 1, 0, 1 },
+  { 194, 1, 1, 0, 1 },
+  { 216, 1, 1, 0, 1 },
+  { 238, 1, 1, 0, 1 },
+  { 4, 1, 1, 0, 1 },
+  { 34, 1, 1, 0, 1 },
+  { 69, 1, 1, 0, 1 },
+  { 91, 1, 1, 0, 1 },
+  { 113, 1, 1, 0, 1 },
+  { 135, 1, 1, 0, 1 },
+  { 157, 1, 1, 0, 1 },
+  { 179, 1, 1, 0, 1 },
+  { 201, 1, 1, 0, 1 },
+  { 223, 1, 1, 0, 1 },
+  { 12, 1, 1, 0, 1 },
+  { 42, 1, 1, 0, 1 },
+  { 77, 1, 1, 0, 1 },
+  { 99, 1, 1, 0, 1 },
+  { 121, 1, 1, 0, 1 },
+  { 143, 1, 1, 0, 1 },
+  { 165, 1, 1, 0, 1 },
+  { 187, 1, 1, 0, 1 },
+  { 209, 1, 1, 0, 1 },
+  { 231, 1, 1, 0, 1 },
+  { 20, 1, 1, 0, 1 },
+  { 50, 1, 1, 0, 1 },
+  { 60, 1, 1, 0, 1 },
+};
+
+// GPRegs Register Class...
+static const MCPhysReg GPRegs[] = {
+  TMS320C64x_A0, TMS320C64x_A1, TMS320C64x_A2, TMS320C64x_A3, TMS320C64x_A4, TMS320C64x_A5, TMS320C64x_A6, TMS320C64x_A7, TMS320C64x_A8, TMS320C64x_A9, TMS320C64x_A10, TMS320C64x_A11, TMS320C64x_A12, TMS320C64x_A13, TMS320C64x_A14, TMS320C64x_A15, TMS320C64x_A16, TMS320C64x_A17, TMS320C64x_A18, TMS320C64x_A19, TMS320C64x_A20, TMS320C64x_A21, TMS320C64x_A22, TMS320C64x_A23, TMS320C64x_A24, TMS320C64x_A25, TMS320C64x_A26, TMS320C64x_A27, TMS320C64x_A28, TMS320C64x_A29, TMS320C64x_A30, TMS320C64x_A31, TMS320C64x_B0, TMS320C64x_B1, TMS320C64x_B2, TMS320C64x_B3, TMS320C64x_B4, TMS320C64x_B5, TMS320C64x_B6, TMS320C64x_B7, TMS320C64x_B8, TMS320C64x_B9, TMS320C64x_B10, TMS320C64x_B11, TMS320C64x_B12, TMS320C64x_B13, TMS320C64x_B14, TMS320C64x_B15, TMS320C64x_B16, TMS320C64x_B17, TMS320C64x_B18, TMS320C64x_B19, TMS320C64x_B20, TMS320C64x_B21, TMS320C64x_B22, TMS320C64x_B23, TMS320C64x_B24, TMS320C64x_B25, TMS320C64x_B26, TMS320C64x_B27, TMS320C64x_B28, TMS320C64x_B29, TMS320C64x_B30, TMS320C64x_B31,
+};
+
+// GPRegs Bit set.
+static const uint8_t GPRegsBits[] = {
+  0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01,
+};
+
+// AFRegs Register Class...
+static const MCPhysReg AFRegs[] = {
+  TMS320C64x_A0, TMS320C64x_A1, TMS320C64x_A2, TMS320C64x_A3, TMS320C64x_A4, TMS320C64x_A5, TMS320C64x_A6, TMS320C64x_A7, TMS320C64x_A8, TMS320C64x_A9, TMS320C64x_A10, TMS320C64x_A11, TMS320C64x_A12, TMS320C64x_A13, TMS320C64x_A14, TMS320C64x_A15, TMS320C64x_A16, TMS320C64x_A17, TMS320C64x_A18, TMS320C64x_A19, TMS320C64x_A20, TMS320C64x_A21, TMS320C64x_A22, TMS320C64x_A23, TMS320C64x_A24, TMS320C64x_A25, TMS320C64x_A26, TMS320C64x_A27, TMS320C64x_A28, TMS320C64x_A29, TMS320C64x_A30, TMS320C64x_A31,
+};
+
+// AFRegs Bit set.
+static const uint8_t AFRegsBits[] = {
+  0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
+};
+
+// BFRegs Register Class...
+static const MCPhysReg BFRegs[] = {
+  TMS320C64x_B0, TMS320C64x_B1, TMS320C64x_B2, TMS320C64x_B3, TMS320C64x_B4, TMS320C64x_B5, TMS320C64x_B6, TMS320C64x_B7, TMS320C64x_B8, TMS320C64x_B9, TMS320C64x_B10, TMS320C64x_B11, TMS320C64x_B12, TMS320C64x_B13, TMS320C64x_B14, TMS320C64x_B15, TMS320C64x_B16, TMS320C64x_B17, TMS320C64x_B18, TMS320C64x_B19, TMS320C64x_B20, TMS320C64x_B21, TMS320C64x_B22, TMS320C64x_B23, TMS320C64x_B24, TMS320C64x_B25, TMS320C64x_B26, TMS320C64x_B27, TMS320C64x_B28, TMS320C64x_B29, TMS320C64x_B30, TMS320C64x_B31,
+};
+
+// BFRegs Bit set.
+static const uint8_t BFRegsBits[] = {
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
+};
+
+// ControlRegs Register Class...
+static const MCPhysReg ControlRegs[] = {
+  TMS320C64x_AMR, TMS320C64x_CSR, TMS320C64x_DIER, TMS320C64x_DNUM, TMS320C64x_ECR, TMS320C64x_GFPGFR, TMS320C64x_GPLYA, TMS320C64x_GPLYB, TMS320C64x_ICR, TMS320C64x_IER, TMS320C64x_IERR, TMS320C64x_ILC, TMS320C64x_IRP, TMS320C64x_ISR, TMS320C64x_ISTP, TMS320C64x_ITSR, TMS320C64x_NRP, TMS320C64x_NTSR, TMS320C64x_PCE1, TMS320C64x_REP, TMS320C64x_RILC, TMS320C64x_SSR, TMS320C64x_TSCH, TMS320C64x_TSCL, TMS320C64x_TSR,
+};
+
+// ControlRegs Bit set.
+static const uint8_t ControlRegsBits[] = {
+  0xfe, 0xff, 0xff, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
+};
+
+static const MCRegisterClass TMS320C64xMCRegisterClasses[] = {
+  { GPRegs, GPRegsBits, TMS320C64x_GPRegsRegClassID },
+  { AFRegs, AFRegsBits, TMS320C64x_AFRegsRegClassID },
+  { BFRegs, BFRegsBits, TMS320C64x_BFRegsRegClassID },
+  { ControlRegs, ControlRegsBits, TMS320C64x_ControlRegsRegClassID },
+};
+
+#endif // GET_REGINFO_MC_DESC
@@ -0,0 +1,568 @@
+/* Capstone Disassembly Engine */
+/* TMS320C64x Backend by Fotis Loukos <me@fotisl.com> 2016 */
+
+#ifdef CAPSTONE_HAS_TMS320C64X
+
+#include <ctype.h>
+#include <string.h>
+
+#include "TMS320C64xInstPrinter.h"
+#include "../../MCInst.h"
+#include "../../utils.h"
+#include "../../SStream.h"
+#include "../../MCRegisterInfo.h"
+#include "../../MathExtras.h"
+#include "TMS320C64xMapping.h"
+
+#include "capstone/tms320c64x.h"
+
+static const char *getRegisterName(unsigned RegNo);
+static void printOperand(MCInst *MI, unsigned OpNo, SStream *O);
+static void printMemOperand(MCInst *MI, unsigned OpNo, SStream *O);
+static void printMemOperand2(MCInst *MI, unsigned OpNo, SStream *O);
+static void printRegPair(MCInst *MI, unsigned OpNo, SStream *O);
+
+void TMS320C64x_post_printer(csh ud, cs_insn *insn, SStream *insn_asm, MCInst *mci)
+{
+	SStream ss;
+	const char *op_str_ptr, *p2;
+	char tmp[8] = { 0 };
+	unsigned int unit = 0;
+	int i;
+	cs_tms320c64x *tms320c64x;
+
+	if (mci->csh->detail_opt) {
+		tms320c64x = &mci->flat_insn->detail->tms320c64x;
+
+		for (i = 0; i < insn->detail->groups_count; i++) {
+			switch(insn->detail->groups[i]) {
+				case TMS320C64X_GRP_FUNIT_D:
+					unit = TMS320C64X_FUNIT_D;
+					break;
+				case TMS320C64X_GRP_FUNIT_L:
+					unit = TMS320C64X_FUNIT_L;
+					break;
+				case TMS320C64X_GRP_FUNIT_M:
+					unit = TMS320C64X_FUNIT_M;
+					break;
+				case TMS320C64X_GRP_FUNIT_S:
+					unit = TMS320C64X_FUNIT_S;
+					break;
+				case TMS320C64X_GRP_FUNIT_NO:
+					unit = TMS320C64X_FUNIT_NO;
+					break;
+			}
+			if (unit != 0)
+				break;
+		}
+		tms320c64x->funit.unit = unit;
+
+		SStream_Init(&ss);
+		if (tms320c64x->condition.reg != TMS320C64X_REG_INVALID)
+			SStream_concat(&ss, "[%c%s]|", (tms320c64x->condition.zero == 1) ? '!' : '|', cs_reg_name(ud, tms320c64x->condition.reg));
+
+		// Sorry for all the fixes below. I don't have time to add more helper SStream functions.
+		// Before that they messed around with the private buffer of the stream.
+		// So it is better now. But still not efficient.
+		op_str_ptr = strchr(SStream_rbuf(insn_asm), '\t');
+
+		if ((op_str_ptr != NULL) && (((p2 = strchr(op_str_ptr, '[')) != NULL) || ((p2 = strchr(op_str_ptr, '(')) != NULL))) {
+			while ((p2 > op_str_ptr) && ((*p2 != 'a') && (*p2 != 'b')))
+				p2--;
+			if (p2 == op_str_ptr) {
+				SStream_Flush(insn_asm, NULL);
+				SStream_concat0(insn_asm, "Invalid!");
+				return;
+			}
+			if (*p2 == 'a')
+				strncpy(tmp, "1T", sizeof(tmp));
+			else
+				strncpy(tmp, "2T", sizeof(tmp));
+		} else {
+			tmp[0] = '\0';
+		}
+		SStream mnem_post = { 0 };
+		SStream_Init(&mnem_post);
+		switch(tms320c64x->funit.unit) {
+			case TMS320C64X_FUNIT_D:
+				SStream_concat(&mnem_post, ".D%s%u", tmp, tms320c64x->funit.side);
+				break;
+			case TMS320C64X_FUNIT_L:
+				SStream_concat(&mnem_post, ".L%s%u", tmp, tms320c64x->funit.side);
+				break;
+			case TMS320C64X_FUNIT_M:
+				SStream_concat(&mnem_post, ".M%s%u", tmp, tms320c64x->funit.side);
+				break;
+			case TMS320C64X_FUNIT_S:
+				SStream_concat(&mnem_post, ".S%s%u", tmp, tms320c64x->funit.side);
+				break;
+		}
+		if (tms320c64x->funit.crosspath > 0)
+			SStream_concat0(&mnem_post, "X");
+
+		if (op_str_ptr != NULL) {
+			// There is an op_str
+			SStream_concat1(&mnem_post, '\t');
+			SStream_replc_str(insn_asm, '\t', SStream_rbuf(&mnem_post));
+		}
+
+		if (tms320c64x->parallel != 0)
+			SStream_concat0(insn_asm, "\t||");
+		SStream_concat0(&ss, SStream_rbuf(insn_asm));
+		SStream_Flush(insn_asm, NULL);
+		SStream_concat0(insn_asm, SStream_rbuf(&ss));
+	}
+}
+
+#define PRINT_ALIAS_INSTR
+#include "TMS320C64xGenAsmWriter.inc"
+
+#define GET_INSTRINFO_ENUM
+#include "TMS320C64xGenInstrInfo.inc"
+
+static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
+{
+	MCOperand *Op = MCInst_getOperand(MI, OpNo);
+	unsigned reg;
+
+	if (MCOperand_isReg(Op)) {
+		reg = MCOperand_getReg(Op);
+		if ((MCInst_getOpcode(MI) == TMS320C64x_MVC_s1_rr) && (OpNo == 1)) {
+			switch(reg) {
+				case TMS320C64X_REG_EFR:
+					SStream_concat0(O, "EFR");
+					break;
+				case TMS320C64X_REG_IFR:
+					SStream_concat0(O, "IFR");
+					break;
+				default:
+					SStream_concat0(O, getRegisterName(reg));
+					break;
+			}
+		} else {
+			SStream_concat0(O, getRegisterName(reg));
+		}
+
+		if (MI->csh->detail_opt) {
+			MI->flat_insn->detail->tms320c64x.operands[MI->flat_insn->detail->tms320c64x.op_count].type = TMS320C64X_OP_REG;
+			MI->flat_insn->detail->tms320c64x.operands[MI->flat_insn->detail->tms320c64x.op_count].reg = reg;
+			MI->flat_insn->detail->tms320c64x.op_count++;
+		}
+	} else if (MCOperand_isImm(Op)) {
+		int64_t Imm = MCOperand_getImm(Op);
+
+		if (Imm >= 0) {
+			if (Imm > HEX_THRESHOLD)
+				SStream_concat(O, "0x%"PRIx64, Imm);
+			else
+				SStream_concat(O, "%"PRIu64, Imm);
+		} else {
+			if (Imm < -HEX_THRESHOLD)
+				SStream_concat(O, "-0x%"PRIx64, -Imm);
+			else
+				SStream_concat(O, "-%"PRIu64, -Imm);
+		}
+
+		if (MI->csh->detail_opt) {
+			MI->flat_insn->detail->tms320c64x.operands[MI->flat_insn->detail->tms320c64x.op_count].type = TMS320C64X_OP_IMM;
+			MI->flat_insn->detail->tms320c64x.operands[MI->flat_insn->detail->tms320c64x.op_count].imm = Imm;
+			MI->flat_insn->detail->tms320c64x.op_count++;
+		}
+	}
+}
+
+static void printMemOperand(MCInst *MI, unsigned OpNo, SStream *O)
+{
+	MCOperand *Op = MCInst_getOperand(MI, OpNo);
+	int64_t Val = MCOperand_getImm(Op);
+	unsigned scaled, base, offset, mode, unit;
+	cs_tms320c64x *tms320c64x;
+	char st, nd;
+
+	scaled = (Val >> 19) & 1;
+	base = (Val >> 12) & 0x7f;
+	offset = (Val >> 5) & 0x7f;
+	mode = (Val >> 1) & 0xf;
+	unit = Val & 1;
+
+	if (scaled) {
+		st = '[';
+		nd = ']';
+	} else {
+		st = '(';
+		nd = ')';
+	}
+
+	switch(mode) {
+		case 0:
+			SStream_concat(O, "*-%s%c%u%c", getRegisterName(base), st, offset, nd);
+			break;
+		case 1:
+			SStream_concat(O, "*+%s%c%u%c", getRegisterName(base), st, offset, nd);
+			break;
+		case 4:
+			SStream_concat(O, "*-%s%c%s%c", getRegisterName(base), st, getRegisterName(offset), nd);
+			break;
+		case 5:
+			SStream_concat(O, "*+%s%c%s%c", getRegisterName(base), st, getRegisterName(offset), nd);
+			break;
+		case 8:
+			SStream_concat(O, "*--%s%c%u%c", getRegisterName(base), st, offset, nd);
+			break;
+		case 9:
+			SStream_concat(O, "*++%s%c%u%c", getRegisterName(base), st, offset, nd);
+			break;
+		case 10:
+			SStream_concat(O, "*%s--%c%u%c", getRegisterName(base), st, offset, nd);
+			break;
+		case 11:
+			SStream_concat(O, "*%s++%c%u%c", getRegisterName(base), st, offset, nd);
+			break;
+		case 12:
+			SStream_concat(O, "*--%s%c%s%c", getRegisterName(base), st, getRegisterName(offset), nd);
+			break;
+		case 13:
+			SStream_concat(O, "*++%s%c%s%c", getRegisterName(base), st, getRegisterName(offset), nd);
+			break;
+		case 14:
+			SStream_concat(O, "*%s--%c%s%c", getRegisterName(base), st, getRegisterName(offset), nd);
+			break;
+		case 15:
+			SStream_concat(O, "*%s++%c%s%c", getRegisterName(base), st, getRegisterName(offset), nd);
+			break;
+	}
+
+	if (MI->csh->detail_opt) {
+		tms320c64x = &MI->flat_insn->detail->tms320c64x;
+
+		tms320c64x->operands[tms320c64x->op_count].type = TMS320C64X_OP_MEM;
+		tms320c64x->operands[tms320c64x->op_count].mem.base = base;
+		tms320c64x->operands[tms320c64x->op_count].mem.disp = offset;
+		tms320c64x->operands[tms320c64x->op_count].mem.unit = unit + 1;
+		tms320c64x->operands[tms320c64x->op_count].mem.scaled = scaled;
+		switch(mode) {
+			case 0:
+				tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT;
+				tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_BW;
+				tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_NO;
+				break;
+			case 1:
+				tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT;
+				tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW;
+				tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_NO;
+				break;
+			case 4:
+				tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_REGISTER;
+				tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_BW;
+				tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_NO;
+				break;
+			case 5:
+				tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_REGISTER;
+				tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW;
+				tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_NO;
+				break;
+			case 8:
+				tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT;
+				tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_BW;
+				tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_PRE;
+				break;
+			case 9:
+				tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT;
+				tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW;
+				tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_PRE;
+				break;
+			case 10:
+				tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT;
+				tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_BW;
+				tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_POST;
+				break;
+			case 11:
+				tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT;
+				tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW;
+				tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_POST;
+				break;
+			case 12:
+				tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_REGISTER;
+				tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_BW;
+				tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_PRE;
+				break;
+			case 13:
+				tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_REGISTER;
+				tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW;
+				tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_PRE;
+				break;
+			case 14:
+				tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_REGISTER;
+				tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_BW;
+				tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_POST;
+				break;
+			case 15:
+				tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_REGISTER;
+				tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW;
+				tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_POST;
+				break;
+		}
+		tms320c64x->op_count++;
+	}
+}
+
+static void printMemOperand2(MCInst *MI, unsigned OpNo, SStream *O)
+{
+	MCOperand *Op = MCInst_getOperand(MI, OpNo);
+	int64_t Val = MCOperand_getImm(Op);
+	uint16_t offset;
+	unsigned basereg;
+	cs_tms320c64x *tms320c64x;
+
+	basereg = Val & 0x7f;
+	offset = (Val >> 7) & 0x7fff;
+	SStream_concat(O, "*+%s[0x%x]", getRegisterName(basereg), offset);
+
+	if (MI->csh->detail_opt) {
+		tms320c64x = &MI->flat_insn->detail->tms320c64x;
+
+		tms320c64x->operands[tms320c64x->op_count].type = TMS320C64X_OP_MEM;
+		tms320c64x->operands[tms320c64x->op_count].mem.base = basereg;
+		tms320c64x->operands[tms320c64x->op_count].mem.unit = 2;
+		tms320c64x->operands[tms320c64x->op_count].mem.disp = offset;
+		tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT;
+		tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW;
+		tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_NO;
+		tms320c64x->op_count++;
+	}
+}
+
+static void printRegPair(MCInst *MI, unsigned OpNo, SStream *O)
+{
+	MCOperand *Op = MCInst_getOperand(MI, OpNo);
+	unsigned reg = MCOperand_getReg(Op);
+	cs_tms320c64x *tms320c64x;
+
+	SStream_concat(O, "%s:%s", getRegisterName(reg + 1), getRegisterName(reg));
+
+	if (MI->csh->detail_opt) {
+		tms320c64x = &MI->flat_insn->detail->tms320c64x;
+
+		tms320c64x->operands[tms320c64x->op_count].type = TMS320C64X_OP_REGPAIR;
+		tms320c64x->operands[tms320c64x->op_count].reg = reg;
+		tms320c64x->op_count++;
+	}
+}
+
+static bool printAliasInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
+{
+	unsigned opcode = MCInst_getOpcode(MI);
+	MCOperand *op;
+
+	switch(opcode) {
+		/* ADD.Dx -i, x, y -> SUB.Dx x, i, y */
+		case TMS320C64x_ADD_d2_rir:
+		/* ADD.L -i, x, y -> SUB.L x, i, y */
+		case TMS320C64x_ADD_l1_irr:
+		case TMS320C64x_ADD_l1_ipp:
+		/* ADD.S -i, x, y -> SUB.S x, i, y */
+		case TMS320C64x_ADD_s1_irr:
+			if ((MCInst_getNumOperands(MI) == 3) &&
+				MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+				MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+				MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+				(MCOperand_getImm(MCInst_getOperand(MI, 2)) < 0)) {
+
+				MCInst_setOpcodePub(MI, TMS320C64X_INS_SUB);
+				op = MCInst_getOperand(MI, 2);
+				MCOperand_setImm(op, -MCOperand_getImm(op));
+
+				SStream_concat0(O, "SUB\t");
+				printOperand(MI, 1, O);
+				SStream_concat0(O, ", ");
+				printOperand(MI, 2, O);
+				SStream_concat0(O, ", ");
+				printOperand(MI, 0, O);
+
+				return true;
+			}
+			break;
+	}
+	switch(opcode) {
+		/* ADD.D 0, x, y -> MV.D x, y */
+		case TMS320C64x_ADD_d1_rir:
+		/* OR.D x, 0, y -> MV.D x, y */
+		case TMS320C64x_OR_d2_rir:
+		/* ADD.L 0, x, y -> MV.L x, y */
+		case TMS320C64x_ADD_l1_irr:
+		case TMS320C64x_ADD_l1_ipp:
+		/* OR.L 0, x, y -> MV.L x, y */
+		case TMS320C64x_OR_l1_irr:
+		/* ADD.S 0, x, y -> MV.S x, y */
+		case TMS320C64x_ADD_s1_irr:
+		/* OR.S 0, x, y -> MV.S x, y */
+		case TMS320C64x_OR_s1_irr:
+			if ((MCInst_getNumOperands(MI) == 3) &&
+				MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+				MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+				MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+				(MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0)) {
+
+				MCInst_setOpcodePub(MI, TMS320C64X_INS_MV);
+				MI->size--;
+
+				SStream_concat0(O, "MV\t");
+				printOperand(MI, 1, O);
+				SStream_concat0(O, ", ");
+				printOperand(MI, 0, O);
+
+				return true;
+			}
+			break;
+	}
+	switch(opcode) {
+		/* XOR.D -1, x, y -> NOT.D x, y */
+		case TMS320C64x_XOR_d2_rir:
+		/* XOR.L -1, x, y -> NOT.L x, y */
+		case TMS320C64x_XOR_l1_irr:
+		/* XOR.S -1, x, y -> NOT.S x, y */
+		case TMS320C64x_XOR_s1_irr:
+			if ((MCInst_getNumOperands(MI) == 3) &&
+				MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+				MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+				MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+				(MCOperand_getImm(MCInst_getOperand(MI, 2)) == -1)) {
+
+				MCInst_setOpcodePub(MI, TMS320C64X_INS_NOT);
+				MI->size--;
+
+				SStream_concat0(O, "NOT\t");
+				printOperand(MI, 1, O);
+				SStream_concat0(O, ", ");
+				printOperand(MI, 0, O);
+
+				return true;
+			}
+			break;
+	}
+	switch(opcode) {
+		/* MVK.D 0, x -> ZERO.D x */
+		case TMS320C64x_MVK_d1_rr:
+		/* MVK.L 0, x -> ZERO.L x */
+		case TMS320C64x_MVK_l2_ir:
+			if ((MCInst_getNumOperands(MI) == 2) &&
+				MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+				MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
+				(MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0)) {
+
+				MCInst_setOpcodePub(MI, TMS320C64X_INS_ZERO);
+				MI->size--;
+
+				SStream_concat0(O, "ZERO\t");
+				printOperand(MI, 0, O);
+
+				return true;
+			}
+			break;
+	}
+	switch(opcode) {
+		/* SUB.L x, x, y -> ZERO.L y */
+		case TMS320C64x_SUB_l1_rrp_x1:
+		/* SUB.S x, x, y -> ZERO.S y */
+		case TMS320C64x_SUB_s1_rrr:
+			if ((MCInst_getNumOperands(MI) == 3) &&
+				MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+				MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+				MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+				(MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 2)))) {
+
+				MCInst_setOpcodePub(MI, TMS320C64X_INS_ZERO);
+				MI->size -= 2;
+
+				SStream_concat0(O, "ZERO\t");
+				printOperand(MI, 0, O);
+
+				return true;
+			}
+			break;
+	}
+	switch(opcode) {
+		/* SUB.L 0, x, y -> NEG.L x, y */
+		case TMS320C64x_SUB_l1_irr:
+		case TMS320C64x_SUB_l1_ipp:
+		/* SUB.S 0, x, y -> NEG.S x, y */
+		case TMS320C64x_SUB_s1_irr:
+			if ((MCInst_getNumOperands(MI) == 3) &&
+				MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+				MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+				MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+				(MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0)) {
+
+				MCInst_setOpcodePub(MI, TMS320C64X_INS_NEG);
+				MI->size--;
+
+				SStream_concat0(O, "NEG\t");
+				printOperand(MI, 1, O);
+				SStream_concat0(O, ", ");
+				printOperand(MI, 0, O);
+
+				return true;
+			}
+			break;
+	}
+	switch(opcode) {
+		/* PACKLH2.L x, x, y -> SWAP2.L x, y */
+		case TMS320C64x_PACKLH2_l1_rrr_x2:
+		/* PACKLH2.S x, x, y -> SWAP2.S x, y */
+		case TMS320C64x_PACKLH2_s1_rrr:
+			if ((MCInst_getNumOperands(MI) == 3) &&
+				MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+				MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+				MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+				(MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 2)))) {
+
+				MCInst_setOpcodePub(MI, TMS320C64X_INS_SWAP2);
+				MI->size--;
+
+				SStream_concat0(O, "SWAP2\t");
+				printOperand(MI, 1, O);
+				SStream_concat0(O, ", ");
+				printOperand(MI, 0, O);
+
+				return true;
+			}
+			break;
+	}
+	switch(opcode) {
+		/* NOP 16 -> IDLE */
+		/* NOP 1 -> NOP */
+		case TMS320C64x_NOP_n:
+			if ((MCInst_getNumOperands(MI) == 1) &&
+				MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
+				(MCOperand_getReg(MCInst_getOperand(MI, 0)) == 16)) {
+
+				MCInst_setOpcodePub(MI, TMS320C64X_INS_IDLE);
+				MI->size--;
+
+				SStream_concat0(O, "IDLE");
+
+				return true;
+			}
+			if ((MCInst_getNumOperands(MI) == 1) &&
+				MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
+				(MCOperand_getReg(MCInst_getOperand(MI, 0)) == 1)) {
+
+				MI->size--;
+
+				SStream_concat0(O, "NOP");
+
+				return true;
+			}
+			break;
+	}
+
+	return false;
+}
+
+void TMS320C64x_printInst(MCInst *MI, SStream *O, void *Info)
+{
+	if (!printAliasInstruction(MI, O, Info))
+		printInstruction(MI, O, Info);
+}
+
+#endif
@@ -0,0 +1,15 @@
+/* Capstone Disassembly Engine */
+/* TMS320C64x Backend by Fotis Loukos <me@fotisl.com> 2016 */
+
+#ifndef CS_TMS320C64XINSTPRINTER_H
+#define CS_TMS320C64XINSTPRINTER_H
+
+#include "../../MCInst.h"
+#include "../../MCRegisterInfo.h"
+#include "../../SStream.h"
+
+void TMS320C64x_printInst(MCInst *MI, SStream *O, void *Info);
+
+void TMS320C64x_post_printer(csh ud, cs_insn *insn, SStream *insn_asm, MCInst *mci);
+
+#endif
@@ -0,0 +1,26 @@
+/* Capstone Disassembly Engine */
+/* TMS320C64x Backend by Fotis Loukos <me@fotisl.com> 2016 */
+
+#ifndef CS_TMS320C64X_MAP_H
+#define CS_TMS320C64X_MAP_H
+
+#include "capstone/capstone.h"
+
+// return name of register in friendly string
+const char *TMS320C64x_reg_name(csh handle, unsigned int reg);
+
+// given internal insn id, return public instruction info
+void TMS320C64x_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
+
+const char *TMS320C64x_insn_name(csh handle, unsigned int id);
+
+const char *TMS320C64x_group_name(csh handle, unsigned int id);
+
+// map internal raw register to 'public' register
+tms320c64x_reg TMS320C64x_map_register(unsigned int r);
+
+// map register name to register ID
+tms320c64x_reg TMS320C64x_reg_id(char *name);
+
+#endif
+
@@ -0,0 +1,49 @@
+/* Capstone Disassembly Engine */
+/* TMS320C64x Backend by Fotis Loukos <me@fotisl.com> 2016 */
+
+#ifdef CAPSTONE_HAS_TMS320C64X
+
+#include "../../utils.h"
+#include "../../MCRegisterInfo.h"
+#include "TMS320C64xDisassembler.h"
+#include "TMS320C64xInstPrinter.h"
+#include "TMS320C64xMapping.h"
+#include "TMS320C64xModule.h"
+
+cs_err TMS320C64x_global_init(cs_struct *ud)
+{
+	MCRegisterInfo *mri;
+
+	mri = cs_mem_malloc(sizeof(*mri));
+
+	TMS320C64x_init(mri);
+	ud->printer = TMS320C64x_printInst;
+	ud->printer_info = mri;
+	ud->getinsn_info = mri;
+	ud->disasm = TMS320C64x_getInstruction;
+	ud->post_printer = TMS320C64x_post_printer;
+
+	ud->reg_name = TMS320C64x_reg_name;
+	ud->insn_id = TMS320C64x_get_insn_id;
+	ud->insn_name = TMS320C64x_insn_name;
+	ud->group_name = TMS320C64x_group_name;
+
+	return CS_ERR_OK;
+}
+
+cs_err TMS320C64x_option(cs_struct *handle, cs_opt_type type, size_t value)
+{
+	switch (type) {
+	case CS_OPT_MODE:
+		handle->mode |= (cs_mode)value;
+		break;
+	case CS_OPT_SYNTAX:
+		handle->syntax |= (int)value;
+		break;
+	default:
+		break;
+	}
+	return CS_ERR_OK;
+}
+
+#endif
@@ -0,0 +1,12 @@
+/* Capstone Disassembly Engine */
+/* By Travis Finkenauer <tmfinken@gmail.com>, 2018 */
+
+#ifndef CS_TMS320C64X_MODULE_H
+#define CS_TMS320C64X_MODULE_H
+
+#include "../../utils.h"
+
+cs_err TMS320C64x_global_init(cs_struct *ud);
+cs_err TMS320C64x_option(cs_struct *handle, cs_opt_type type, size_t value);
+
+#endif