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Squashed 'external/ircolib/' changes from ce3cd726c..de6e324bd

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de6e324bd separate emu thread
10d3daf86 Roms List improvements
95d202f37 Let's make the rom list process on a separate thread so the emulator doesnt take ages to load.
fc306967f Wow the ROM Header was just completely busted. Game list view works now
bad1691ee fuck this shit
2b59e5f46 game list in progress
d26417b83 remappable inputs in progress
ac4af8106 input
e72abc240 update readme
430139dc9 Qt6 frontend
3080d4d45 Fix this small bug too
08cd13b85 Cop0 unused functions do not actually pose a threat (as per manual). They don't do anything, so shall we.
61bb4fb44 make idle loop detection a little more specific with where the load goes
b037de4c3 SAZDFsdff
12e81e73e need to figure out why n64-systemtest loops indefinitely at some address that appears to be valid (i think it's me not invalidating the cache properly)
204f0e13b idle skipping seems to work!
cb8bb634a sdkfjlasdf
58e5c89c1 Fix compilation issue on my machine (no idea)
24fb2898e attempting more serious idle skipping
214719577 Place rsp.Step inside cached interpreter. Gains about 3 more fps
bb97dcc23 mmmmm
920b77d38 wjkhasdfjhkasdf
430ccdab4 it's a start...
4f42a673a Cached interpreter plays Mario 64. Start looking into RSP as well
c9a030787 idle skipping works!
5fbda03ce new idea
366637aba Idle skipping... maybe?
609fa2fb0 Cache instructions implemented but broken lmao. Commented out for now
e140a6d12 - Stop using inheritance for CPU, instead use composition. - Introduce KAIZEN_JIT_ENABLED optional define instead of relying on __aarch64__ and the like. - More cache work
68e613057 prep cache impl
811b4d809 fix clang format
fda755f7d idk
d5024ebbf small MI refactor in preparation of (eventually) implementing the RDRAM interface properly
694b45341 Merge commit '206dcdedf195fb320913584180edb12c7731e396' as 'external/SDL'
206dcdedf Squashed 'external/SDL/' content from commit 4d17b99d0a
4d16e1cb4 need to update sdl
848b19920 Fix compilation error
db61b5299 Merge commit 'e94a94559f28e49678fbcf72199a5258137b0fe9' as 'external/imgui'
e94a94559 Squashed 'external/imgui/' content from commit 02e9b8cac
52edb3757 need to update imgui
c1a705e86 Emulate weird JALR behaviour
4b4c32f4b Fix exception for "unusable COP1" in 4 instructions i missed accidentally (again)
df5828142 Bug putting 0s in the log everywhere
f8b580048 Make isviewer a sink to file
8241e9735 Fix exception for "unusable COP1" in 4 instructions i missed accidentally
b29715f20 small changes
d9a620bc1 make use of my new small utility library
0d1aa938e Add 'external/ircolib/' from commit 'ce3cd726c8df8388d554abf8bb55d55020eb4450'
e64eb40b3 Fuck git

git-subtree-dir: external/ircolib
git-subtree-split: de6e324bde
This commit is contained in:
iris
2026-06-15 11:56:38 +02:00
parent ce3cd726c8
commit 00cc9309cb
4479 changed files with 2943227 additions and 7 deletions
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external/capstone/include/capstone/aarch64.h
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external/capstone/include/capstone/alpha.h
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#ifndef CAPSTONE_ALPHA_H
#define CAPSTONE_ALPHA_H
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2014 */
#ifdef __cplusplus
extern "C" {
#endif
#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
#include <stdint.h>
#endif
#include "cs_operand.h"
#include "platform.h"
#ifdef _MSC_VER
#pragma warning(disable : 4201)
#endif
#define NUM_ALPHA_OPS 3
//> Operand type for instruction's operands
typedef enum alpha_op_type {
ALPHA_OP_INVALID = CS_OP_INVALID, ///< CS_OP_INVALID (Uninitialized).
ALPHA_OP_REG = CS_OP_REG, ///< CS_OP_REG (Register operand).
ALPHA_OP_IMM = CS_OP_IMM, ///< CS_OP_IMM (Immediate operand).
} alpha_op_type;
// Instruction operand
typedef struct cs_alpha_op {
alpha_op_type type; // operand type
union {
unsigned int reg; // register value for REG operand
int32_t imm; // immediate value for IMM operand
};
enum cs_ac_type access;
} cs_alpha_op;
// Instruction structure
typedef struct cs_alpha {
// Number of operands of this instruction,
// or 0 when instruction has no operand.
uint8_t op_count;
cs_alpha_op operands[NUM_ALPHA_OPS]; // operands for this instruction.
} cs_alpha;
//> Alpha registers
typedef enum alpha_reg {
// generated content <AlphaGenCSRegEnum.inc> begin
// clang-format off
Alpha_REG_INVALID = 0,
Alpha_REG_F0 = 1,
Alpha_REG_F1 = 2,
Alpha_REG_F2 = 3,
Alpha_REG_F3 = 4,
Alpha_REG_F4 = 5,
Alpha_REG_F5 = 6,
Alpha_REG_F6 = 7,
Alpha_REG_F7 = 8,
Alpha_REG_F8 = 9,
Alpha_REG_F9 = 10,
Alpha_REG_F10 = 11,
Alpha_REG_F11 = 12,
Alpha_REG_F12 = 13,
Alpha_REG_F13 = 14,
Alpha_REG_F14 = 15,
Alpha_REG_F15 = 16,
Alpha_REG_F16 = 17,
Alpha_REG_F17 = 18,
Alpha_REG_F18 = 19,
Alpha_REG_F19 = 20,
Alpha_REG_F20 = 21,
Alpha_REG_F21 = 22,
Alpha_REG_F22 = 23,
Alpha_REG_F23 = 24,
Alpha_REG_F24 = 25,
Alpha_REG_F25 = 26,
Alpha_REG_F26 = 27,
Alpha_REG_F27 = 28,
Alpha_REG_F28 = 29,
Alpha_REG_F29 = 30,
Alpha_REG_F30 = 31,
Alpha_REG_F31 = 32,
Alpha_REG_R0 = 33,
Alpha_REG_R1 = 34,
Alpha_REG_R2 = 35,
Alpha_REG_R3 = 36,
Alpha_REG_R4 = 37,
Alpha_REG_R5 = 38,
Alpha_REG_R6 = 39,
Alpha_REG_R7 = 40,
Alpha_REG_R8 = 41,
Alpha_REG_R9 = 42,
Alpha_REG_R10 = 43,
Alpha_REG_R11 = 44,
Alpha_REG_R12 = 45,
Alpha_REG_R13 = 46,
Alpha_REG_R14 = 47,
Alpha_REG_R15 = 48,
Alpha_REG_R16 = 49,
Alpha_REG_R17 = 50,
Alpha_REG_R18 = 51,
Alpha_REG_R19 = 52,
Alpha_REG_R20 = 53,
Alpha_REG_R21 = 54,
Alpha_REG_R22 = 55,
Alpha_REG_R23 = 56,
Alpha_REG_R24 = 57,
Alpha_REG_R25 = 58,
Alpha_REG_R26 = 59,
Alpha_REG_R27 = 60,
Alpha_REG_R28 = 61,
Alpha_REG_R29 = 62,
Alpha_REG_R30 = 63,
Alpha_REG_R31 = 64,
Alpha_REG_ENDING, // 65
// clang-format on
// generated content <AlphaGenCSRegEnum.inc> end
} alpha_reg;
//> Alpha instruction
typedef enum alpha_insn {
// generated content <AlphaGenCSInsnEnum.inc:GET_INSTR_ENUM> begin
// clang-format off
Alpha_INS_INVALID,
Alpha_INS_ADDL,
Alpha_INS_ADDQ,
Alpha_INS_ADDSsSU,
Alpha_INS_ADDTsSU,
Alpha_INS_AND,
Alpha_INS_BEQ,
Alpha_INS_BGE,
Alpha_INS_BGT,
Alpha_INS_BIC,
Alpha_INS_BIS,
Alpha_INS_BLBC,
Alpha_INS_BLBS,
Alpha_INS_BLE,
Alpha_INS_BLT,
Alpha_INS_BNE,
Alpha_INS_BR,
Alpha_INS_BSR,
Alpha_INS_CMOVEQ,
Alpha_INS_CMOVGE,
Alpha_INS_CMOVGT,
Alpha_INS_CMOVLBC,
Alpha_INS_CMOVLBS,
Alpha_INS_CMOVLE,
Alpha_INS_CMOVLT,
Alpha_INS_CMOVNE,
Alpha_INS_CMPBGE,
Alpha_INS_CMPEQ,
Alpha_INS_CMPLE,
Alpha_INS_CMPLT,
Alpha_INS_CMPTEQsSU,
Alpha_INS_CMPTLEsSU,
Alpha_INS_CMPTLTsSU,
Alpha_INS_CMPTUNsSU,
Alpha_INS_CMPULE,
Alpha_INS_CMPULT,
Alpha_INS_COND_BRANCH,
Alpha_INS_CPYSE,
Alpha_INS_CPYSN,
Alpha_INS_CPYS,
Alpha_INS_CTLZ,
Alpha_INS_CTPOP,
Alpha_INS_CTTZ,
Alpha_INS_CVTQSsSUI,
Alpha_INS_CVTQTsSUI,
Alpha_INS_CVTSTsS,
Alpha_INS_CVTTQsSVC,
Alpha_INS_CVTTSsSUI,
Alpha_INS_DIVSsSU,
Alpha_INS_DIVTsSU,
Alpha_INS_ECB,
Alpha_INS_EQV,
Alpha_INS_EXCB,
Alpha_INS_EXTBL,
Alpha_INS_EXTLH,
Alpha_INS_EXTLL,
Alpha_INS_EXTQH,
Alpha_INS_EXTQL,
Alpha_INS_EXTWH,
Alpha_INS_EXTWL,
Alpha_INS_FBEQ,
Alpha_INS_FBGE,
Alpha_INS_FBGT,
Alpha_INS_FBLE,
Alpha_INS_FBLT,
Alpha_INS_FBNE,
Alpha_INS_FCMOVEQ,
Alpha_INS_FCMOVGE,
Alpha_INS_FCMOVGT,
Alpha_INS_FCMOVLE,
Alpha_INS_FCMOVLT,
Alpha_INS_FCMOVNE,
Alpha_INS_FETCH,
Alpha_INS_FETCH_M,
Alpha_INS_FTOIS,
Alpha_INS_FTOIT,
Alpha_INS_INSBL,
Alpha_INS_INSLH,
Alpha_INS_INSLL,
Alpha_INS_INSQH,
Alpha_INS_INSQL,
Alpha_INS_INSWH,
Alpha_INS_INSWL,
Alpha_INS_ITOFS,
Alpha_INS_ITOFT,
Alpha_INS_JMP,
Alpha_INS_JSR,
Alpha_INS_JSR_COROUTINE,
Alpha_INS_LDA,
Alpha_INS_LDAH,
Alpha_INS_LDBU,
Alpha_INS_LDL,
Alpha_INS_LDL_L,
Alpha_INS_LDQ,
Alpha_INS_LDQ_L,
Alpha_INS_LDQ_U,
Alpha_INS_LDS,
Alpha_INS_LDT,
Alpha_INS_LDWU,
Alpha_INS_MB,
Alpha_INS_MSKBL,
Alpha_INS_MSKLH,
Alpha_INS_MSKLL,
Alpha_INS_MSKQH,
Alpha_INS_MSKQL,
Alpha_INS_MSKWH,
Alpha_INS_MSKWL,
Alpha_INS_MULL,
Alpha_INS_MULQ,
Alpha_INS_MULSsSU,
Alpha_INS_MULTsSU,
Alpha_INS_ORNOT,
Alpha_INS_RC,
Alpha_INS_RET,
Alpha_INS_RPCC,
Alpha_INS_RS,
Alpha_INS_S4ADDL,
Alpha_INS_S4ADDQ,
Alpha_INS_S4SUBL,
Alpha_INS_S4SUBQ,
Alpha_INS_S8ADDL,
Alpha_INS_S8ADDQ,
Alpha_INS_S8SUBL,
Alpha_INS_S8SUBQ,
Alpha_INS_SEXTB,
Alpha_INS_SEXTW,
Alpha_INS_SLL,
Alpha_INS_SQRTSsSU,
Alpha_INS_SQRTTsSU,
Alpha_INS_SRA,
Alpha_INS_SRL,
Alpha_INS_STB,
Alpha_INS_STL,
Alpha_INS_STL_C,
Alpha_INS_STQ,
Alpha_INS_STQ_C,
Alpha_INS_STQ_U,
Alpha_INS_STS,
Alpha_INS_STT,
Alpha_INS_STW,
Alpha_INS_SUBL,
Alpha_INS_SUBQ,
Alpha_INS_SUBSsSU,
Alpha_INS_SUBTsSU,
Alpha_INS_TRAPB,
Alpha_INS_UMULH,
Alpha_INS_WH64,
Alpha_INS_WH64EN,
Alpha_INS_WMB,
Alpha_INS_XOR,
Alpha_INS_ZAPNOT,
// clang-format on
// generated content <AlphaGenCSInsnEnum.inc:GET_INSTR_ENUM> end
ALPHA_INS_ENDING, // <-- mark the end of the list of instructions
} alpha_insn;
//> Group of Alpha instructions
typedef enum alpha_insn_group {
Alpha_GRP_INVALID, ///< = CS_GRP_INVALID
//> Generic groups
Alpha_GRP_CALL, ///< = CS_GRP_CALL
Alpha_GRP_JUMP, ///< = CS_GRP_JUMP
Alpha_GRP_BRANCH_RELATIVE, ///< = CS_GRP_BRANCH_RELATIVE
Alpha_GRP_ENDING, ///< = mark the end of the list of groups
} alpha_insn_group;
#ifdef __cplusplus
}
#endif
#endif
external/capstone/include/capstone/arc.h
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#ifndef CAPSTONE_ARC_H
#define CAPSTONE_ARC_H
#ifdef __cplusplus
extern "C" {
#endif
#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
#include <stdint.h>
#endif
#include "platform.h"
#include "cs_operand.h"
/// Operand type for instruction's operands
typedef enum arc_op_type {
ARC_OP_INVALID = CS_OP_INVALID, ///< Invalid
ARC_OP_REG = CS_OP_REG, ///< Register operand
ARC_OP_IMM = CS_OP_IMM, ///< Immediate operand
} arc_op_type;
/// Instruction operand
typedef struct cs_arc_op {
arc_op_type type; //< operand type
union {
unsigned int reg; /// register value for REG operand
int64_t imm; /// immediate value for IMM operand
};
/// How is this operand accessed? (READ, WRITE or READ|WRITE)
/// NOTE: this field is irrelevant if engine is compiled in DIET mode.
enum cs_ac_type access;
} cs_arc_op;
#define NUM_ARC_OPS 8
/// Instruction structure
typedef struct cs_arc {
/// Number of operands of this instruction,
/// or 0 when instruction has no operand.
uint8_t op_count;
cs_arc_op operands[NUM_ARC_OPS]; ///< operands for this instruction.
} cs_arc;
/// ARC registers
typedef enum arc_reg {
// generated content <ARCGenCSRegEnum.inc> begin
// clang-format off
ARC_REG_INVALID = 0,
ARC_REG_BLINK = 1,
ARC_REG_FP = 2,
ARC_REG_GP = 3,
ARC_REG_ILINK = 4,
ARC_REG_SP = 5,
ARC_REG_R0 = 6,
ARC_REG_R1 = 7,
ARC_REG_R2 = 8,
ARC_REG_R3 = 9,
ARC_REG_R4 = 10,
ARC_REG_R5 = 11,
ARC_REG_R6 = 12,
ARC_REG_R7 = 13,
ARC_REG_R8 = 14,
ARC_REG_R9 = 15,
ARC_REG_R10 = 16,
ARC_REG_R11 = 17,
ARC_REG_R12 = 18,
ARC_REG_R13 = 19,
ARC_REG_R14 = 20,
ARC_REG_R15 = 21,
ARC_REG_R16 = 22,
ARC_REG_R17 = 23,
ARC_REG_R18 = 24,
ARC_REG_R19 = 25,
ARC_REG_R20 = 26,
ARC_REG_R21 = 27,
ARC_REG_R22 = 28,
ARC_REG_R23 = 29,
ARC_REG_R24 = 30,
ARC_REG_R25 = 31,
ARC_REG_R30 = 32,
ARC_REG_R32 = 33,
ARC_REG_R33 = 34,
ARC_REG_R34 = 35,
ARC_REG_R35 = 36,
ARC_REG_R36 = 37,
ARC_REG_R37 = 38,
ARC_REG_R38 = 39,
ARC_REG_R39 = 40,
ARC_REG_R40 = 41,
ARC_REG_R41 = 42,
ARC_REG_R42 = 43,
ARC_REG_R43 = 44,
ARC_REG_R44 = 45,
ARC_REG_R45 = 46,
ARC_REG_R46 = 47,
ARC_REG_R47 = 48,
ARC_REG_R48 = 49,
ARC_REG_R49 = 50,
ARC_REG_R50 = 51,
ARC_REG_R51 = 52,
ARC_REG_R52 = 53,
ARC_REG_R53 = 54,
ARC_REG_R54 = 55,
ARC_REG_R55 = 56,
ARC_REG_R56 = 57,
ARC_REG_R57 = 58,
ARC_REG_R58 = 59,
ARC_REG_R59 = 60,
ARC_REG_R60 = 61,
ARC_REG_R61 = 62,
ARC_REG_R62 = 63,
ARC_REG_R63 = 64,
ARC_REG_STATUS32 = 65,
ARC_REG_ENDING, // 66
// clang-format on
// generated content <ARCGenCSRegEnum.inc> end
} arc_reg;
/// ARC instruction
typedef enum arc_insn {
// generated content <ARCGenCSInsnEnum.inc> begin
// clang-format off
ARC_INS_INVALID,
ARC_INS_h,
ARC_INS_PBR,
ARC_INS_ERROR_FLS,
ARC_INS_ERROR_FFS,
ARC_INS_PLDFI,
ARC_INS_STB_FAR,
ARC_INS_STH_FAR,
ARC_INS_ST_FAR,
ARC_INS_ADC,
ARC_INS_ADC_F,
ARC_INS_ADD_S,
ARC_INS_ADD,
ARC_INS_ADD_F,
ARC_INS_AND,
ARC_INS_AND_F,
ARC_INS_ASL_S,
ARC_INS_ASL,
ARC_INS_ASL_F,
ARC_INS_ASR_S,
ARC_INS_ASR,
ARC_INS_ASR_F,
ARC_INS_BCLR_S,
ARC_INS_BEQ_S,
ARC_INS_BGE_S,
ARC_INS_BGT_S,
ARC_INS_BHI_S,
ARC_INS_BHS_S,
ARC_INS_BL,
ARC_INS_BLE_S,
ARC_INS_BLO_S,
ARC_INS_BLS_S,
ARC_INS_BLT_S,
ARC_INS_BL_S,
ARC_INS_BMSK_S,
ARC_INS_BNE_S,
ARC_INS_B,
ARC_INS_BREQ_S,
ARC_INS_BRNE_S,
ARC_INS_BR,
ARC_INS_BSET_S,
ARC_INS_BTST_S,
ARC_INS_B_S,
ARC_INS_CMP_S,
ARC_INS_CMP,
ARC_INS_LD_S,
ARC_INS_MOV_S,
ARC_INS_EI_S,
ARC_INS_ENTER_S,
ARC_INS_FFS_F,
ARC_INS_FFS,
ARC_INS_FLS_F,
ARC_INS_FLS,
ARC_INS_ABS_S,
ARC_INS_ADD1_S,
ARC_INS_ADD2_S,
ARC_INS_ADD3_S,
ARC_INS_AND_S,
ARC_INS_BIC_S,
ARC_INS_BRK_S,
ARC_INS_EXTB_S,
ARC_INS_EXTH_S,
ARC_INS_JEQ_S,
ARC_INS_JL_S,
ARC_INS_JL_S_D,
ARC_INS_JNE_S,
ARC_INS_J_S,
ARC_INS_J_S_D,
ARC_INS_LSR_S,
ARC_INS_MPYUW_S,
ARC_INS_MPYW_S,
ARC_INS_MPY_S,
ARC_INS_NEG_S,
ARC_INS_NOP_S,
ARC_INS_NOT_S,
ARC_INS_OR_S,
ARC_INS_SEXB_S,
ARC_INS_SEXH_S,
ARC_INS_SUB_S,
ARC_INS_SUB_S_NE,
ARC_INS_SWI_S,
ARC_INS_TRAP_S,
ARC_INS_TST_S,
ARC_INS_UNIMP_S,
ARC_INS_XOR_S,
ARC_INS_LDB_S,
ARC_INS_LDH_S,
ARC_INS_J,
ARC_INS_JL,
ARC_INS_JLI_S,
ARC_INS_LDB_AB,
ARC_INS_LDB_AW,
ARC_INS_LDB_DI_AB,
ARC_INS_LDB_DI_AW,
ARC_INS_LDB_DI,
ARC_INS_LDB_X_AB,
ARC_INS_LDB_X_AW,
ARC_INS_LDB_X_DI_AB,
ARC_INS_LDB_X_DI_AW,
ARC_INS_LDB_X_DI,
ARC_INS_LDB_X,
ARC_INS_LDB,
ARC_INS_LDH_AB,
ARC_INS_LDH_AW,
ARC_INS_LDH_DI_AB,
ARC_INS_LDH_DI_AW,
ARC_INS_LDH_DI,
ARC_INS_LDH_S_X,
ARC_INS_LDH_X_AB,
ARC_INS_LDH_X_AW,
ARC_INS_LDH_X_DI_AB,
ARC_INS_LDH_X_DI_AW,
ARC_INS_LDH_X_DI,
ARC_INS_LDH_X,
ARC_INS_LDH,
ARC_INS_LDI_S,
ARC_INS_LD_AB,
ARC_INS_LD_AW,
ARC_INS_LD_DI_AB,
ARC_INS_LD_DI_AW,
ARC_INS_LD_DI,
ARC_INS_LD_S_AS,
ARC_INS_LD,
ARC_INS_LEAVE_S,
ARC_INS_LR,
ARC_INS_LSR,
ARC_INS_LSR_F,
ARC_INS_MAX,
ARC_INS_MAX_F,
ARC_INS_MIN,
ARC_INS_MIN_F,
ARC_INS_MOV_S_NE,
ARC_INS_MOV,
ARC_INS_MOV_F,
ARC_INS_MPYMU,
ARC_INS_MPYMU_F,
ARC_INS_MPYM,
ARC_INS_MPYM_F,
ARC_INS_MPY,
ARC_INS_MPY_F,
ARC_INS_NORMH_F,
ARC_INS_NORMH,
ARC_INS_NORM_F,
ARC_INS_NORM,
ARC_INS_OR,
ARC_INS_OR_F,
ARC_INS_POP_S,
ARC_INS_PUSH_S,
ARC_INS_ROR,
ARC_INS_ROR_F,
ARC_INS_RSUB,
ARC_INS_RSUB_F,
ARC_INS_SBC,
ARC_INS_SBC_F,
ARC_INS_SETEQ,
ARC_INS_SETEQ_F,
ARC_INS_SEXB_F,
ARC_INS_SEXB,
ARC_INS_SEXH_F,
ARC_INS_SEXH,
ARC_INS_STB_S,
ARC_INS_ST_S,
ARC_INS_STB_AB,
ARC_INS_STB_AW,
ARC_INS_STB_DI_AB,
ARC_INS_STB_DI_AW,
ARC_INS_STB_DI,
ARC_INS_STB,
ARC_INS_STH_AB,
ARC_INS_STH_AW,
ARC_INS_STH_DI_AB,
ARC_INS_STH_DI_AW,
ARC_INS_STH_DI,
ARC_INS_STH_S,
ARC_INS_STH,
ARC_INS_ST_AB,
ARC_INS_ST_AW,
ARC_INS_ST_DI_AB,
ARC_INS_ST_DI_AW,
ARC_INS_ST_DI,
ARC_INS_ST,
ARC_INS_SUB1,
ARC_INS_SUB1_F,
ARC_INS_SUB2,
ARC_INS_SUB2_F,
ARC_INS_SUB3,
ARC_INS_SUB3_F,
ARC_INS_SUB,
ARC_INS_SUB_F,
ARC_INS_XOR,
ARC_INS_XOR_F,
// clang-format on
// generated content <ARCGenCSInsnEnum.inc> end
} arc_insn;
//> Group of ARC instructions
typedef enum arc_insn_group {
ARC_GRP_INVALID = 0, ///< = CS_GRP_INVALID
/// Generic groups
/// all jump instructions (conditional+direct+indirect jumps)
ARC_GRP_JUMP, ///< = CS_GRP_JUMP
/// all call instructions
ARC_GRP_CALL, ///< = CS_GRP_CALL
/// all return instructions
ARC_GRP_RET, ///< = CS_GRP_RET
/// all relative branching instructions
ARC_GRP_BRANCH_RELATIVE, ///< = CS_GRP_BRANCH_RELATIVE
ARC_GRP_ENDING,
} arc_insn_group;
#ifdef __cplusplus
}
#endif
#endif
external/capstone/include/capstone/arm.h
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File diff suppressed because it is too large Load Diff
external/capstone/include/capstone/arm64.h
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File diff suppressed because it is too large Load Diff
external/capstone/include/capstone/bpf.h
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/* Capstone Disassembly Engine */
/* BPF Backend by david942j <david942j@gmail.com>, 2019 */
/* SPDX-FileCopyrightText: 2024 Roee Toledano <roeetoledano10@gmail.com> */
/* SPDX-License-Identifier: BSD-3 */
#ifndef CAPSTONE_BPF_H
#define CAPSTONE_BPF_H
#ifdef __cplusplus
extern "C" {
#endif
#include "platform.h"
#include "cs_operand.h"
#ifdef _MSC_VER
#pragma warning(disable : 4201)
#endif
#define NUM_BPF_OPS 3
/// Operand type for instruction's operands
typedef enum bpf_op_type {
BPF_OP_INVALID = CS_OP_INVALID,
BPF_OP_REG = CS_OP_REG,
BPF_OP_IMM = CS_OP_IMM,
BPF_OP_OFF = CS_OP_SPECIAL + 0,
BPF_OP_MSH = CS_OP_SPECIAL + 1, ///< corresponds to cBPF's BPF_MSH mode
BPF_OP_EXT = CS_OP_SPECIAL + 2, ///< cBPF's extension (not eBPF)
BPF_OP_MMEM = CS_OP_MEM | (CS_OP_SPECIAL + 3), ///< M[k] in cBPF
BPF_OP_MEM = CS_OP_MEM,
} bpf_op_type;
/// BPF registers
typedef enum bpf_reg {
BPF_REG_INVALID = 0,
///< cBPF
BPF_REG_A,
BPF_REG_X,
///< eBPF
BPF_REG_R0,
BPF_REG_R1,
BPF_REG_R2,
BPF_REG_R3,
BPF_REG_R4,
BPF_REG_R5,
BPF_REG_R6,
BPF_REG_R7,
BPF_REG_R8,
BPF_REG_R9,
BPF_REG_R10,
BPF_REG_ENDING,
} bpf_reg;
/// Instruction's operand referring to memory
/// This is associated with BPF_OP_MEM operand type above
typedef struct bpf_op_mem {
bpf_reg base; ///< base register
uint32_t disp; ///< offset value
} bpf_op_mem;
typedef enum bpf_ext_type {
BPF_EXT_INVALID = 0,
BPF_EXT_LEN,
} bpf_ext_type;
/// Instruction operand
typedef struct cs_bpf_op {
bpf_op_type type;
union {
uint8_t reg; ///< register value for REG operand
uint64_t imm; ///< immediate value IMM operand
uint32_t off; ///< offset value, used in jump & call
bpf_op_mem mem; ///< base/disp value for MEM operand
/* cBPF only */
uint32_t mmem; ///< M[k] in cBPF
uint32_t msh; ///< corresponds to cBPF's BPF_MSH mode
uint32_t ext; ///< cBPF's extension (not eBPF)
};
bool is_signed; ///< is this operand signed? It is set for memory, immediate and offset operands.
bool is_pkt; ///< is this operand referring to packet data? It is set for memory operands.
/// How is this operand accessed? (READ, WRITE or READ|WRITE)
/// This field is combined of cs_ac_type.
/// NOTE: this field is irrelevant if engine is compiled in DIET mode.
cs_ac_type access;
} cs_bpf_op;
/// Instruction structure
typedef struct cs_bpf {
uint8_t op_count;
cs_bpf_op operands[4];
} cs_bpf;
/// BPF instruction
typedef enum bpf_insn {
BPF_INS_INVALID = 0,
///< ALU
BPF_INS_ADD,
BPF_INS_SUB,
BPF_INS_MUL,
BPF_INS_DIV,
BPF_INS_SDIV,
BPF_INS_OR,
BPF_INS_AND,
BPF_INS_LSH,
BPF_INS_RSH,
BPF_INS_NEG,
BPF_INS_MOD,
BPF_INS_SMOD,
BPF_INS_XOR,
BPF_INS_MOV, ///< eBPF only
BPF_INS_MOVSB, ///< eBPF only
BPF_INS_MOVSH, ///< eBPF only
BPF_INS_ARSH, ///< eBPF only
///< ALU64, eBPF only
BPF_INS_ADD64,
BPF_INS_SUB64,
BPF_INS_MUL64,
BPF_INS_DIV64,
BPF_INS_SDIV64,
BPF_INS_OR64,
BPF_INS_AND64,
BPF_INS_LSH64,
BPF_INS_RSH64,
BPF_INS_NEG64,
BPF_INS_MOD64,
BPF_INS_SMOD64,
BPF_INS_XOR64,
BPF_INS_MOV64,
BPF_INS_MOVSB64,
BPF_INS_MOVSH64,
BPF_INS_MOVSW64,
BPF_INS_ARSH64,
///< Byteswap, eBPF only
BPF_INS_LE16,
BPF_INS_LE32,
BPF_INS_LE64,
BPF_INS_BE16,
BPF_INS_BE32,
BPF_INS_BE64,
BPF_INS_BSWAP16,
BPF_INS_BSWAP32,
BPF_INS_BSWAP64,
///< Load
BPF_INS_LDW, ///< eBPF only
BPF_INS_LDH,
BPF_INS_LDB,
BPF_INS_LDDW, ///< eBPF only: load 64-bit imm
BPF_INS_LDXW, ///< eBPF only
BPF_INS_LDXH, ///< eBPF only
BPF_INS_LDXB, ///< eBPF only
BPF_INS_LDXDW, ///< eBPF only
///< Packet data access
BPF_INS_LDABSW, ///< eBPF only
BPF_INS_LDABSH, ///< eBPF only
BPF_INS_LDABSB, ///< eBPF only
BPF_INS_LDINDW, ///< eBPF only
BPF_INS_LDINDH, ///< eBPF only
BPF_INS_LDINDB, ///< eBPF only
///< Store
BPF_INS_STW, ///< eBPF only
BPF_INS_STH, ///< eBPF only
BPF_INS_STB, ///< eBPF only
BPF_INS_STDW, ///< eBPF only
BPF_INS_STXW, ///< eBPF only
BPF_INS_STXH, ///< eBPF only
BPF_INS_STXB, ///< eBPF only
BPF_INS_STXDW, ///< eBPF only
BPF_INS_XADDW, ///< eBPF only
BPF_INS_XADDDW, ///< eBPF only
///< Jump
BPF_INS_JA,
BPF_INS_JEQ,
BPF_INS_JGT,
BPF_INS_JGE,
BPF_INS_JSET,
BPF_INS_JNE, ///< eBPF only
BPF_INS_JSGT, ///< eBPF only
BPF_INS_JSGE, ///< eBPF only
BPF_INS_CALL, ///< eBPF only
BPF_INS_CALLX, ///< eBPF only
BPF_INS_EXIT, ///< eBPF only
BPF_INS_JLT, ///< eBPF only
BPF_INS_JLE, ///< eBPF only
BPF_INS_JSLT, ///< eBPF only
BPF_INS_JSLE, ///< eBPF only
///< Jump32, eBPF only
BPF_INS_JAL,
BPF_INS_JEQ32,
BPF_INS_JGT32,
BPF_INS_JGE32,
BPF_INS_JSET32,
BPF_INS_JNE32,
BPF_INS_JSGT32,
BPF_INS_JSGE32,
BPF_INS_JLT32,
BPF_INS_JLE32,
BPF_INS_JSLT32,
BPF_INS_JSLE32,
///< Return, cBPF only
BPF_INS_RET,
///< Atomic, eBPF only
BPF_INS_AADD,
BPF_INS_AOR,
BPF_INS_AAND,
BPF_INS_AXOR,
BPF_INS_AFADD,
BPF_INS_AFOR,
BPF_INS_AFAND,
BPF_INS_AFXOR,
///< Atomic 64-bit, eBPF only
BPF_INS_AXCHG64,
BPF_INS_ACMPXCHG64,
BPF_INS_AADD64,
BPF_INS_AOR64,
BPF_INS_AAND64,
BPF_INS_AXOR64,
BPF_INS_AFADD64,
BPF_INS_AFOR64,
BPF_INS_AFAND64,
BPF_INS_AFXOR64,
///< Misc, cBPF only
BPF_INS_TAX,
BPF_INS_TXA,
BPF_INS_ENDING,
// alias instructions
BPF_INS_LD = BPF_INS_LDW, ///< cBPF only
BPF_INS_LDX = BPF_INS_LDXW, ///< cBPF only
BPF_INS_ST = BPF_INS_STW, ///< cBPF only
BPF_INS_STX = BPF_INS_STXW, ///< cBPF only
} bpf_insn;
/// Group of BPF instructions
typedef enum bpf_insn_group {
BPF_GRP_INVALID = 0, ///< = CS_GRP_INVALID
BPF_GRP_LOAD,
BPF_GRP_STORE,
BPF_GRP_ALU,
BPF_GRP_JUMP,
BPF_GRP_CALL, ///< eBPF only
BPF_GRP_RETURN,
BPF_GRP_MISC, ///< cBPF only
BPF_GRP_ENDING,
} bpf_insn_group;
#ifdef __cplusplus
}
#endif
#endif
external/capstone/include/capstone/capstone.h
Vendored
+980
View File
@@ -0,0 +1,980 @@
#ifndef CAPSTONE_ENGINE_H
#define CAPSTONE_ENGINE_H
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2016 */
#ifdef __cplusplus
extern "C" {
#endif
#include <stdarg.h>
#if defined(CAPSTONE_HAS_OSXKERNEL)
#include <libkern/libkern.h>
#else
#include <stdlib.h>
#include <stdio.h>
#endif
#include "cs_operand.h"
#include "platform.h"
#ifdef _MSC_VER
#pragma warning(disable:4201)
#pragma warning(disable:4100)
#define CAPSTONE_API __cdecl
#ifdef CAPSTONE_SHARED
#define CAPSTONE_EXPORT __declspec(dllexport)
#else // defined(CAPSTONE_STATIC)
#define CAPSTONE_EXPORT
#endif
#else
#define CAPSTONE_API
#if (defined(__GNUC__) || defined(__IBMC__)) && !defined(CAPSTONE_STATIC)
#define CAPSTONE_EXPORT __attribute__((visibility("default")))
#else // defined(CAPSTONE_STATIC)
#define CAPSTONE_EXPORT
#endif
#endif
#if (defined(__GNUC__) || defined(__IBMC__))
#define CAPSTONE_DEPRECATED __attribute__((deprecated))
#elif defined(_MSC_VER)
#define CAPSTONE_DEPRECATED __declspec(deprecated)
#else
#pragma message("WARNING: You need to implement CAPSTONE_DEPRECATED for this compiler")
#define CAPSTONE_DEPRECATED
#endif
// Capstone API version
#define CS_API_MAJOR 6
#define CS_API_MINOR 0
// Version for bleeding edge code of the Github's "next" branch.
// Use this if you want the absolutely latest development code.
// This version number will be bumped up whenever we have a new major change.
#define CS_NEXT_VERSION 7
// Capstone package version
#define CS_VERSION_MAJOR CS_API_MAJOR
#define CS_VERSION_MINOR CS_API_MINOR
#define CS_VERSION_EXTRA 0
/// Macro to create combined version which can be compared to
/// result of cs_version() API.
#define CS_MAKE_VERSION(major, minor) ((major << 8) + minor)
/// Maximum size of an instruction mnemonic string.
#define CS_MNEMONIC_SIZE 32
// Handle using with all API
typedef size_t csh;
/// Architecture type
typedef enum cs_arch {
CS_ARCH_ARM = 0, ///< ARM architecture (including Thumb, Thumb-2)
#ifdef CAPSTONE_AARCH64_COMPAT_HEADER
CS_ARCH_ARM64 = 1, ///< ARM64
#else
CS_ARCH_AARCH64 = 1, ///< AArch64
#endif
#ifdef CAPSTONE_SYSTEMZ_COMPAT_HEADER
CS_ARCH_SYSZ = 2, ///< SystemZ architecture
#else
CS_ARCH_SYSTEMZ = 2, ///< SystemZ architecture
#endif
CS_ARCH_MIPS, ///< Mips architecture
CS_ARCH_X86, ///< X86 architecture (including x86 & x86-64)
CS_ARCH_PPC, ///< PowerPC architecture
CS_ARCH_SPARC, ///< Sparc architecture
CS_ARCH_XCORE, ///< XCore architecture
CS_ARCH_M68K, ///< 68K architecture
CS_ARCH_TMS320C64X, ///< TMS320C64x architecture
CS_ARCH_M680X, ///< 680X architecture
CS_ARCH_EVM, ///< Ethereum architecture
CS_ARCH_MOS65XX, ///< MOS65XX architecture (including MOS6502)
CS_ARCH_WASM, ///< WebAssembly architecture
CS_ARCH_BPF, ///< Berkeley Packet Filter architecture (including eBPF)
CS_ARCH_RISCV, ///< RISCV architecture
CS_ARCH_SH, ///< SH architecture
CS_ARCH_TRICORE, ///< TriCore architecture
CS_ARCH_ALPHA, ///< Alpha architecture
CS_ARCH_HPPA, ///< HPPA architecture
CS_ARCH_LOONGARCH, ///< LoongArch architecture
CS_ARCH_XTENSA, ///< Xtensa architecture
CS_ARCH_ARC, ///< ARC architecture
CS_ARCH_MAX,
CS_ARCH_ALL = 0xFFFF, // All architectures - for cs_support()
} cs_arch;
// Support value to verify diet mode of the engine.
// If cs_support(CS_SUPPORT_DIET) return True, the engine was compiled
// in diet mode.
#define CS_SUPPORT_DIET (CS_ARCH_ALL + 1)
// Support value to verify X86 reduce mode of the engine.
// If cs_support(CS_SUPPORT_X86_REDUCE) return True, the engine was compiled
// in X86 reduce mode.
#define CS_SUPPORT_X86_REDUCE (CS_ARCH_ALL + 2)
/// The mode bits of the AArch64 ISA (not vendor specific).
#define CS_MODE_AARCH64_ISA_BITS 0x00fffff8
#define CS_MODE_VENDOR_AARCH64_BIT0 30
/// Mode type
typedef enum cs_mode {
CS_MODE_LITTLE_ENDIAN = 0, ///< little-endian mode (default mode)
CS_MODE_ARM = 0, ///< 32-bit ARM
CS_MODE_16 = 1 << 1, ///< 16-bit mode (X86)
CS_MODE_32 = 1 << 2, ///< 32-bit mode (X86)
CS_MODE_64 = 1 << 3, ///< 64-bit mode (X86, PPC)
// ARM
CS_MODE_THUMB = 1 << 4, ///< ARM's Thumb mode, including Thumb-2
CS_MODE_MCLASS = 1 << 5, ///< ARM's Cortex-M series
CS_MODE_V8 = 1 << 6, ///< ARMv8 A32 encodings for ARM
// AArch64
CS_MODE_APPLE_PROPRIETARY = 1 << CS_MODE_VENDOR_AARCH64_BIT0, ///< Enable Apple proprietary AArch64 instructions like AMX, MUL53, and others.
// SPARC
CS_MODE_V9 = 1 << 4, ///< SparcV9 mode (Sparc)
// PPC
CS_MODE_QPX = 1 << 4, ///< Quad Processing eXtensions mode (PPC)
CS_MODE_SPE = 1 << 5, ///< Signal Processing Engine mode (PPC)
CS_MODE_BOOKE = 1 << 6, ///< Book-E mode (PPC)
CS_MODE_PS = 1 << 7, ///< Paired-singles mode (PPC)
CS_MODE_AIX_OS = 1 << 8, ///< PowerPC AIX-OS
CS_MODE_PWR7 = 1 << 9, ///< Power 7
CS_MODE_PWR8 = 1 << 10, ///< Power 8
CS_MODE_PWR9 = 1 << 11, ///< Power 9
CS_MODE_PWR10 = 1 << 12, ///< Power 10
CS_MODE_PPC_ISA_FUTURE = 1 << 13, ///< Power ISA Future
CS_MODE_MODERN_AIX_AS = 1 << 14, ///< PowerPC AIX-OS with modern assembly
CS_MODE_MSYNC = 1 << 15, ///< PowerPC Has only the msync instruction instead of sync. Implies BOOKE
CS_MODE_M68K_000 = 1 << 1, ///< M68K 68000 mode
CS_MODE_M68K_010 = 1 << 2, ///< M68K 68010 mode
CS_MODE_M68K_020 = 1 << 3, ///< M68K 68020 mode
CS_MODE_M68K_030 = 1 << 4, ///< M68K 68030 mode
CS_MODE_M68K_040 = 1 << 5, ///< M68K 68040 mode
CS_MODE_M68K_060 = 1 << 6, ///< M68K 68060 mode
CS_MODE_BIG_ENDIAN = 1U << 31, ///< big-endian mode
CS_MODE_MIPS16 = CS_MODE_16, ///< Generic mips16
CS_MODE_MIPS32 = CS_MODE_32, ///< Generic mips32
CS_MODE_MIPS64 = CS_MODE_64, ///< Generic mips64
CS_MODE_MICRO = 1 << 4, ///< microMips
CS_MODE_MIPS1 = 1 << 5, ///< Mips I ISA Support
CS_MODE_MIPS2 = 1 << 6, ///< Mips II ISA Support
CS_MODE_MIPS32R2 = 1 << 7, ///< Mips32r2 ISA Support
CS_MODE_MIPS32R3 = 1 << 8, ///< Mips32r3 ISA Support
CS_MODE_MIPS32R5 = 1 << 9, ///< Mips32r5 ISA Support
CS_MODE_MIPS32R6 = 1 << 10, ///< Mips32r6 ISA Support
CS_MODE_MIPS3 = 1 << 11, ///< MIPS III ISA Support
CS_MODE_MIPS4 = 1 << 12, ///< MIPS IV ISA Support
CS_MODE_MIPS5 = 1 << 13, ///< MIPS V ISA Support
CS_MODE_MIPS64R2 = 1 << 14, ///< Mips64r2 ISA Support
CS_MODE_MIPS64R3 = 1 << 15, ///< Mips64r3 ISA Support
CS_MODE_MIPS64R5 = 1 << 16, ///< Mips64r5 ISA Support
CS_MODE_MIPS64R6 = 1 << 17, ///< Mips64r6 ISA Support
CS_MODE_OCTEON = 1 << 18, ///< Octeon cnMIPS Support
CS_MODE_OCTEONP = 1 << 19, ///< Octeon+ cnMIPS Support
CS_MODE_NANOMIPS = 1 << 20, ///< Generic nanomips
CS_MODE_NMS1 = ((1 << 21) | CS_MODE_NANOMIPS), ///< nanoMips NMS1
CS_MODE_I7200 = ((1 << 22) | CS_MODE_NANOMIPS), ///< nanoMips I7200
CS_MODE_MIPS_NOFLOAT = 1 << 23, ///< Disable floating points ops
CS_MODE_MIPS_PTR64 = 1 << 24, ///< Mips pointers are 64-bit
CS_MODE_MICRO32R3 = (CS_MODE_MICRO | CS_MODE_MIPS32R3), ///< microMips32r3
CS_MODE_MICRO32R6 = (CS_MODE_MICRO | CS_MODE_MIPS32R6), ///< microMips32r6
CS_MODE_M680X_6301 = 1 << 1, ///< M680X Hitachi 6301,6303 mode
CS_MODE_M680X_6309 = 1 << 2, ///< M680X Hitachi 6309 mode
CS_MODE_M680X_6800 = 1 << 3, ///< M680X Motorola 6800,6802 mode
CS_MODE_M680X_6801 = 1 << 4, ///< M680X Motorola 6801,6803 mode
CS_MODE_M680X_6805 = 1 << 5, ///< M680X Motorola/Freescale 6805 mode
CS_MODE_M680X_6808 = 1 << 6, ///< M680X Motorola/Freescale/NXP 68HC08 mode
CS_MODE_M680X_6809 = 1 << 7, ///< M680X Motorola 6809 mode
CS_MODE_M680X_6811 = 1 << 8, ///< M680X Motorola/Freescale/NXP 68HC11 mode
CS_MODE_M680X_CPU12 = 1 << 9, ///< M680X Motorola/Freescale/NXP CPU12
///< used on M68HC12/HCS12
CS_MODE_M680X_HCS08 = 1 << 10, ///< M680X Freescale/NXP HCS08 mode
CS_MODE_BPF_CLASSIC = 0, ///< Classic BPF mode (default)
CS_MODE_BPF_EXTENDED = 1 << 0, ///< Extended BPF mode
CS_MODE_RISCV32 = 1 << 0, ///< RISCV RV32G
CS_MODE_RISCV64 = 1 << 1, ///< RISCV RV64G
CS_MODE_RISCVC = 1 << 2, ///< RISCV compressed instructure mode
CS_MODE_MOS65XX_6502 = 1 << 1, ///< MOS65XXX MOS 6502
CS_MODE_MOS65XX_65C02 = 1 << 2, ///< MOS65XXX WDC 65c02
CS_MODE_MOS65XX_W65C02 = 1 << 3, ///< MOS65XXX WDC W65c02
CS_MODE_MOS65XX_65816 = 1 << 4, ///< MOS65XXX WDC 65816, 8-bit m/x
CS_MODE_MOS65XX_65816_LONG_M = (1 << 5), ///< MOS65XXX WDC 65816, 16-bit m, 8-bit x
CS_MODE_MOS65XX_65816_LONG_X = (1 << 6), ///< MOS65XXX WDC 65816, 8-bit m, 16-bit x
CS_MODE_MOS65XX_65816_LONG_MX = CS_MODE_MOS65XX_65816_LONG_M | CS_MODE_MOS65XX_65816_LONG_X,
CS_MODE_SH2 = 1 << 1, ///< SH2
CS_MODE_SH2A = 1 << 2, ///< SH2A
CS_MODE_SH3 = 1 << 3, ///< SH3
CS_MODE_SH4 = 1 << 4, ///< SH4
CS_MODE_SH4A = 1 << 5, ///< SH4A
CS_MODE_SHFPU = 1 << 6, ///< w/ FPU
CS_MODE_SHDSP = 1 << 7, ///< w/ DSP
CS_MODE_TRICORE_110 = 1 << 1, ///< Tricore 1.1
CS_MODE_TRICORE_120 = 1 << 2, ///< Tricore 1.2
CS_MODE_TRICORE_130 = 1 << 3, ///< Tricore 1.3
CS_MODE_TRICORE_131 = 1 << 4, ///< Tricore 1.3.1
CS_MODE_TRICORE_160 = 1 << 5, ///< Tricore 1.6
CS_MODE_TRICORE_161 = 1 << 6, ///< Tricore 1.6.1
CS_MODE_TRICORE_162 = 1 << 7, ///< Tricore 1.6.2
CS_MODE_TRICORE_180 = 1 << 8, ///< Tricore 1.8.0
CS_MODE_HPPA_11 = 1 << 1, ///< HPPA 1.1
CS_MODE_HPPA_20 = 1 << 2, ///< HPPA 2.0
CS_MODE_HPPA_20W = CS_MODE_HPPA_20 | (1 << 3), ///< HPPA 2.0 wide
CS_MODE_LOONGARCH32 = 1 << 0, ///< LoongArch32
CS_MODE_LOONGARCH64 = 1 << 1, ///< LoongArch64
CS_MODE_SYSTEMZ_ARCH8 = 1 << 1, ///< Enables features of the ARCH8 processor
CS_MODE_SYSTEMZ_ARCH9 = 1 << 2, ///< Enables features of the ARCH9 processor
CS_MODE_SYSTEMZ_ARCH10 = 1 << 3, ///< Enables features of the ARCH10 processor
CS_MODE_SYSTEMZ_ARCH11 = 1 << 4, ///< Enables features of the ARCH11 processor
CS_MODE_SYSTEMZ_ARCH12 = 1 << 5, ///< Enables features of the ARCH12 processor
CS_MODE_SYSTEMZ_ARCH13 = 1 << 6, ///< Enables features of the ARCH13 processor
CS_MODE_SYSTEMZ_ARCH14 = 1 << 7, ///< Enables features of the ARCH14 processor
CS_MODE_SYSTEMZ_Z10 = 1 << 8, ///< Enables features of the Z10 processor
CS_MODE_SYSTEMZ_Z196 = 1 << 9, ///< Enables features of the Z196 processor
CS_MODE_SYSTEMZ_ZEC12 = 1 << 10, ///< Enables features of the ZEC12 processor
CS_MODE_SYSTEMZ_Z13 = 1 << 11, ///< Enables features of the Z13 processor
CS_MODE_SYSTEMZ_Z14 = 1 << 12, ///< Enables features of the Z14 processor
CS_MODE_SYSTEMZ_Z15 = 1 << 13, ///< Enables features of the Z15 processor
CS_MODE_SYSTEMZ_Z16 = 1 << 14, ///< Enables features of the Z16 processor
CS_MODE_SYSTEMZ_GENERIC = 1 << 15, ///< Enables features of the generic processor
CS_MODE_XTENSA_ESP32 = 1 << 1, ///< Xtensa ESP32
CS_MODE_XTENSA_ESP32S2 = 1 << 2, ///< Xtensa ESP32S2
CS_MODE_XTENSA_ESP8266 = 1 << 3, ///< Xtensa ESP328266
} cs_mode;
typedef void* (CAPSTONE_API *cs_malloc_t)(size_t size);
typedef void* (CAPSTONE_API *cs_calloc_t)(size_t nmemb, size_t size);
typedef void* (CAPSTONE_API *cs_realloc_t)(void *ptr, size_t size);
typedef void (CAPSTONE_API *cs_free_t)(void *ptr);
typedef int (CAPSTONE_API *cs_vsnprintf_t)(char *str, size_t size, const char *format, va_list ap);
/// User-defined dynamic memory related functions: malloc/calloc/realloc/free/vsnprintf()
/// By default, Capstone uses system's malloc(), calloc(), realloc(), free() & vsnprintf().
typedef struct cs_opt_mem {
cs_malloc_t malloc;
cs_calloc_t calloc;
cs_realloc_t realloc;
cs_free_t free;
cs_vsnprintf_t vsnprintf;
} cs_opt_mem;
/// Customize mnemonic for instructions with alternative name.
/// To reset existing customized instruction to its default mnemonic,
/// call cs_option(CS_OPT_MNEMONIC) again with the same @id and NULL value
/// for @mnemonic.
typedef struct cs_opt_mnem {
/// ID of instruction to be customized.
unsigned int id;
/// Customized instruction mnemonic.
const char *mnemonic;
} cs_opt_mnem;
/// Runtime option for the disassembled engine
typedef enum cs_opt_type {
CS_OPT_INVALID = 0, ///< No option specified
CS_OPT_SYNTAX, ///< Assembly output syntax
CS_OPT_DETAIL, ///< Break down instruction structure into details
CS_OPT_MODE, ///< Change engine's mode at run-time
CS_OPT_MEM, ///< User-defined dynamic memory related functions
CS_OPT_SKIPDATA, ///< Skip data when disassembling. Then engine is in SKIPDATA mode.
CS_OPT_SKIPDATA_SETUP, ///< Setup user-defined function for SKIPDATA option
CS_OPT_MNEMONIC, ///< Customize instruction mnemonic
CS_OPT_UNSIGNED, ///< print immediate operands in unsigned form
CS_OPT_ONLY_OFFSET_BRANCH, ///< ARM, PPC, AArch64: Don't add the branch immediate value to the PC.
CS_OPT_LITBASE, ///< Xtensa, set the LITBASE value. LITBASE is set to 0 by default.
} cs_opt_type;
/// Runtime option value (associated with option type above)
typedef enum cs_opt_value {
CS_OPT_OFF = 0, ///< Turn OFF an option - default for CS_OPT_DETAIL, CS_OPT_SKIPDATA, CS_OPT_UNSIGNED.
CS_OPT_ON = 1 << 0, ///< Turn ON an option (CS_OPT_DETAIL, CS_OPT_SKIPDATA).
CS_OPT_SYNTAX_DEFAULT = 1 << 1, ///< Default asm syntax (CS_OPT_SYNTAX).
CS_OPT_SYNTAX_INTEL = 1 << 2, ///< X86 Intel asm syntax - default on X86 (CS_OPT_SYNTAX).
CS_OPT_SYNTAX_ATT = 1 << 3, ///< X86 ATT asm syntax (CS_OPT_SYNTAX).
CS_OPT_SYNTAX_NOREGNAME = 1 << 4, ///< Prints register name with only number (CS_OPT_SYNTAX)
CS_OPT_SYNTAX_MASM = 1 << 5, ///< X86 Intel Masm syntax (CS_OPT_SYNTAX).
CS_OPT_SYNTAX_MOTOROLA = 1 << 6, ///< MOS65XX use $ as hex prefix
CS_OPT_SYNTAX_CS_REG_ALIAS = 1 << 7, ///< Prints common register alias which are not defined in LLVM (ARM: r9 = sb etc.)
CS_OPT_SYNTAX_PERCENT = 1 << 8, ///< Prints the % in front of PPC registers.
CS_OPT_SYNTAX_NO_DOLLAR = 1 << 9, ///< Does not print the $ in front of Mips, LoongArch registers.
CS_OPT_DETAIL_REAL = 1 << 1, ///< If enabled, always sets the real instruction detail. Even if the instruction is an alias.
} cs_opt_value;
/// An option
typedef struct {
cs_opt_type type; ///< The option type
cs_opt_value val; ///< The option value to set.
} cs_opt;
/// Common instruction groups - to be consistent across all architectures.
typedef enum cs_group_type {
CS_GRP_INVALID = 0, ///< uninitialized/invalid group.
CS_GRP_JUMP, ///< all jump instructions (conditional+direct+indirect jumps)
CS_GRP_CALL, ///< all call instructions
CS_GRP_RET, ///< all return instructions
CS_GRP_INT, ///< all interrupt instructions (int+syscall)
CS_GRP_IRET, ///< all interrupt return instructions
CS_GRP_PRIVILEGE, ///< all privileged instructions
CS_GRP_BRANCH_RELATIVE, ///< all relative branching instructions
} cs_group_type;
/**
User-defined callback function for SKIPDATA option.
See tests/test_skipdata.c for sample code demonstrating this API.
@code: the input buffer containing code to be disassembled.
This is the same buffer passed to cs_disasm().
@code_size: size (in bytes) of the above @code buffer.
@offset: the position of the currently-examining byte in the input
buffer @code mentioned above.
@user_data: user-data passed to cs_option() via @user_data field in
cs_opt_skipdata struct below.
@return: return number of bytes to skip, or 0 to immediately stop disassembling.
*/
typedef size_t (CAPSTONE_API *cs_skipdata_cb_t)(const uint8_t *code, size_t code_size, size_t offset, void *user_data);
/// User-customized setup for SKIPDATA option
typedef struct cs_opt_skipdata {
/// Capstone considers data to skip as special "instructions".
/// User can specify the string for this instruction's "mnemonic" here.
/// By default (if @mnemonic is NULL), Capstone use ".byte".
const char *mnemonic;
/// User-defined callback function to be called when Capstone hits data.
/// If the returned value from this callback is positive (>0), Capstone
/// will skip exactly that number of bytes & continue. Otherwise, if
/// the callback returns 0, Capstone stops disassembling and returns
/// immediately from cs_disasm()
/// NOTE: if this callback pointer is NULL, Capstone would skip a number
/// of bytes depending on architectures, as following:
/// Arm: 2 bytes (Thumb mode) or 4 bytes.
/// AArch64: 4 bytes.
/// Mips: 4 bytes.
/// M680x: 1 byte.
/// PowerPC: 4 bytes.
/// Sparc: 4 bytes.
/// SystemZ: 2 bytes.
/// X86: 1 bytes.
/// XCore: 2 bytes.
/// EVM: 1 bytes.
/// RISCV: 4 bytes.
/// WASM: 1 bytes.
/// MOS65XX: 1 bytes.
/// BPF: 8 bytes.
/// TriCore: 2 bytes.
/// LoongArch: 4 bytes.
/// ARC: 2 bytes.
cs_skipdata_cb_t callback; // default value is NULL
/// User-defined data to be passed to @callback function pointer.
void *user_data;
} cs_opt_skipdata;
#include "arm.h"
#ifdef CAPSTONE_AARCH64_COMPAT_HEADER
#include "arm64.h"
#else
#include "aarch64.h"
#endif
#include "m68k.h"
#include "mips.h"
#include "ppc.h"
#include "sparc.h"
#include "systemz.h"
#include "x86.h"
#include "xcore.h"
#include "tms320c64x.h"
#include "m680x.h"
#include "evm.h"
#include "riscv.h"
#include "wasm.h"
#include "mos65xx.h"
#include "bpf.h"
#include "sh.h"
#include "tricore.h"
#include "alpha.h"
#include "hppa.h"
#include "loongarch.h"
#include "xtensa.h"
#include "arc.h"
#define MAX_IMPL_W_REGS 47
#define MAX_IMPL_R_REGS 20
#define MAX_NUM_GROUPS 16
/// NOTE: All information in cs_detail is only available when CS_OPT_DETAIL = CS_OPT_ON
/// Initialized as memset(., 0, offsetof(cs_detail, ARCH)+sizeof(cs_ARCH))
/// by ARCH_getInstruction in arch/ARCH/ARCHDisassembler.c
/// if cs_detail changes, in particular if a field is added after the union,
/// then update arch/ARCH/ARCHDisassembler.c accordingly
typedef struct cs_detail {
uint16_t regs_read
[MAX_IMPL_R_REGS]; ///< list of implicit registers read by this insn
uint8_t regs_read_count; ///< number of implicit registers read by this insn
uint16_t regs_write
[MAX_IMPL_W_REGS]; ///< list of implicit registers modified by this insn
uint8_t regs_write_count; ///< number of implicit registers modified by this insn
uint8_t groups[MAX_NUM_GROUPS]; ///< list of group this instruction belong to
uint8_t groups_count; ///< number of groups this insn belongs to
bool writeback; ///< Instruction has writeback operands.
/// Architecture-specific instruction info
union {
cs_x86 x86; ///< X86 architecture, including 16-bit, 32-bit & 64-bit mode
#ifdef CAPSTONE_AARCH64_COMPAT_HEADER
cs_arm64 arm64;
#else
cs_aarch64 aarch64; ///< AArch6464 architecture (aka ARM64)
#endif
#ifdef CAPSTONE_SYSTEMZ_COMPAT_HEADER
cs_sysz sysz; ///< SystemZ architecture
#else
cs_systemz systemz; ///< SystemZ architecture (aka SysZ)
#endif
cs_arm arm; ///< ARM architecture (including Thumb/Thumb2)
cs_m68k m68k; ///< M68K architecture
cs_mips mips; ///< MIPS architecture
cs_ppc ppc; ///< PowerPC architecture
cs_sparc sparc; ///< Sparc architecture
cs_xcore xcore; ///< XCore architecture
cs_tms320c64x tms320c64x; ///< TMS320C64x architecture
cs_m680x m680x; ///< M680X architecture
cs_evm evm; ///< Ethereum architecture
cs_mos65xx mos65xx; ///< MOS65XX architecture (including MOS6502)
cs_wasm wasm; ///< Web Assembly architecture
cs_bpf bpf; ///< Berkeley Packet Filter architecture (including eBPF)
cs_riscv riscv; ///< RISCV architecture
cs_sh sh; ///< SH architecture
cs_tricore tricore; ///< TriCore architecture
cs_alpha alpha; ///< Alpha architecture
cs_hppa hppa; ///< HPPA architecture
cs_loongarch loongarch; ///< LoongArch architecture
cs_xtensa xtensa; ///< Xtensa architecture
cs_arc arc; ///< ARC architecture
};
} cs_detail;
/// Detail information of disassembled instruction
typedef struct cs_insn {
/// Instruction ID (basically a numeric ID for the instruction mnemonic)
/// Find the instruction id in the '[ARCH]_insn' enum in the header file
/// of corresponding architecture, such as 'arm_insn' in arm.h for ARM,
/// 'x86_insn' in x86.h for X86, etc...
/// This information is available even when CS_OPT_DETAIL = CS_OPT_OFF
/// NOTE: in Skipdata mode, "data" instruction has 0 for this id field.
unsigned int id;
/// If this instruction is an alias instruction, this member is set with
/// the alias ID.
/// Otherwise to <ARCH>_INS_INVALID.
/// -- Only supported by auto-sync archs --
uint64_t alias_id;
/// Address (EIP) of this instruction
/// This information is available even when CS_OPT_DETAIL = CS_OPT_OFF
uint64_t address;
/// Size of this instruction
/// This information is available even when CS_OPT_DETAIL = CS_OPT_OFF
uint16_t size;
/// Machine bytes of this instruction, with number of bytes indicated by @size above
/// This information is available even when CS_OPT_DETAIL = CS_OPT_OFF
uint8_t bytes[24];
/// Ascii text of instruction mnemonic
/// This information is available even when CS_OPT_DETAIL = CS_OPT_OFF
char mnemonic[CS_MNEMONIC_SIZE];
/// Ascii text of instruction operands
/// This information is available even when CS_OPT_DETAIL = CS_OPT_OFF
char op_str[160];
/// True: This instruction is an alias.
/// False: Otherwise.
/// -- Only supported by auto-sync archs --
bool is_alias;
/// True: The operands are the ones of the alias instructions.
/// False: The detail operands are from the real instruction.
bool usesAliasDetails;
/// True: The bytes disassemble to a valid instruction, but it is illegal by ISA definitions.
/// For example the instruction uses a register which is not allowed or it appears in
/// an invalid context.
///
/// False: The instruction decoded correctly and is valid.
bool illegal;
/// Pointer to cs_detail.
/// NOTE: detail pointer is only valid when both requirements below are met:
/// (1) CS_OP_DETAIL = CS_OPT_ON
/// (2) Engine is not in Skipdata mode (CS_OP_SKIPDATA option set to CS_OPT_ON)
///
/// NOTE 2: when in Skipdata mode, or when detail mode is OFF, even if this pointer
/// is not NULL, its content is still irrelevant.
cs_detail *detail;
} cs_insn;
/// Calculate the offset of a disassembled instruction in its buffer, given its position
/// in its array of disassembled insn
/// NOTE: this macro works with position (>=1), not index
#define CS_INSN_OFFSET(insns, post) (insns[post - 1].address - insns[0].address)
/// All type of errors encountered by Capstone API.
/// These are values returned by cs_errno()
typedef enum cs_err {
CS_ERR_OK = 0, ///< No error: everything was fine
CS_ERR_MEM, ///< Out-Of-Memory error: cs_open(), cs_disasm(), cs_disasm_iter()
CS_ERR_ARCH, ///< Unsupported architecture: cs_open()
CS_ERR_HANDLE, ///< Invalid handle: cs_op_count(), cs_op_index()
CS_ERR_CSH, ///< Invalid csh argument: cs_close(), cs_errno(), cs_option()
CS_ERR_MODE, ///< Invalid/unsupported mode: cs_open()
CS_ERR_OPTION, ///< Invalid/unsupported option: cs_option()
CS_ERR_DETAIL, ///< Information is unavailable because detail option is OFF
CS_ERR_MEMSETUP, ///< Dynamic memory management uninitialized (see CS_OPT_MEM)
CS_ERR_VERSION, ///< Unsupported version (bindings)
CS_ERR_DIET, ///< Access irrelevant data in "diet" engine
CS_ERR_SKIPDATA, ///< Access irrelevant data for "data" instruction in SKIPDATA mode
CS_ERR_X86_ATT, ///< X86 AT&T syntax is unsupported (opt-out at compile time)
CS_ERR_X86_INTEL, ///< X86 Intel syntax is unsupported (opt-out at compile time)
CS_ERR_X86_MASM, ///< X86 Masm syntax is unsupported (opt-out at compile time)
} cs_err;
/**
Return combined API version & major and minor version numbers.
@major: major number of API version
@minor: minor number of API version
@return hexical number as (major << 8 | minor), which encodes both
major & minor versions.
NOTE: This returned value can be compared with version number made
with macro CS_MAKE_VERSION
For example, second API version would return 1 in @major, and 1 in @minor
The return value would be 0x0101
NOTE: if you only care about returned value, but not major and minor values,
set both @major & @minor arguments to NULL.
*/
CAPSTONE_EXPORT
unsigned int CAPSTONE_API cs_version(int *major, int *minor);
CAPSTONE_EXPORT
void CAPSTONE_API cs_arch_register_arm(void);
CAPSTONE_EXPORT
void CAPSTONE_API cs_arch_register_aarch64(void);
#ifdef CAPSTONE_AARCH64_COMPAT_HEADER
#define cs_arch_register_aarch64 cs_arch_register_arm64
#endif
CAPSTONE_EXPORT
void CAPSTONE_API cs_arch_register_mips(void);
CAPSTONE_EXPORT
void CAPSTONE_API cs_arch_register_x86(void);
CAPSTONE_EXPORT
void CAPSTONE_API cs_arch_register_powerpc(void);
CAPSTONE_EXPORT
void CAPSTONE_API cs_arch_register_sparc(void);
CAPSTONE_EXPORT
void CAPSTONE_API cs_arch_register_systemz(void);
#ifdef CAPSTONE_SYSTEMZ_COMPAT_HEADER
#define cs_arch_register_sysz cs_arch_register_systemz
#endif
CAPSTONE_EXPORT
void CAPSTONE_API cs_arch_register_xcore(void);
CAPSTONE_EXPORT
void CAPSTONE_API cs_arch_register_m68k(void);
CAPSTONE_EXPORT
void CAPSTONE_API cs_arch_register_tms320c64x(void);
CAPSTONE_EXPORT
void CAPSTONE_API cs_arch_register_m680x(void);
CAPSTONE_EXPORT
void CAPSTONE_API cs_arch_register_evm(void);
CAPSTONE_EXPORT
void CAPSTONE_API cs_arch_register_mos65xx(void);
CAPSTONE_EXPORT
void CAPSTONE_API cs_arch_register_wasm(void);
CAPSTONE_EXPORT
void CAPSTONE_API cs_arch_register_bpf(void);
CAPSTONE_EXPORT
void CAPSTONE_API cs_arch_register_riscv(void);
CAPSTONE_EXPORT
void CAPSTONE_API cs_arch_register_sh(void);
CAPSTONE_EXPORT
void CAPSTONE_API cs_arch_register_tricore(void);
CAPSTONE_EXPORT
void CAPSTONE_API cs_arch_register_alpha(void);
CAPSTONE_EXPORT
void CAPSTONE_API cs_arch_register_loongarch(void);
CAPSTONE_EXPORT
void CAPSTONE_API cs_arch_register_arc(void);
/**
This API can be used to either ask for archs supported by this library,
or check to see if the library was compile with 'diet' option (or called
in 'diet' mode).
To check if a particular arch is supported by this library, set @query to
arch mode (CS_ARCH_* value).
To verify if this library supports all the archs, use CS_ARCH_ALL.
To check if this library is in 'diet' mode, set @query to CS_SUPPORT_DIET.
@return True if this library supports the given arch, or in 'diet' mode.
*/
CAPSTONE_EXPORT
bool CAPSTONE_API cs_support(int query);
/**
Initialize CS handle: this must be done before any usage of CS.
@arch: architecture type (CS_ARCH_*)
@mode: hardware mode. This is combined of CS_MODE_*
@handle: pointer to handle, which will be updated at return time
@return CS_ERR_OK on success, or other value on failure (refer to cs_err enum
for detailed error).
*/
CAPSTONE_EXPORT
cs_err CAPSTONE_API cs_open(cs_arch arch, cs_mode mode, csh *handle);
/**
Close CS handle: MUST do to release the handle when it is not used anymore.
NOTE: this must be only called when there is no longer usage of Capstone,
not even access to cs_insn array. The reason is the this API releases some
cached memory, thus access to any Capstone API after cs_close() might crash
your application.
In fact,this API invalidate @handle by ZERO out its value (i.e *handle = 0).
@handle: pointer to a handle returned by cs_open()
@return CS_ERR_OK on success, or other value on failure (refer to cs_err enum
for detailed error).
*/
CAPSTONE_EXPORT
cs_err CAPSTONE_API cs_close(csh *handle);
/**
Set option for disassembling engine at runtime
@handle: handle returned by cs_open()
@type: type of option to be set
@value: option value corresponding with @type
@return: CS_ERR_OK on success, or other value on failure.
Refer to cs_err enum for detailed error.
NOTE: in the case of CS_OPT_MEM, handle's value can be anything,
so that cs_option(handle, CS_OPT_MEM, value) can (i.e must) be called
even before cs_open()
*/
CAPSTONE_EXPORT
cs_err CAPSTONE_API cs_option(csh handle, cs_opt_type type, size_t value);
/**
Report the last error number when some API function fail.
Like glibc's errno, cs_errno might not retain its old value once accessed.
@handle: handle returned by cs_open()
@return: error code of cs_err enum type (CS_ERR_*, see above)
*/
CAPSTONE_EXPORT
cs_err CAPSTONE_API cs_errno(csh handle);
/**
Return a string describing given error code.
@code: error code (see CS_ERR_* above)
@return: returns a pointer to a string that describes the error code
passed in the argument @code
*/
CAPSTONE_EXPORT
const char * CAPSTONE_API cs_strerror(cs_err code);
/**
Disassemble binary code, given the code buffer, size, address and number
of instructions to be decoded.
This API dynamically allocate memory to contain disassembled instruction.
Resulting instructions will be put into @*insn
NOTE 1: this API will automatically determine memory needed to contain
output disassembled instructions in @insn.
NOTE 2: caller must free the allocated memory itself to avoid memory leaking.
NOTE 3: for system with scarce memory to be dynamically allocated such as
OS kernel or firmware, the API cs_disasm_iter() might be a better choice than
cs_disasm(). The reason is that with cs_disasm(), based on limited available
memory, we have to calculate in advance how many instructions to be disassembled,
which complicates things. This is especially troublesome for the case @count=0,
when cs_disasm() runs uncontrollably (until either end of input buffer, or
when it encounters an invalid instruction).
@handle: handle returned by cs_open()
@code: buffer containing raw binary code to be disassembled.
@code_size: size of the above code buffer.
@address: address of the first instruction in given raw code buffer.
@insn: array of instructions filled in by this API.
NOTE: @insn will be allocated by this function, and should be freed
with cs_free() API.
@count: number of instructions to be disassembled, or 0 to get all of them
@return: the number of successfully disassembled instructions,
or 0 if this function failed to disassemble the given code
On failure, call cs_errno() for error code.
*/
CAPSTONE_EXPORT
size_t CAPSTONE_API cs_disasm(csh handle,
const uint8_t *code, size_t code_size,
uint64_t address,
size_t count,
cs_insn **insn);
/**
Free memory allocated by cs_malloc() or cs_disasm() (argument @insn)
@insn: pointer returned by @insn argument in cs_disasm() or cs_malloc()
@count: number of cs_insn structures returned by cs_disasm(), or 1
to free memory allocated by cs_malloc().
*/
CAPSTONE_EXPORT
void CAPSTONE_API cs_free(cs_insn *insn, size_t count);
/**
Allocate memory for 1 instruction to be used by cs_disasm_iter().
@handle: handle returned by cs_open()
NOTE: when no longer in use, you can reclaim the memory allocated for
this instruction with cs_free(insn, 1)
*/
CAPSTONE_EXPORT
cs_insn * CAPSTONE_API cs_malloc(csh handle);
/**
Fast API to disassemble binary code, given the code buffer, size, address
and number of instructions to be decoded.
This API puts the resulting instruction into a given cache in @insn.
See tests/test_iter.c for sample code demonstrating this API.
NOTE 1: this API will update @code, @size & @address to point to the next
instruction in the input buffer. Therefore, it is convenient to use
cs_disasm_iter() inside a loop to quickly iterate all the instructions.
While decoding one instruction at a time can also be achieved with
cs_disasm(count=1), some benchmarks shown that cs_disasm_iter() can be 30%
faster on random input.
NOTE 2: the cache in @insn can be created with cs_malloc() API.
NOTE 3: for system with scarce memory to be dynamically allocated such as
OS kernel or firmware, this API is recommended over cs_disasm(), which
allocates memory based on the number of instructions to be disassembled.
The reason is that with cs_disasm(), based on limited available memory,
we have to calculate in advance how many instructions to be disassembled,
which complicates things. This is especially troublesome for the case
@count=0, when cs_disasm() runs uncontrollably (until either end of input
buffer, or when it encounters an invalid instruction).
@handle: handle returned by cs_open()
@code: buffer containing raw binary code to be disassembled
@size: size of above code
@address: address of the first insn in given raw code buffer
@insn: pointer to instruction to be filled in by this API.
@return: true if this API successfully decode 1 instruction,
or false otherwise.
On failure, call cs_errno() for error code.
*/
CAPSTONE_EXPORT
bool CAPSTONE_API cs_disasm_iter(csh handle,
const uint8_t **code, size_t *size,
uint64_t *address, cs_insn *insn);
/**
Return friendly name of register in a string.
Find the instruction id from header file of corresponding architecture (arm.h for ARM,
x86.h for X86, ...)
WARN: when in 'diet' mode, this API is irrelevant because engine does not
store register name.
@handle: handle returned by cs_open()
@reg_id: register id
@return: string name of the register, or NULL if @reg_id is invalid.
*/
CAPSTONE_EXPORT
const char * CAPSTONE_API cs_reg_name(csh handle, unsigned int reg_id);
/**
Return friendly name of an instruction in a string.
Find the instruction id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)
WARN: when in 'diet' mode, this API is irrelevant because the engine does not
store instruction name.
@handle: handle returned by cs_open()
@insn_id: instruction id
@return: string name of the instruction, or NULL if @insn_id is invalid.
*/
CAPSTONE_EXPORT
const char * CAPSTONE_API cs_insn_name(csh handle, unsigned int insn_id);
/**
Return friendly name of a group id (that an instruction can belong to)
Find the group id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)
WARN: when in 'diet' mode, this API is irrelevant because the engine does not
store group name.
@handle: handle returned by cs_open()
@group_id: group id
@return: string name of the group, or NULL if @group_id is invalid.
*/
CAPSTONE_EXPORT
const char * CAPSTONE_API cs_group_name(csh handle, unsigned int group_id);
/**
Check if a disassembled instruction belong to a particular group.
Find the group id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)
Internally, this simply verifies if @group_id matches any member of insn->groups array.
NOTE: this API is only valid when detail option is ON (which is OFF by default).
WARN: when in 'diet' mode, this API is irrelevant because the engine does not
update @groups array.
@handle: handle returned by cs_open()
@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()
@group_id: group that you want to check if this instruction belong to.
@return: true if this instruction indeed belongs to the given group, or false otherwise.
*/
CAPSTONE_EXPORT
bool CAPSTONE_API cs_insn_group(csh handle, const cs_insn *insn, unsigned int group_id);
/**
Check if a disassembled instruction IMPLICITLY used a particular register.
Find the register id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)
Internally, this simply verifies if @reg_id matches any member of insn->regs_read array.
NOTE: this API is only valid when detail option is ON (which is OFF by default)
WARN: when in 'diet' mode, this API is irrelevant because the engine does not
update @regs_read array.
@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()
@reg_id: register that you want to check if this instruction used it.
@return: true if this instruction indeed implicitly used the given register, or false otherwise.
*/
CAPSTONE_EXPORT
bool CAPSTONE_API cs_reg_read(csh handle, const cs_insn *insn, unsigned int reg_id);
/**
Check if a disassembled instruction IMPLICITLY modified a particular register.
Find the register id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)
Internally, this simply verifies if @reg_id matches any member of insn->regs_write array.
NOTE: this API is only valid when detail option is ON (which is OFF by default)
WARN: when in 'diet' mode, this API is irrelevant because the engine does not
update @regs_write array.
@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()
@reg_id: register that you want to check if this instruction modified it.
@return: true if this instruction indeed implicitly modified the given register, or false otherwise.
*/
CAPSTONE_EXPORT
bool CAPSTONE_API cs_reg_write(csh handle, const cs_insn *insn, unsigned int reg_id);
/**
Count the number of operands of a given type.
Find the operand type in header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)
NOTE: this API is only valid when detail option is ON (which is OFF by default)
@handle: handle returned by cs_open()
@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()
@op_type: Operand type to be found.
@return: number of operands of given type @op_type in instruction @insn,
or -1 on failure.
*/
CAPSTONE_EXPORT
int CAPSTONE_API cs_op_count(csh handle, const cs_insn *insn, unsigned int op_type);
/**
Retrieve the position of operand of given type in <arch>.operands[] array.
Later, the operand can be accessed using the returned position.
Find the operand type in header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)
NOTE: this API is only valid when detail option is ON (which is OFF by default)
@handle: handle returned by cs_open()
@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()
@op_type: Operand type to be found.
@position: position of the operand to be found. This must be in the range
[1, cs_op_count(handle, insn, op_type)]
@return: index of operand of given type @op_type in <arch>.operands[] array
in instruction @insn, or -1 on failure.
*/
CAPSTONE_EXPORT
int CAPSTONE_API cs_op_index(csh handle, const cs_insn *insn, unsigned int op_type,
unsigned int position);
/// Type of array to keep the list of registers
typedef uint16_t cs_regs[64];
/**
Retrieve all the registers accessed by an instruction, either explicitly or
implicitly.
WARN: when in 'diet' mode, this API is irrelevant because engine does not
store registers.
@handle: handle returned by cs_open()
@insn: disassembled instruction structure returned from cs_disasm() or cs_disasm_iter()
@regs_read: on return, this array contains all registers read by instruction.
@regs_read_count: number of registers kept inside @regs_read array.
@regs_write: on return, this array contains all registers written by instruction.
@regs_write_count: number of registers kept inside @regs_write array.
@return CS_ERR_OK on success, or other value on failure (refer to cs_err enum
for detailed error).
*/
CAPSTONE_EXPORT
cs_err CAPSTONE_API cs_regs_access(csh handle, const cs_insn *insn,
cs_regs regs_read, uint8_t *regs_read_count,
cs_regs regs_write, uint8_t *regs_write_count);
#ifdef __cplusplus
}
#endif
#endif
external/capstone/include/capstone/cs_operand.h
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/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2014 */
/* Rot127 <unisono@quyllur.org>, 2022-2023 */
#ifndef CS_OPERAND_H
#define CS_OPERAND_H
/// Common instruction operand types - to be consistent across all architectures.
typedef enum cs_op_type {
CS_OP_INVALID = 0, ///< uninitialized/invalid operand.
CS_OP_REG = 1, ///< Register operand.
CS_OP_IMM = 2, ///< Immediate operand.
CS_OP_FP = 3, ///< Floating-Point operand.
CS_OP_PRED = 4, ///< Predicate operand.
CS_OP_RESERVED_5 = 5,
CS_OP_RESERVED_6 = 6,
CS_OP_RESERVED_7 = 7,
CS_OP_RESERVED_8 = 8,
CS_OP_RESERVED_9 = 9,
CS_OP_RESERVED_10 = 10,
CS_OP_RESERVED_11 = 11,
CS_OP_RESERVED_12 = 12,
CS_OP_RESERVED_13 = 13,
CS_OP_RESERVED_14 = 14,
CS_OP_RESERVED_15 = 15,
CS_OP_SPECIAL = 0x10, ///< Special operands from archs
CS_OP_BOUND = 0x40, ///< Operand is associated with a previous operand. Used by AArch64 for SME operands.
CS_OP_MEM = 0x80, ///< Memory operand. Can be ORed with another operand type.
CS_OP_MEM_REG = CS_OP_MEM | CS_OP_REG, ///< Memory referencing register operand.
CS_OP_MEM_IMM = CS_OP_MEM | CS_OP_IMM, ///< Memory referencing immediate operand.
} cs_op_type;
/// Common instruction operand access types - to be consistent across all architectures.
/// It is possible to combine access types, for example: CS_AC_READ | CS_AC_WRITE
typedef enum cs_ac_type {
CS_AC_INVALID = 0, ///< Uninitialized/invalid access type.
CS_AC_READ = 1 << 0, ///< Operand read from memory or register.
CS_AC_WRITE = 1 << 1, ///< Operand write to memory or register.
CS_AC_READ_WRITE =
CS_AC_READ |
CS_AC_WRITE, ///< Operand reads and writes from/to memory or register.
} cs_ac_type;
#endif // CS_OPERAND_H
external/capstone/include/capstone/evm.h
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#ifndef CAPSTONE_EVM_H
#define CAPSTONE_EVM_H
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2018 */
/* By Andelf <andelf@gmail.com>, 2025 */
#ifdef __cplusplus
extern "C" {
#endif
#include "platform.h"
#ifdef _MSC_VER
#pragma warning(disable:4201)
#endif
/// Instruction structure
typedef struct cs_evm {
unsigned char pop; ///< number of items popped from the stack
unsigned char push; ///< number of items pushed into the stack
unsigned int fee; ///< gas fee for the instruction
} cs_evm;
/// EVM instruction
typedef enum evm_insn {
EVM_INS_STOP = 0,
EVM_INS_ADD = 1,
EVM_INS_MUL = 2,
EVM_INS_SUB = 3,
EVM_INS_DIV = 4,
EVM_INS_SDIV = 5,
EVM_INS_MOD = 6,
EVM_INS_SMOD = 7,
EVM_INS_ADDMOD = 8,
EVM_INS_MULMOD = 9,
EVM_INS_EXP = 10,
EVM_INS_SIGNEXTEND = 11,
EVM_INS_LT = 16,
EVM_INS_GT = 17,
EVM_INS_SLT = 18,
EVM_INS_SGT = 19,
EVM_INS_EQ = 20,
EVM_INS_ISZERO = 21,
EVM_INS_AND = 22,
EVM_INS_OR = 23,
EVM_INS_XOR = 24,
EVM_INS_NOT = 25,
EVM_INS_BYTE = 26,
EVM_INS_SHL = 27,
EVM_INS_SHR = 28,
EVM_INS_SAR = 29,
EVM_INS_SHA3 = 32,
EVM_INS_ADDRESS = 48,
EVM_INS_BALANCE = 49,
EVM_INS_ORIGIN = 50,
EVM_INS_CALLER = 51,
EVM_INS_CALLVALUE = 52,
EVM_INS_CALLDATALOAD = 53,
EVM_INS_CALLDATASIZE = 54,
EVM_INS_CALLDATACOPY = 55,
EVM_INS_CODESIZE = 56,
EVM_INS_CODECOPY = 57,
EVM_INS_GASPRICE = 58,
EVM_INS_EXTCODESIZE = 59,
EVM_INS_EXTCODECOPY = 60,
EVM_INS_RETURNDATASIZE = 61,
EVM_INS_RETURNDATACOPY = 62,
EVM_INS_BLOCKHASH = 64,
EVM_INS_COINBASE = 65,
EVM_INS_TIMESTAMP = 66,
EVM_INS_NUMBER = 67,
EVM_INS_DIFFICULTY = 68,
EVM_INS_GASLIMIT = 69,
EVM_INS_CHAINID = 70,
EVM_INS_SELFBALANCE = 71,
EVM_INS_BASEFEE = 72,
EVM_INS_BLOBHASH = 73,
EVM_INS_BLOBBASEFEE = 74,
EVM_INS_POP = 80,
EVM_INS_MLOAD = 81,
EVM_INS_MSTORE = 82,
EVM_INS_MSTORE8 = 83,
EVM_INS_SLOAD = 84,
EVM_INS_SSTORE = 85,
EVM_INS_JUMP = 86,
EVM_INS_JUMPI = 87,
EVM_INS_PC = 88,
EVM_INS_MSIZE = 89,
EVM_INS_GAS = 90,
EVM_INS_JUMPDEST = 91,
EVM_INS_TLOAD = 92,
EVM_INS_TSTORE = 93,
EVM_INS_MCOPY = 94,
EVM_INS_PUSH0 = 95,
EVM_INS_PUSH1 = 96,
EVM_INS_PUSH2 = 97,
EVM_INS_PUSH3 = 98,
EVM_INS_PUSH4 = 99,
EVM_INS_PUSH5 = 100,
EVM_INS_PUSH6 = 101,
EVM_INS_PUSH7 = 102,
EVM_INS_PUSH8 = 103,
EVM_INS_PUSH9 = 104,
EVM_INS_PUSH10 = 105,
EVM_INS_PUSH11 = 106,
EVM_INS_PUSH12 = 107,
EVM_INS_PUSH13 = 108,
EVM_INS_PUSH14 = 109,
EVM_INS_PUSH15 = 110,
EVM_INS_PUSH16 = 111,
EVM_INS_PUSH17 = 112,
EVM_INS_PUSH18 = 113,
EVM_INS_PUSH19 = 114,
EVM_INS_PUSH20 = 115,
EVM_INS_PUSH21 = 116,
EVM_INS_PUSH22 = 117,
EVM_INS_PUSH23 = 118,
EVM_INS_PUSH24 = 119,
EVM_INS_PUSH25 = 120,
EVM_INS_PUSH26 = 121,
EVM_INS_PUSH27 = 122,
EVM_INS_PUSH28 = 123,
EVM_INS_PUSH29 = 124,
EVM_INS_PUSH30 = 125,
EVM_INS_PUSH31 = 126,
EVM_INS_PUSH32 = 127,
EVM_INS_DUP1 = 128,
EVM_INS_DUP2 = 129,
EVM_INS_DUP3 = 130,
EVM_INS_DUP4 = 131,
EVM_INS_DUP5 = 132,
EVM_INS_DUP6 = 133,
EVM_INS_DUP7 = 134,
EVM_INS_DUP8 = 135,
EVM_INS_DUP9 = 136,
EVM_INS_DUP10 = 137,
EVM_INS_DUP11 = 138,
EVM_INS_DUP12 = 139,
EVM_INS_DUP13 = 140,
EVM_INS_DUP14 = 141,
EVM_INS_DUP15 = 142,
EVM_INS_DUP16 = 143,
EVM_INS_SWAP1 = 144,
EVM_INS_SWAP2 = 145,
EVM_INS_SWAP3 = 146,
EVM_INS_SWAP4 = 147,
EVM_INS_SWAP5 = 148,
EVM_INS_SWAP6 = 149,
EVM_INS_SWAP7 = 150,
EVM_INS_SWAP8 = 151,
EVM_INS_SWAP9 = 152,
EVM_INS_SWAP10 = 153,
EVM_INS_SWAP11 = 154,
EVM_INS_SWAP12 = 155,
EVM_INS_SWAP13 = 156,
EVM_INS_SWAP14 = 157,
EVM_INS_SWAP15 = 158,
EVM_INS_SWAP16 = 159,
EVM_INS_LOG0 = 160,
EVM_INS_LOG1 = 161,
EVM_INS_LOG2 = 162,
EVM_INS_LOG3 = 163,
EVM_INS_LOG4 = 164,
EVM_INS_CREATE = 240,
EVM_INS_CALL = 241,
EVM_INS_CALLCODE = 242,
EVM_INS_RETURN = 243,
EVM_INS_DELEGATECALL = 244,
EVM_INS_CREATE2 = 245,
EVM_INS_STATICCALL = 250,
EVM_INS_REVERT = 253,
EVM_INS_INVALID = 254,
EVM_INS_SELFDESTRUCT = 255, // originally called SUICIDE
EVM_INS_ENDING, // <-- mark the end of the list of instructions
} evm_insn;
/// Group of EVM instructions
typedef enum evm_insn_group {
EVM_GRP_INVALID = 0, ///< = CS_GRP_INVALID
EVM_GRP_JUMP, ///< all jump instructions
EVM_GRP_MATH = 8, ///< math instructions
EVM_GRP_STACK_WRITE, ///< instructions write to stack
EVM_GRP_STACK_READ, ///< instructions read from stack
EVM_GRP_MEM_WRITE, ///< instructions write to memory
EVM_GRP_MEM_READ, ///< instructions read from memory
EVM_GRP_STORE_WRITE, ///< instructions write to storage
EVM_GRP_STORE_READ, ///< instructions read from storage
EVM_GRP_HALT, ///< instructions halt execution
EVM_GRP_ENDING, ///< <-- mark the end of the list of groups
} evm_insn_group;
#ifdef __cplusplus
}
#endif
#endif
external/capstone/include/capstone/hppa.h
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#ifndef CAPSTONE_HPPA_H
#define CAPSTONE_HPPA_H
#ifdef __cplusplus
extern "C" {
#endif
#include "cs_operand.h"
#include "platform.h"
#define NUM_HPPA_OPS 5
#define HPPA_STR_MODIFIER_LEN 8
#define HPPA_MAX_MODIFIERS_LEN 5
/// Operand type for instruction's operands
typedef enum hppa_op_type {
HPPA_OP_INVALID = CS_OP_INVALID,
HPPA_OP_REG = CS_OP_REG,
HPPA_OP_IMM = CS_OP_IMM,
HPPA_OP_IDX_REG = CS_OP_SPECIAL + 0,
HPPA_OP_DISP = CS_OP_SPECIAL + 1,
HPPA_OP_TARGET = CS_OP_SPECIAL + 2,
HPPA_OP_MEM = CS_OP_MEM,
} hppa_op_type;
//> HPPA registers
typedef enum hppa_reg {
HPPA_REG_INVALID = 0,
///> General registers
HPPA_REG_GR0,
HPPA_REG_GR1,
HPPA_REG_GR2,
HPPA_REG_GR3,
HPPA_REG_GR4,
HPPA_REG_GR5,
HPPA_REG_GR6,
HPPA_REG_GR7,
HPPA_REG_GR8,
HPPA_REG_GR9,
HPPA_REG_GR10,
HPPA_REG_GR11,
HPPA_REG_GR12,
HPPA_REG_GR13,
HPPA_REG_GR14,
HPPA_REG_GR15,
HPPA_REG_GR16,
HPPA_REG_GR17,
HPPA_REG_GR18,
HPPA_REG_GR19,
HPPA_REG_GR20,
HPPA_REG_GR21,
HPPA_REG_GR22,
HPPA_REG_GR23,
HPPA_REG_GR24,
HPPA_REG_GR25,
HPPA_REG_GR26,
HPPA_REG_GR27,
HPPA_REG_GR28,
HPPA_REG_GR29,
HPPA_REG_GR30,
HPPA_REG_GR31,
///> Floating-point registers
HPPA_REG_FPR0,
HPPA_REG_FPR1,
HPPA_REG_FPR2,
HPPA_REG_FPR3,
HPPA_REG_FPR4,
HPPA_REG_FPR5,
HPPA_REG_FPR6,
HPPA_REG_FPR7,
HPPA_REG_FPR8,
HPPA_REG_FPR9,
HPPA_REG_FPR10,
HPPA_REG_FPR11,
HPPA_REG_FPR12,
HPPA_REG_FPR13,
HPPA_REG_FPR14,
HPPA_REG_FPR15,
HPPA_REG_FPR16,
HPPA_REG_FPR17,
HPPA_REG_FPR18,
HPPA_REG_FPR19,
HPPA_REG_FPR20,
HPPA_REG_FPR21,
HPPA_REG_FPR22,
HPPA_REG_FPR23,
HPPA_REG_FPR24,
HPPA_REG_FPR25,
HPPA_REG_FPR26,
HPPA_REG_FPR27,
HPPA_REG_FPR28,
HPPA_REG_FPR29,
HPPA_REG_FPR30,
HPPA_REG_FPR31,
///> Space registers
HPPA_REG_SR0,
HPPA_REG_SR1,
HPPA_REG_SR2,
HPPA_REG_SR3,
HPPA_REG_SR4,
HPPA_REG_SR5,
HPPA_REG_SR6,
HPPA_REG_SR7,
///> Control registers
HPPA_REG_CR0,
HPPA_REG_CR1,
HPPA_REG_CR2,
HPPA_REG_CR3,
HPPA_REG_CR4,
HPPA_REG_CR5,
HPPA_REG_CR6,
HPPA_REG_CR7,
HPPA_REG_CR8,
HPPA_REG_CR9,
HPPA_REG_CR10,
HPPA_REG_CR11,
HPPA_REG_CR12,
HPPA_REG_CR13,
HPPA_REG_CR14,
HPPA_REG_CR15,
HPPA_REG_CR16,
HPPA_REG_CR17,
HPPA_REG_CR18,
HPPA_REG_CR19,
HPPA_REG_CR20,
HPPA_REG_CR21,
HPPA_REG_CR22,
HPPA_REG_CR23,
HPPA_REG_CR24,
HPPA_REG_CR25,
HPPA_REG_CR26,
HPPA_REG_CR27,
HPPA_REG_CR28,
HPPA_REG_CR29,
HPPA_REG_CR30,
HPPA_REG_CR31,
///> Special floating point exception registers
HPPA_REG_FPE0,
HPPA_REG_FPE1,
HPPA_REG_FPE2,
HPPA_REG_FPE3,
HPPA_REG_FPE4,
HPPA_REG_FPE5,
HPPA_REG_FPE6,
HPPA_REG_FPE7,
HPPA_REG_FPE8,
HPPA_REG_FPE9,
HPPA_REG_FPE10,
HPPA_REG_FPE11,
HPPA_REG_FPE12,
HPPA_REG_FPE13,
HPPA_REG_FPE14,
HPPA_REG_FPE15,
HPPA_REG_FPE16,
HPPA_REG_FPE17,
HPPA_REG_FPE18,
HPPA_REG_FPE19,
HPPA_REG_FPE20,
HPPA_REG_FPE21,
HPPA_REG_FPE22,
HPPA_REG_FPE23,
HPPA_REG_FPE24,
HPPA_REG_FPE25,
HPPA_REG_FPE26,
HPPA_REG_FPE27,
HPPA_REG_FPE28,
HPPA_REG_FPE29,
HPPA_REG_FPE30,
HPPA_REG_FPE31,
///> Single-precision floating point registers
HPPA_REG_SP_FPR0,
HPPA_REG_SP_FPR1,
HPPA_REG_SP_FPR2,
HPPA_REG_SP_FPR3,
HPPA_REG_SP_FPR4,
HPPA_REG_SP_FPR5,
HPPA_REG_SP_FPR6,
HPPA_REG_SP_FPR7,
HPPA_REG_SP_FPR8,
HPPA_REG_SP_FPR9,
HPPA_REG_SP_FPR10,
HPPA_REG_SP_FPR11,
HPPA_REG_SP_FPR12,
HPPA_REG_SP_FPR13,
HPPA_REG_SP_FPR14,
HPPA_REG_SP_FPR15,
HPPA_REG_SP_FPR16,
HPPA_REG_SP_FPR17,
HPPA_REG_SP_FPR18,
HPPA_REG_SP_FPR19,
HPPA_REG_SP_FPR20,
HPPA_REG_SP_FPR21,
HPPA_REG_SP_FPR22,
HPPA_REG_SP_FPR23,
HPPA_REG_SP_FPR24,
HPPA_REG_SP_FPR25,
HPPA_REG_SP_FPR26,
HPPA_REG_SP_FPR27,
HPPA_REG_SP_FPR28,
HPPA_REG_SP_FPR29,
HPPA_REG_SP_FPR30,
HPPA_REG_SP_FPR31,
HPPA_REG_ENDING,
} hppa_reg;
/// HPPA instruction
typedef enum hppa_insn {
HPPA_INS_INVALID = 0,
HPPA_INS_ADD,
HPPA_INS_ADDI,
HPPA_INS_ADDIO,
HPPA_INS_ADDIT,
HPPA_INS_ADDITO,
HPPA_INS_ADDB,
HPPA_INS_ADDBT,
HPPA_INS_ADDBF,
HPPA_INS_ADDIB,
HPPA_INS_ADDIBT,
HPPA_INS_ADDIBF,
HPPA_INS_ADDIL,
HPPA_INS_ADDC,
HPPA_INS_ADDCO,
HPPA_INS_ADDL,
HPPA_INS_ADDO,
HPPA_INS_AND,
HPPA_INS_ANDCM,
HPPA_INS_B,
HPPA_INS_BB,
HPPA_INS_BE,
HPPA_INS_BL,
HPPA_INS_BLE,
HPPA_INS_BLR,
HPPA_INS_BREAK,
HPPA_INS_BV,
HPPA_INS_BVB,
HPPA_INS_BVE,
HPPA_INS_CALL,
HPPA_INS_CLDD,
HPPA_INS_CLDDS,
HPPA_INS_CLDDX,
HPPA_INS_CLDW,
HPPA_INS_CLDWS,
HPPA_INS_CLDWX,
HPPA_INS_CLRBTS,
HPPA_INS_CMPB,
HPPA_INS_CMPCLR,
HPPA_INS_CMPIB,
HPPA_INS_CMPICLR,
HPPA_INS_COMB,
HPPA_INS_COMBT,
HPPA_INS_COMBF,
HPPA_INS_COMCLR,
HPPA_INS_COMIB,
HPPA_INS_COMIBT,
HPPA_INS_COMIBF,
HPPA_INS_COMICLR,
HPPA_INS_COPR,
HPPA_INS_COPY,
HPPA_INS_CSTD,
HPPA_INS_CSTDS,
HPPA_INS_CSTDX,
HPPA_INS_CSTW,
HPPA_INS_CSTWS,
HPPA_INS_CSTWX,
HPPA_INS_DCOR,
HPPA_INS_DEP,
HPPA_INS_DEPI,
HPPA_INS_DEPD,
HPPA_INS_DEPDI,
HPPA_INS_DEPW,
HPPA_INS_DEPWI,
HPPA_INS_DIAG,
HPPA_INS_DS,
HPPA_INS_EXTRD,
HPPA_INS_EXTRS,
HPPA_INS_EXTRU,
HPPA_INS_EXTRW,
HPPA_INS_FABS,
HPPA_INS_FADD,
HPPA_INS_FCMP,
HPPA_INS_FCNV,
HPPA_INS_FCNVFF,
HPPA_INS_FCNVFX,
HPPA_INS_FCNVFXT,
HPPA_INS_FCNVXF,
HPPA_INS_FCPY,
HPPA_INS_FDC,
HPPA_INS_FDCE,
HPPA_INS_FDIV,
HPPA_INS_FIC,
HPPA_INS_FICE,
HPPA_INS_FID,
HPPA_INS_FLDD,
HPPA_INS_FLDDS,
HPPA_INS_FLDDX,
HPPA_INS_FLDW,
HPPA_INS_FLDWS,
HPPA_INS_FLDWX,
HPPA_INS_FMPY,
HPPA_INS_FMPYADD,
HPPA_INS_FMPYFADD,
HPPA_INS_FMPYNFADD,
HPPA_INS_FMPYSUB,
HPPA_INS_FNEG,
HPPA_INS_FNEGABS,
HPPA_INS_FREM,
HPPA_INS_FRND,
HPPA_INS_FSQRT,
HPPA_INS_FSTD,
HPPA_INS_FSTDS,
HPPA_INS_FSTDX,
HPPA_INS_FSTW,
HPPA_INS_FSTWS,
HPPA_INS_FSTWX,
HPPA_INS_FSTQS,
HPPA_INS_FSTQX,
HPPA_INS_FSUB,
HPPA_INS_FTEST,
HPPA_INS_GATE,
HPPA_INS_GFR,
HPPA_INS_GFW,
HPPA_INS_GRSHDW,
HPPA_INS_HADD,
HPPA_INS_HAVG,
HPPA_INS_HSHL,
HPPA_INS_HSHLADD,
HPPA_INS_HSHR,
HPPA_INS_HSHRADD,
HPPA_INS_HSUB,
HPPA_INS_IDTLBA,
HPPA_INS_IDTLBP,
HPPA_INS_IDTLBT,
HPPA_INS_IDCOR,
HPPA_INS_IITLBA,
HPPA_INS_IITLBP,
HPPA_INS_IITLBT,
HPPA_INS_LCI,
HPPA_INS_LDB,
HPPA_INS_LDBS,
HPPA_INS_LDBX,
HPPA_INS_LDCD,
HPPA_INS_LDCW,
HPPA_INS_LDCWS,
HPPA_INS_LDCWX,
HPPA_INS_LDD,
HPPA_INS_LDDA,
HPPA_INS_LDH,
HPPA_INS_LDHS,
HPPA_INS_LDHX,
HPPA_INS_LDI,
HPPA_INS_LDIL,
HPPA_INS_LDO,
HPPA_INS_LDSID,
HPPA_INS_LDW,
HPPA_INS_LDWA,
HPPA_INS_LDWAS,
HPPA_INS_LDWAX,
HPPA_INS_LDWM,
HPPA_INS_LDWS,
HPPA_INS_LDWX,
HPPA_INS_LPA,
HPPA_INS_MFCPU,
HPPA_INS_MFCTL,
HPPA_INS_MFIA,
HPPA_INS_MFSP,
HPPA_INS_MIXH,
HPPA_INS_MIXW,
HPPA_INS_MOVB,
HPPA_INS_MOVIB,
HPPA_INS_MTCPU,
HPPA_INS_MTCTL,
HPPA_INS_MTSAR,
HPPA_INS_MTSARCM,
HPPA_INS_MTSM,
HPPA_INS_MTSP,
HPPA_INS_NOP,
HPPA_INS_OR,
HPPA_INS_PDC,
HPPA_INS_PDTLB,
HPPA_INS_PDTLBE,
HPPA_INS_PERMH,
HPPA_INS_PITLB,
HPPA_INS_PITLBE,
HPPA_INS_PMDIS,
HPPA_INS_PMENB,
HPPA_INS_POPBTS,
HPPA_INS_PROBE,
HPPA_INS_PROBEI,
HPPA_INS_PROBER,
HPPA_INS_PROBERI,
HPPA_INS_PROBEW,
HPPA_INS_PROBEWI,
HPPA_INS_PUSHBTS,
HPPA_INS_PUSHNOM,
HPPA_INS_RET,
HPPA_INS_RFI,
HPPA_INS_RFIR,
HPPA_INS_RSM,
HPPA_INS_SHDWGR,
HPPA_INS_SHLADD,
HPPA_INS_SH1ADD,
HPPA_INS_SH1ADDL,
HPPA_INS_SH1ADDO,
HPPA_INS_SH2ADD,
HPPA_INS_SH2ADDL,
HPPA_INS_SH2ADDO,
HPPA_INS_SH3ADD,
HPPA_INS_SH3ADDL,
HPPA_INS_SH3ADDO,
HPPA_INS_SHD,
HPPA_INS_SHRPD,
HPPA_INS_SHRPW,
HPPA_INS_SPOP0,
HPPA_INS_SPOP1,
HPPA_INS_SPOP2,
HPPA_INS_SPOP3,
HPPA_INS_SSM,
HPPA_INS_STB,
HPPA_INS_STBS,
HPPA_INS_STBY,
HPPA_INS_STBYS,
HPPA_INS_STD,
HPPA_INS_STDA,
HPPA_INS_STDBY,
HPPA_INS_STH,
HPPA_INS_STHS,
HPPA_INS_STW,
HPPA_INS_STWA,
HPPA_INS_STWAS,
HPPA_INS_STWS,
HPPA_INS_STWM,
HPPA_INS_SUB,
HPPA_INS_SUBB,
HPPA_INS_SUBBO,
HPPA_INS_SUBI,
HPPA_INS_SUBIO,
HPPA_INS_SUBO,
HPPA_INS_SUBT,
HPPA_INS_SUBTO,
HPPA_INS_SYNC,
HPPA_INS_SYNCDMA,
HPPA_INS_TOCDIS,
HPPA_INS_TOCEN,
HPPA_INS_UADDCM,
HPPA_INS_UADDCMT,
HPPA_INS_UXOR,
HPPA_INS_VDEP,
HPPA_INS_VDEPI,
HPPA_INS_VEXTRS,
HPPA_INS_VEXTRU,
HPPA_INS_VSHD,
HPPA_INS_XMPYU,
HPPA_INS_XOR,
HPPA_INS_ZDEP,
HPPA_INS_ZDEPI,
HPPA_INS_ZVDEP,
HPPA_INS_ZVDEPI,
HPPA_INS_ENDING
} hppa_insn;
/// HPPA space select operand
typedef struct hppa_mem {
hppa_reg base;
hppa_reg space;
cs_ac_type base_access;
} hppa_mem;
// Instruction operand
typedef struct cs_hppa_op {
hppa_op_type type; ///< operand type
union {
hppa_reg reg; ///< register value for REG operand
int64_t imm; ///< immediate value for IMM operand
hppa_mem mem;
};
cs_ac_type access;
} cs_hppa_op;
// Instruction structure
typedef struct cs_hppa {
// Number of operands of this instruction,
// or 0 when instruction has no operand.
uint8_t op_count;
cs_hppa_op operands[NUM_HPPA_OPS]; ///< operands for hppa instruction.
} cs_hppa;
/// HPPA modifiers type. Can be string (most of them) or int (uid, sop)
typedef enum hppa_modifier_type {
HPPA_MOD_STR = 0,
HPPA_MOD_INT = 1
} hppa_modifier_type;
/// hppa string/integer modifier
typedef struct hppa_modifier {
hppa_modifier_type type;
union {
char str_mod[HPPA_STR_MODIFIER_LEN];
uint32_t int_mod;
};
} hppa_modifier;
// Additional instruction info
typedef struct hppa_ext {
hppa_modifier modifiers[HPPA_MAX_MODIFIERS_LEN]; ///< instruction modifiers array
uint8_t mod_num; ///< number of modifiers of current instruction
bool b_writeble; ///< true if some load/store modifier has modify base register bit
bool is_alternative; ///< true if some modifier affects instruction format
} hppa_ext;
// Group of HPPA instructions
typedef enum hppa_insn_group {
HPPA_GRP_INVALID = 0, ///< = CS_GRP_INVALID
HPPA_GRP_COMPUTATION = 128,
HPPA_GRP_MULTIMEDIA,
HPPA_GRP_MEM_REF,
HPPA_GRP_LONG_IMM,
HPPA_GRP_BRANCH,
HPPA_GRP_SYSCTRL,
HPPA_GRP_ASSIST,
HPPA_GRP_FLOAT,
HPPA_GRP_PERFMON,
HPPA_GRP_ENDING,
} hppa_insn_group;
#ifdef __cplusplus
}
#endif
#endif
external/capstone/include/capstone/loongarch.h
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external/capstone/include/capstone/m680x.h
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#ifndef CAPSTONE_M680X_H
#define CAPSTONE_M680X_H
/* Capstone Disassembly Engine */
/* M680X Backend by Wolfgang Schwotzer <wolfgang.schwotzer@gmx.net> 2017 */
#ifdef __cplusplus
extern "C" {
#endif
#include "platform.h"
#include "cs_operand.h"
#ifdef _MSC_VER
#pragma warning(disable:4201)
#endif
#define M680X_OPERAND_COUNT 9
/// M680X registers and special registers
typedef enum m680x_reg {
M680X_REG_INVALID = 0,
M680X_REG_A, ///< M6800/1/2/3/9, HD6301/9
M680X_REG_B, ///< M6800/1/2/3/9, HD6301/9
M680X_REG_E, ///< HD6309
M680X_REG_F, ///< HD6309
M680X_REG_0, ///< HD6309
M680X_REG_D, ///< M6801/3/9, HD6301/9
M680X_REG_W, ///< HD6309
M680X_REG_CC, ///< M6800/1/2/3/9, M6301/9
M680X_REG_DP, ///< M6809/M6309
M680X_REG_MD, ///< M6309
M680X_REG_HX, ///< M6808
M680X_REG_H, ///< M6808
M680X_REG_X, ///< M6800/1/2/3/9, M6301/9
M680X_REG_Y, ///< M6809/M6309
M680X_REG_S, ///< M6809/M6309
M680X_REG_U, ///< M6809/M6309
M680X_REG_V, ///< M6309
M680X_REG_Q, ///< M6309
M680X_REG_PC, ///< M6800/1/2/3/9, M6301/9
M680X_REG_TMP2, ///< CPU12
M680X_REG_TMP3, ///< CPU12
M680X_REG_ENDING, ///< <-- mark the end of the list of registers
} m680x_reg;
/// Operand type for instruction's operands
typedef enum m680x_op_type {
M680X_OP_INVALID = CS_OP_INVALID, ///< = CS_OP_INVALID (Uninitialized).
M680X_OP_REGISTER = CS_OP_REG, ///< = Register operand.
M680X_OP_IMMEDIATE = CS_OP_IMM, ///< = Immediate operand.
M680X_OP_INDEXED = CS_OP_SPECIAL + 0, ///< = Indexed addressing operand.
M680X_OP_EXTENDED = CS_OP_SPECIAL + 1, ///< = Extended addressing operand.
M680X_OP_DIRECT = CS_OP_SPECIAL + 2, ///< = Direct addressing operand.
M680X_OP_RELATIVE = CS_OP_SPECIAL + 3, ///< = Relative addressing operand.
M680X_OP_CONSTANT = CS_OP_SPECIAL + 4, ///< = constant operand (Displayed as number only).
///< Used e.g. for a bit index or page number.
} m680x_op_type;
// Supported bit values for mem.idx.offset_bits
#define M680X_OFFSET_NONE 0
#define M680X_OFFSET_BITS_5 5
#define M680X_OFFSET_BITS_8 8
#define M680X_OFFSET_BITS_9 9
#define M680X_OFFSET_BITS_16 16
// Supported bit flags for mem.idx.flags
// These flags can be combined
#define M680X_IDX_INDIRECT 1
#define M680X_IDX_NO_COMMA 2
#define M680X_IDX_POST_INC_DEC 4
/// Instruction's operand referring to indexed addressing
typedef struct m680x_op_idx {
m680x_reg base_reg; ///< base register (or M680X_REG_INVALID if
///< irrelevant)
m680x_reg offset_reg; ///< offset register (or M680X_REG_INVALID if
///< irrelevant)
int16_t offset; ///< 5-,8- or 16-bit offset. See also offset_bits.
uint16_t offset_addr; ///< = offset addr. if base_reg == M680X_REG_PC.
///< calculated as offset + PC
uint8_t offset_bits; ///< offset width in bits for indexed addressing
int8_t inc_dec; ///< inc. or dec. value:
///< 0: no inc-/decrement
///< 1 .. 8: increment by 1 .. 8
///< -1 .. -8: decrement by 1 .. 8
///< if flag M680X_IDX_POST_INC_DEC set it is post
///< inc-/decrement otherwise pre inc-/decrement
uint8_t flags; ///< 8-bit flags (see above)
} m680x_op_idx;
/// Instruction's memory operand referring to relative addressing (Bcc/LBcc)
typedef struct m680x_op_rel {
uint16_t address; ///< The absolute address.
///< calculated as PC + offset. PC is the first
///< address after the instruction.
int16_t offset; ///< the offset/displacement value
} m680x_op_rel;
/// Instruction's operand referring to extended addressing
typedef struct m680x_op_ext {
uint16_t address; ///< The absolute address
bool indirect; ///< true if extended indirect addressing
} m680x_op_ext;
/// Instruction operand
typedef struct cs_m680x_op {
m680x_op_type type;
union {
int32_t imm; ///< immediate value for IMM operand
m680x_reg reg; ///< register value for REG operand
m680x_op_idx idx; ///< Indexed addressing operand
m680x_op_rel rel; ///< Relative address. operand (Bcc/LBcc)
m680x_op_ext ext; ///< Extended address
uint8_t direct_addr; ///<</ Direct address (lower 8-bit)
uint8_t const_val; ///< constant value (bit index, page nr.)
};
uint8_t size; ///< size of this operand (in bytes)
/// How is this operand accessed? (READ, WRITE or READ|WRITE)
/// This field is combined of cs_ac_type.
/// NOTE: this field is irrelevant if engine is compiled in DIET
cs_ac_type access;
} cs_m680x_op;
/// Group of M680X instructions
typedef enum m680x_group_type {
M680X_GRP_INVALID = 0, /// = CS_GRP_INVALID
// Generic groups
// all jump instructions (conditional+direct+indirect jumps)
M680X_GRP_JUMP, ///< = CS_GRP_JUMP
// all call instructions
M680X_GRP_CALL, ///< = CS_GRP_CALL
// all return instructions
M680X_GRP_RET, ///< = CS_GRP_RET
// all interrupt instructions (int+syscall)
M680X_GRP_INT, ///< = CS_GRP_INT
// all interrupt return instructions
M680X_GRP_IRET, ///< = CS_GRP_IRET
// all privileged instructions
M680X_GRP_PRIV, ///< = CS_GRP_PRIVILEDGE; not used
// all relative branching instructions
M680X_GRP_BRAREL, ///< = CS_GRP_BRANCH_RELATIVE
// Architecture-specific groups
M680X_GRP_ENDING, // <-- mark the end of the list of groups
} m680x_group_type;
// M680X instruction flags:
/// The first (register) operand is part of the
/// instruction mnemonic
#define M680X_FIRST_OP_IN_MNEM 1
/// The second (register) operand is part of the
/// instruction mnemonic
#define M680X_SECOND_OP_IN_MNEM 2
/// The M680X instruction and its operands
typedef struct cs_m680x {
uint8_t flags; ///< See: M680X instruction flags
uint8_t op_count; ///< number of operands for the instruction or 0
cs_m680x_op operands[M680X_OPERAND_COUNT]; ///< operands for this insn.
} cs_m680x;
/// M680X instruction IDs
typedef enum m680x_insn {
M680X_INS_INVLD = 0,
M680X_INS_ABA, ///< M6800/1/2/3
M680X_INS_ABX,
M680X_INS_ABY,
M680X_INS_ADC,
M680X_INS_ADCA,
M680X_INS_ADCB,
M680X_INS_ADCD,
M680X_INS_ADCR,
M680X_INS_ADD,
M680X_INS_ADDA,
M680X_INS_ADDB,
M680X_INS_ADDD,
M680X_INS_ADDE,
M680X_INS_ADDF,
M680X_INS_ADDR,
M680X_INS_ADDW,
M680X_INS_AIM,
M680X_INS_AIS,
M680X_INS_AIX,
M680X_INS_AND,
M680X_INS_ANDA,
M680X_INS_ANDB,
M680X_INS_ANDCC,
M680X_INS_ANDD,
M680X_INS_ANDR,
M680X_INS_ASL,
M680X_INS_ASLA,
M680X_INS_ASLB,
M680X_INS_ASLD, ///< or LSLD
M680X_INS_ASR,
M680X_INS_ASRA,
M680X_INS_ASRB,
M680X_INS_ASRD,
M680X_INS_ASRX,
M680X_INS_BAND,
M680X_INS_BCC, ///< or BHS
M680X_INS_BCLR,
M680X_INS_BCS, ///< or BLO
M680X_INS_BEOR,
M680X_INS_BEQ,
M680X_INS_BGE,
M680X_INS_BGND,
M680X_INS_BGT,
M680X_INS_BHCC,
M680X_INS_BHCS,
M680X_INS_BHI,
M680X_INS_BIAND,
M680X_INS_BIEOR,
M680X_INS_BIH,
M680X_INS_BIL,
M680X_INS_BIOR,
M680X_INS_BIT,
M680X_INS_BITA,
M680X_INS_BITB,
M680X_INS_BITD,
M680X_INS_BITMD,
M680X_INS_BLE,
M680X_INS_BLS,
M680X_INS_BLT,
M680X_INS_BMC,
M680X_INS_BMI,
M680X_INS_BMS,
M680X_INS_BNE,
M680X_INS_BOR,
M680X_INS_BPL,
M680X_INS_BRCLR,
M680X_INS_BRSET,
M680X_INS_BRA,
M680X_INS_BRN,
M680X_INS_BSET,
M680X_INS_BSR,
M680X_INS_BVC,
M680X_INS_BVS,
M680X_INS_CALL,
M680X_INS_CBA, ///< M6800/1/2/3
M680X_INS_CBEQ,
M680X_INS_CBEQA,
M680X_INS_CBEQX,
M680X_INS_CLC, ///< M6800/1/2/3
M680X_INS_CLI, ///< M6800/1/2/3
M680X_INS_CLR,
M680X_INS_CLRA,
M680X_INS_CLRB,
M680X_INS_CLRD,
M680X_INS_CLRE,
M680X_INS_CLRF,
M680X_INS_CLRH,
M680X_INS_CLRW,
M680X_INS_CLRX,
M680X_INS_CLV, ///< M6800/1/2/3
M680X_INS_CMP,
M680X_INS_CMPA,
M680X_INS_CMPB,
M680X_INS_CMPD,
M680X_INS_CMPE,
M680X_INS_CMPF,
M680X_INS_CMPR,
M680X_INS_CMPS,
M680X_INS_CMPU,
M680X_INS_CMPW,
M680X_INS_CMPX,
M680X_INS_CMPY,
M680X_INS_COM,
M680X_INS_COMA,
M680X_INS_COMB,
M680X_INS_COMD,
M680X_INS_COME,
M680X_INS_COMF,
M680X_INS_COMW,
M680X_INS_COMX,
M680X_INS_CPD,
M680X_INS_CPHX,
M680X_INS_CPS,
M680X_INS_CPX, ///< M6800/1/2/3
M680X_INS_CPY,
M680X_INS_CWAI,
M680X_INS_DAA,
M680X_INS_DBEQ,
M680X_INS_DBNE,
M680X_INS_DBNZ,
M680X_INS_DBNZA,
M680X_INS_DBNZX,
M680X_INS_DEC,
M680X_INS_DECA,
M680X_INS_DECB,
M680X_INS_DECD,
M680X_INS_DECE,
M680X_INS_DECF,
M680X_INS_DECW,
M680X_INS_DECX,
M680X_INS_DES, ///< M6800/1/2/3
M680X_INS_DEX, ///< M6800/1/2/3
M680X_INS_DEY,
M680X_INS_DIV,
M680X_INS_DIVD,
M680X_INS_DIVQ,
M680X_INS_EDIV,
M680X_INS_EDIVS,
M680X_INS_EIM,
M680X_INS_EMACS,
M680X_INS_EMAXD,
M680X_INS_EMAXM,
M680X_INS_EMIND,
M680X_INS_EMINM,
M680X_INS_EMUL,
M680X_INS_EMULS,
M680X_INS_EOR,
M680X_INS_EORA,
M680X_INS_EORB,
M680X_INS_EORD,
M680X_INS_EORR,
M680X_INS_ETBL,
M680X_INS_EXG,
M680X_INS_FDIV,
M680X_INS_IBEQ,
M680X_INS_IBNE,
M680X_INS_IDIV,
M680X_INS_IDIVS,
M680X_INS_ILLGL,
M680X_INS_INC,
M680X_INS_INCA,
M680X_INS_INCB,
M680X_INS_INCD,
M680X_INS_INCE,
M680X_INS_INCF,
M680X_INS_INCW,
M680X_INS_INCX,
M680X_INS_INS, ///< M6800/1/2/3
M680X_INS_INX, ///< M6800/1/2/3
M680X_INS_INY,
M680X_INS_JMP,
M680X_INS_JSR,
M680X_INS_LBCC, ///< or LBHS
M680X_INS_LBCS, ///< or LBLO
M680X_INS_LBEQ,
M680X_INS_LBGE,
M680X_INS_LBGT,
M680X_INS_LBHI,
M680X_INS_LBLE,
M680X_INS_LBLS,
M680X_INS_LBLT,
M680X_INS_LBMI,
M680X_INS_LBNE,
M680X_INS_LBPL,
M680X_INS_LBRA,
M680X_INS_LBRN,
M680X_INS_LBSR,
M680X_INS_LBVC,
M680X_INS_LBVS,
M680X_INS_LDA,
M680X_INS_LDAA, ///< M6800/1/2/3
M680X_INS_LDAB, ///< M6800/1/2/3
M680X_INS_LDB,
M680X_INS_LDBT,
M680X_INS_LDD,
M680X_INS_LDE,
M680X_INS_LDF,
M680X_INS_LDHX,
M680X_INS_LDMD,
M680X_INS_LDQ,
M680X_INS_LDS,
M680X_INS_LDU,
M680X_INS_LDW,
M680X_INS_LDX,
M680X_INS_LDY,
M680X_INS_LEAS,
M680X_INS_LEAU,
M680X_INS_LEAX,
M680X_INS_LEAY,
M680X_INS_LSL,
M680X_INS_LSLA,
M680X_INS_LSLB,
M680X_INS_LSLD,
M680X_INS_LSLX,
M680X_INS_LSR,
M680X_INS_LSRA,
M680X_INS_LSRB,
M680X_INS_LSRD, ///< or ASRD
M680X_INS_LSRW,
M680X_INS_LSRX,
M680X_INS_MAXA,
M680X_INS_MAXM,
M680X_INS_MEM,
M680X_INS_MINA,
M680X_INS_MINM,
M680X_INS_MOV,
M680X_INS_MOVB,
M680X_INS_MOVW,
M680X_INS_MUL,
M680X_INS_MULD,
M680X_INS_NEG,
M680X_INS_NEGA,
M680X_INS_NEGB,
M680X_INS_NEGD,
M680X_INS_NEGX,
M680X_INS_NOP,
M680X_INS_NSA,
M680X_INS_OIM,
M680X_INS_ORA,
M680X_INS_ORAA, ///< M6800/1/2/3
M680X_INS_ORAB, ///< M6800/1/2/3
M680X_INS_ORB,
M680X_INS_ORCC,
M680X_INS_ORD,
M680X_INS_ORR,
M680X_INS_PSHA, ///< M6800/1/2/3
M680X_INS_PSHB, ///< M6800/1/2/3
M680X_INS_PSHC,
M680X_INS_PSHD,
M680X_INS_PSHH,
M680X_INS_PSHS,
M680X_INS_PSHSW,
M680X_INS_PSHU,
M680X_INS_PSHUW,
M680X_INS_PSHX, ///< M6800/1/2/3
M680X_INS_PSHY,
M680X_INS_PULA, ///< M6800/1/2/3
M680X_INS_PULB, ///< M6800/1/2/3
M680X_INS_PULC,
M680X_INS_PULD,
M680X_INS_PULH,
M680X_INS_PULS,
M680X_INS_PULSW,
M680X_INS_PULU,
M680X_INS_PULUW,
M680X_INS_PULX, ///< M6800/1/2/3
M680X_INS_PULY,
M680X_INS_REV,
M680X_INS_REVW,
M680X_INS_ROL,
M680X_INS_ROLA,
M680X_INS_ROLB,
M680X_INS_ROLD,
M680X_INS_ROLW,
M680X_INS_ROLX,
M680X_INS_ROR,
M680X_INS_RORA,
M680X_INS_RORB,
M680X_INS_RORD,
M680X_INS_RORW,
M680X_INS_RORX,
M680X_INS_RSP,
M680X_INS_RTC,
M680X_INS_RTI,
M680X_INS_RTS,
M680X_INS_SBA, ///< M6800/1/2/3
M680X_INS_SBC,
M680X_INS_SBCA,
M680X_INS_SBCB,
M680X_INS_SBCD,
M680X_INS_SBCR,
M680X_INS_SEC,
M680X_INS_SEI,
M680X_INS_SEV,
M680X_INS_SEX,
M680X_INS_SEXW,
M680X_INS_SLP,
M680X_INS_STA,
M680X_INS_STAA, ///< M6800/1/2/3
M680X_INS_STAB, ///< M6800/1/2/3
M680X_INS_STB,
M680X_INS_STBT,
M680X_INS_STD,
M680X_INS_STE,
M680X_INS_STF,
M680X_INS_STOP,
M680X_INS_STHX,
M680X_INS_STQ,
M680X_INS_STS,
M680X_INS_STU,
M680X_INS_STW,
M680X_INS_STX,
M680X_INS_STY,
M680X_INS_SUB,
M680X_INS_SUBA,
M680X_INS_SUBB,
M680X_INS_SUBD,
M680X_INS_SUBE,
M680X_INS_SUBF,
M680X_INS_SUBR,
M680X_INS_SUBW,
M680X_INS_SWI,
M680X_INS_SWI2,
M680X_INS_SWI3,
M680X_INS_SYNC,
M680X_INS_TAB, ///< M6800/1/2/3
M680X_INS_TAP, ///< M6800/1/2/3
M680X_INS_TAX,
M680X_INS_TBA, ///< M6800/1/2/3
M680X_INS_TBEQ,
M680X_INS_TBL,
M680X_INS_TBNE,
M680X_INS_TEST,
M680X_INS_TFM,
M680X_INS_TFR,
M680X_INS_TIM,
M680X_INS_TPA, ///< M6800/1/2/3
M680X_INS_TST,
M680X_INS_TSTA,
M680X_INS_TSTB,
M680X_INS_TSTD,
M680X_INS_TSTE,
M680X_INS_TSTF,
M680X_INS_TSTW,
M680X_INS_TSTX,
M680X_INS_TSX, ///< M6800/1/2/3
M680X_INS_TSY,
M680X_INS_TXA,
M680X_INS_TXS, ///< M6800/1/2/3
M680X_INS_TYS,
M680X_INS_WAI, ///< M6800/1/2/3
M680X_INS_WAIT,
M680X_INS_WAV,
M680X_INS_WAVR,
M680X_INS_XGDX, ///< HD6301
M680X_INS_XGDY,
M680X_INS_ENDING, // <-- mark the end of the list of instructions
} m680x_insn;
#ifdef __cplusplus
}
#endif
#endif
external/capstone/include/capstone/m68k.h
Vendored
+614
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@@ -0,0 +1,614 @@
#ifndef CAPSTONE_M68K_H
#define CAPSTONE_M68K_H
/* Capstone Disassembly Engine */
/* By Daniel Collin <daniel@collin.com>, 2015-2016 */
#ifdef __cplusplus
extern "C" {
#endif
#include "platform.h"
#include "cs_operand.h"
#ifdef _MSC_VER
#pragma warning(disable:4201)
#endif
#define M68K_OPERAND_COUNT 4
/// M68K registers and special registers
typedef enum m68k_reg {
M68K_REG_INVALID = 0,
M68K_REG_D0,
M68K_REG_D1,
M68K_REG_D2,
M68K_REG_D3,
M68K_REG_D4,
M68K_REG_D5,
M68K_REG_D6,
M68K_REG_D7,
M68K_REG_A0,
M68K_REG_A1,
M68K_REG_A2,
M68K_REG_A3,
M68K_REG_A4,
M68K_REG_A5,
M68K_REG_A6,
M68K_REG_A7,
M68K_REG_FP0,
M68K_REG_FP1,
M68K_REG_FP2,
M68K_REG_FP3,
M68K_REG_FP4,
M68K_REG_FP5,
M68K_REG_FP6,
M68K_REG_FP7,
M68K_REG_PC,
M68K_REG_SR,
M68K_REG_CCR,
M68K_REG_SFC,
M68K_REG_DFC,
M68K_REG_USP,
M68K_REG_VBR,
M68K_REG_CACR,
M68K_REG_CAAR,
M68K_REG_MSP,
M68K_REG_ISP,
M68K_REG_TC,
M68K_REG_ITT0,
M68K_REG_ITT1,
M68K_REG_DTT0,
M68K_REG_DTT1,
M68K_REG_MMUSR,
M68K_REG_URP,
M68K_REG_SRP,
M68K_REG_FPCR,
M68K_REG_FPSR,
M68K_REG_FPIAR,
M68K_REG_ENDING, // <-- mark the end of the list of registers
} m68k_reg;
/// M68K Addressing Modes
typedef enum m68k_address_mode {
M68K_AM_NONE = 0, ///< No address mode.
M68K_AM_REG_DIRECT_DATA, ///< Register Direct - Data
M68K_AM_REG_DIRECT_ADDR, ///< Register Direct - Address
M68K_AM_REGI_ADDR, ///< Register Indirect - Address
M68K_AM_REGI_ADDR_POST_INC, ///< Register Indirect - Address with Postincrement
M68K_AM_REGI_ADDR_PRE_DEC, ///< Register Indirect - Address with Predecrement
M68K_AM_REGI_ADDR_DISP, ///< Register Indirect - Address with Displacement
M68K_AM_AREGI_INDEX_8_BIT_DISP, ///< Address Register Indirect With Index- 8-bit displacement
M68K_AM_AREGI_INDEX_BASE_DISP, ///< Address Register Indirect With Index- Base displacement
M68K_AM_MEMI_POST_INDEX, ///< Memory indirect - Postindex
M68K_AM_MEMI_PRE_INDEX, ///< Memory indirect - Preindex
M68K_AM_PCI_DISP, ///< Program Counter Indirect - with Displacement
M68K_AM_PCI_INDEX_8_BIT_DISP, ///< Program Counter Indirect with Index - with 8-Bit Displacement
M68K_AM_PCI_INDEX_BASE_DISP, ///< Program Counter Indirect with Index - with Base Displacement
M68K_AM_PC_MEMI_POST_INDEX, ///< Program Counter Memory Indirect - Postindexed
M68K_AM_PC_MEMI_PRE_INDEX, ///< Program Counter Memory Indirect - Preindexed
M68K_AM_ABSOLUTE_DATA_SHORT, ///< Absolute Data Addressing - Short
M68K_AM_ABSOLUTE_DATA_LONG, ///< Absolute Data Addressing - Long
M68K_AM_IMMEDIATE, ///< Immediate value
M68K_AM_BRANCH_DISPLACEMENT, ///< Address as displacement from (PC+2) used by branches
} m68k_address_mode;
/// Operand type for instruction's operands
typedef enum m68k_op_type {
M68K_OP_INVALID = CS_OP_INVALID, ///< = CS_OP_INVALID (Uninitialized).
M68K_OP_REG = CS_OP_REG, ///< = CS_OP_REG (Register operand).
M68K_OP_IMM = CS_OP_IMM, ///< = CS_OP_IMM (Immediate operand).
M68K_OP_FP_SINGLE = CS_OP_SPECIAL + 0, ///< single precision Floating-Point operand
M68K_OP_FP_DOUBLE = CS_OP_SPECIAL + 1, ///< double precision Floating-Point operand
M68K_OP_REG_BITS = CS_OP_SPECIAL + 2, ///< Register bits move
M68K_OP_REG_PAIR = CS_OP_SPECIAL + 3, ///< Register pair in the same op (upper 4 bits for first reg, lower for second)
M68K_OP_BR_DISP = CS_OP_SPECIAL + 4, ///< Branch displacement
M68K_OP_MEM = CS_OP_MEM, ///< = CS_OP_MEM (Memory operand).
} m68k_op_type;
/// Instruction's operand referring to memory
/// This is associated with M68K_OP_MEM operand type above
typedef struct m68k_op_mem {
m68k_reg base_reg; ///< base register (or M68K_REG_INVALID if irrelevant)
m68k_reg index_reg; ///< index register (or M68K_REG_INVALID if irrelevant)
m68k_reg in_base_reg; ///< indirect base register (or M68K_REG_INVALID if irrelevant)
uint32_t in_disp; ///< indirect displacement
uint32_t out_disp; ///< other displacement
int16_t disp; ///< displacement value
uint8_t scale; ///< scale for index register
uint8_t bitfield; ///< set to true if the two values below should be used
uint8_t width; ///< used for bf* instructions
uint8_t offset; ///< used for bf* instructions
uint8_t index_size; ///< 0 = w, 1 = l
} m68k_op_mem;
/// Operand type for instruction's operands
typedef enum m68k_op_br_disp_size {
M68K_OP_BR_DISP_SIZE_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized).
M68K_OP_BR_DISP_SIZE_BYTE = 1, ///< signed 8-bit displacement
M68K_OP_BR_DISP_SIZE_WORD = 2, ///< signed 16-bit displacement
M68K_OP_BR_DISP_SIZE_LONG = 4, ///< signed 32-bit displacement
} m68k_op_br_disp_size;
typedef struct m68k_op_br_disp {
int32_t disp; ///< displacement value
uint8_t disp_size; ///< Size from m68k_op_br_disp_size type above
} m68k_op_br_disp;
/// Register pair in one operand.
typedef struct cs_m68k_op_reg_pair {
m68k_reg reg_0;
m68k_reg reg_1;
} cs_m68k_op_reg_pair;
/// Instruction operand
typedef struct cs_m68k_op {
union {
uint64_t imm; ///< immediate value for IMM operand
double dimm; ///< double imm
float simm; ///< float imm
m68k_reg reg; ///< register value for REG operand
cs_m68k_op_reg_pair reg_pair; ///< register pair in one operand
};
m68k_op_mem mem; ///< data when operand is targeting memory
m68k_op_br_disp br_disp; ///< data when operand is a branch displacement
uint32_t register_bits; ///< register bits for movem etc. (always in d0-d7, a0-a7, fp0 - fp7 order)
m68k_op_type type;
m68k_address_mode address_mode; ///< M68K addressing mode for this op
} cs_m68k_op;
/// Operation size of the CPU instructions
typedef enum m68k_cpu_size {
M68K_CPU_SIZE_NONE = 0, ///< unsized or unspecified
M68K_CPU_SIZE_BYTE = 1, ///< 1 byte in size
M68K_CPU_SIZE_WORD = 2, ///< 2 bytes in size
M68K_CPU_SIZE_LONG = 4, ///< 4 bytes in size
} m68k_cpu_size;
/// Operation size of the FPU instructions (Notice that FPU instruction can also use CPU sizes if needed)
typedef enum m68k_fpu_size {
M68K_FPU_SIZE_NONE = 0, ///< unsized like fsave/frestore
M68K_FPU_SIZE_SINGLE = 4, ///< 4 byte in size (single float)
M68K_FPU_SIZE_DOUBLE = 8, ///< 8 byte in size (double)
M68K_FPU_SIZE_EXTENDED = 12, ///< 12 byte in size (extended real format)
} m68k_fpu_size;
/// Type of size that is being used for the current instruction
typedef enum m68k_size_type {
M68K_SIZE_TYPE_INVALID = 0,
M68K_SIZE_TYPE_CPU,
M68K_SIZE_TYPE_FPU,
} m68k_size_type;
/// Operation size of the current instruction (NOT the actually size of instruction)
typedef struct m68k_op_size {
m68k_size_type type;
union {
m68k_cpu_size cpu_size;
m68k_fpu_size fpu_size;
};
} m68k_op_size;
/// The M68K instruction and its operands
typedef struct cs_m68k {
// Number of operands of this instruction or 0 when instruction has no operand.
cs_m68k_op operands[M68K_OPERAND_COUNT]; ///< operands for this instruction.
m68k_op_size op_size; ///< size of data operand works on in bytes (.b, .w, .l, etc)
uint8_t op_count; ///< number of operands for the instruction
} cs_m68k;
/// M68K instruction
typedef enum m68k_insn {
M68K_INS_INVALID = 0,
M68K_INS_ABCD,
M68K_INS_ADD,
M68K_INS_ADDA,
M68K_INS_ADDI,
M68K_INS_ADDQ,
M68K_INS_ADDX,
M68K_INS_AND,
M68K_INS_ANDI,
M68K_INS_ASL,
M68K_INS_ASR,
M68K_INS_BHS,
M68K_INS_BLO,
M68K_INS_BHI,
M68K_INS_BLS,
M68K_INS_BCC,
M68K_INS_BCS,
M68K_INS_BNE,
M68K_INS_BEQ,
M68K_INS_BVC,
M68K_INS_BVS,
M68K_INS_BPL,
M68K_INS_BMI,
M68K_INS_BGE,
M68K_INS_BLT,
M68K_INS_BGT,
M68K_INS_BLE,
M68K_INS_BRA,
M68K_INS_BSR,
M68K_INS_BCHG,
M68K_INS_BCLR,
M68K_INS_BSET,
M68K_INS_BTST,
M68K_INS_BFCHG,
M68K_INS_BFCLR,
M68K_INS_BFEXTS,
M68K_INS_BFEXTU,
M68K_INS_BFFFO,
M68K_INS_BFINS,
M68K_INS_BFSET,
M68K_INS_BFTST,
M68K_INS_BKPT,
M68K_INS_CALLM,
M68K_INS_CAS,
M68K_INS_CAS2,
M68K_INS_CHK,
M68K_INS_CHK2,
M68K_INS_CLR,
M68K_INS_CMP,
M68K_INS_CMPA,
M68K_INS_CMPI,
M68K_INS_CMPM,
M68K_INS_CMP2,
M68K_INS_CINVL,
M68K_INS_CINVP,
M68K_INS_CINVA,
M68K_INS_CPUSHL,
M68K_INS_CPUSHP,
M68K_INS_CPUSHA,
M68K_INS_DBT,
M68K_INS_DBF,
M68K_INS_DBHI,
M68K_INS_DBLS,
M68K_INS_DBCC,
M68K_INS_DBCS,
M68K_INS_DBNE,
M68K_INS_DBEQ,
M68K_INS_DBVC,
M68K_INS_DBVS,
M68K_INS_DBPL,
M68K_INS_DBMI,
M68K_INS_DBGE,
M68K_INS_DBLT,
M68K_INS_DBGT,
M68K_INS_DBLE,
M68K_INS_DBRA,
M68K_INS_DIVS,
M68K_INS_DIVSL,
M68K_INS_DIVU,
M68K_INS_DIVUL,
M68K_INS_EOR,
M68K_INS_EORI,
M68K_INS_EXG,
M68K_INS_EXT,
M68K_INS_EXTB,
M68K_INS_FABS,
M68K_INS_FSABS,
M68K_INS_FDABS,
M68K_INS_FACOS,
M68K_INS_FADD,
M68K_INS_FSADD,
M68K_INS_FDADD,
M68K_INS_FASIN,
M68K_INS_FATAN,
M68K_INS_FATANH,
M68K_INS_FBF,
M68K_INS_FBEQ,
M68K_INS_FBOGT,
M68K_INS_FBOGE,
M68K_INS_FBOLT,
M68K_INS_FBOLE,
M68K_INS_FBOGL,
M68K_INS_FBOR,
M68K_INS_FBUN,
M68K_INS_FBUEQ,
M68K_INS_FBUGT,
M68K_INS_FBUGE,
M68K_INS_FBULT,
M68K_INS_FBULE,
M68K_INS_FBNE,
M68K_INS_FBT,
M68K_INS_FBSF,
M68K_INS_FBSEQ,
M68K_INS_FBGT,
M68K_INS_FBGE,
M68K_INS_FBLT,
M68K_INS_FBLE,
M68K_INS_FBGL,
M68K_INS_FBGLE,
M68K_INS_FBNGLE,
M68K_INS_FBNGL,
M68K_INS_FBNLE,
M68K_INS_FBNLT,
M68K_INS_FBNGE,
M68K_INS_FBNGT,
M68K_INS_FBSNE,
M68K_INS_FBST,
M68K_INS_FCMP,
M68K_INS_FCOS,
M68K_INS_FCOSH,
M68K_INS_FDBF,
M68K_INS_FDBEQ,
M68K_INS_FDBOGT,
M68K_INS_FDBOGE,
M68K_INS_FDBOLT,
M68K_INS_FDBOLE,
M68K_INS_FDBOGL,
M68K_INS_FDBOR,
M68K_INS_FDBUN,
M68K_INS_FDBUEQ,
M68K_INS_FDBUGT,
M68K_INS_FDBUGE,
M68K_INS_FDBULT,
M68K_INS_FDBULE,
M68K_INS_FDBNE,
M68K_INS_FDBT,
M68K_INS_FDBSF,
M68K_INS_FDBSEQ,
M68K_INS_FDBGT,
M68K_INS_FDBGE,
M68K_INS_FDBLT,
M68K_INS_FDBLE,
M68K_INS_FDBGL,
M68K_INS_FDBGLE,
M68K_INS_FDBNGLE,
M68K_INS_FDBNGL,
M68K_INS_FDBNLE,
M68K_INS_FDBNLT,
M68K_INS_FDBNGE,
M68K_INS_FDBNGT,
M68K_INS_FDBSNE,
M68K_INS_FDBST,
M68K_INS_FDIV,
M68K_INS_FSDIV,
M68K_INS_FDDIV,
M68K_INS_FETOX,
M68K_INS_FETOXM1,
M68K_INS_FGETEXP,
M68K_INS_FGETMAN,
M68K_INS_FINT,
M68K_INS_FINTRZ,
M68K_INS_FLOG10,
M68K_INS_FLOG2,
M68K_INS_FLOGN,
M68K_INS_FLOGNP1,
M68K_INS_FMOD,
M68K_INS_FMOVE,
M68K_INS_FSMOVE,
M68K_INS_FDMOVE,
M68K_INS_FMOVECR,
M68K_INS_FMOVEM,
M68K_INS_FMUL,
M68K_INS_FSMUL,
M68K_INS_FDMUL,
M68K_INS_FNEG,
M68K_INS_FSNEG,
M68K_INS_FDNEG,
M68K_INS_FNOP,
M68K_INS_FREM,
M68K_INS_FRESTORE,
M68K_INS_FSAVE,
M68K_INS_FSCALE,
M68K_INS_FSGLDIV,
M68K_INS_FSGLMUL,
M68K_INS_FSIN,
M68K_INS_FSINCOS,
M68K_INS_FSINH,
M68K_INS_FSQRT,
M68K_INS_FSSQRT,
M68K_INS_FDSQRT,
M68K_INS_FSF,
M68K_INS_FSBEQ,
M68K_INS_FSOGT,
M68K_INS_FSOGE,
M68K_INS_FSOLT,
M68K_INS_FSOLE,
M68K_INS_FSOGL,
M68K_INS_FSOR,
M68K_INS_FSUN,
M68K_INS_FSUEQ,
M68K_INS_FSUGT,
M68K_INS_FSUGE,
M68K_INS_FSULT,
M68K_INS_FSULE,
M68K_INS_FSNE,
M68K_INS_FST,
M68K_INS_FSSF,
M68K_INS_FSSEQ,
M68K_INS_FSGT,
M68K_INS_FSGE,
M68K_INS_FSLT,
M68K_INS_FSLE,
M68K_INS_FSGL,
M68K_INS_FSGLE,
M68K_INS_FSNGLE,
M68K_INS_FSNGL,
M68K_INS_FSNLE,
M68K_INS_FSNLT,
M68K_INS_FSNGE,
M68K_INS_FSNGT,
M68K_INS_FSSNE,
M68K_INS_FSST,
M68K_INS_FSUB,
M68K_INS_FSSUB,
M68K_INS_FDSUB,
M68K_INS_FTAN,
M68K_INS_FTANH,
M68K_INS_FTENTOX,
M68K_INS_FTRAPF,
M68K_INS_FTRAPEQ,
M68K_INS_FTRAPOGT,
M68K_INS_FTRAPOGE,
M68K_INS_FTRAPOLT,
M68K_INS_FTRAPOLE,
M68K_INS_FTRAPOGL,
M68K_INS_FTRAPOR,
M68K_INS_FTRAPUN,
M68K_INS_FTRAPUEQ,
M68K_INS_FTRAPUGT,
M68K_INS_FTRAPUGE,
M68K_INS_FTRAPULT,
M68K_INS_FTRAPULE,
M68K_INS_FTRAPNE,
M68K_INS_FTRAPT,
M68K_INS_FTRAPSF,
M68K_INS_FTRAPSEQ,
M68K_INS_FTRAPGT,
M68K_INS_FTRAPGE,
M68K_INS_FTRAPLT,
M68K_INS_FTRAPLE,
M68K_INS_FTRAPGL,
M68K_INS_FTRAPGLE,
M68K_INS_FTRAPNGLE,
M68K_INS_FTRAPNGL,
M68K_INS_FTRAPNLE,
M68K_INS_FTRAPNLT,
M68K_INS_FTRAPNGE,
M68K_INS_FTRAPNGT,
M68K_INS_FTRAPSNE,
M68K_INS_FTRAPST,
M68K_INS_FTST,
M68K_INS_FTWOTOX,
M68K_INS_HALT,
M68K_INS_ILLEGAL,
M68K_INS_JMP,
M68K_INS_JSR,
M68K_INS_LEA,
M68K_INS_LINK,
M68K_INS_LPSTOP,
M68K_INS_LSL,
M68K_INS_LSR,
M68K_INS_MOVE,
M68K_INS_MOVEA,
M68K_INS_MOVEC,
M68K_INS_MOVEM,
M68K_INS_MOVEP,
M68K_INS_MOVEQ,
M68K_INS_MOVES,
M68K_INS_MOVE16,
M68K_INS_MULS,
M68K_INS_MULU,
M68K_INS_NBCD,
M68K_INS_NEG,
M68K_INS_NEGX,
M68K_INS_NOP,
M68K_INS_NOT,
M68K_INS_OR,
M68K_INS_ORI,
M68K_INS_PACK,
M68K_INS_PEA,
M68K_INS_PFLUSH,
M68K_INS_PFLUSHA,
M68K_INS_PFLUSHAN,
M68K_INS_PFLUSHN,
M68K_INS_PLOADR,
M68K_INS_PLOADW,
M68K_INS_PLPAR,
M68K_INS_PLPAW,
M68K_INS_PMOVE,
M68K_INS_PMOVEFD,
M68K_INS_PTESTR,
M68K_INS_PTESTW,
M68K_INS_PULSE,
M68K_INS_REMS,
M68K_INS_REMU,
M68K_INS_RESET,
M68K_INS_ROL,
M68K_INS_ROR,
M68K_INS_ROXL,
M68K_INS_ROXR,
M68K_INS_RTD,
M68K_INS_RTE,
M68K_INS_RTM,
M68K_INS_RTR,
M68K_INS_RTS,
M68K_INS_SBCD,
M68K_INS_ST,
M68K_INS_SF,
M68K_INS_SHI,
M68K_INS_SLS,
M68K_INS_SCC,
M68K_INS_SHS,
M68K_INS_SCS,
M68K_INS_SLO,
M68K_INS_SNE,
M68K_INS_SEQ,
M68K_INS_SVC,
M68K_INS_SVS,
M68K_INS_SPL,
M68K_INS_SMI,
M68K_INS_SGE,
M68K_INS_SLT,
M68K_INS_SGT,
M68K_INS_SLE,
M68K_INS_STOP,
M68K_INS_SUB,
M68K_INS_SUBA,
M68K_INS_SUBI,
M68K_INS_SUBQ,
M68K_INS_SUBX,
M68K_INS_SWAP,
M68K_INS_TAS,
M68K_INS_TRAP,
M68K_INS_TRAPV,
M68K_INS_TRAPT,
M68K_INS_TRAPF,
M68K_INS_TRAPHI,
M68K_INS_TRAPLS,
M68K_INS_TRAPCC,
M68K_INS_TRAPHS,
M68K_INS_TRAPCS,
M68K_INS_TRAPLO,
M68K_INS_TRAPNE,
M68K_INS_TRAPEQ,
M68K_INS_TRAPVC,
M68K_INS_TRAPVS,
M68K_INS_TRAPPL,
M68K_INS_TRAPMI,
M68K_INS_TRAPGE,
M68K_INS_TRAPLT,
M68K_INS_TRAPGT,
M68K_INS_TRAPLE,
M68K_INS_TST,
M68K_INS_UNLK,
M68K_INS_UNPK,
M68K_INS_ENDING, // <-- mark the end of the list of instructions
} m68k_insn;
/// Group of M68K instructions
typedef enum m68k_group_type {
M68K_GRP_INVALID = 0, ///< CS_GRUP_INVALID
M68K_GRP_JUMP, ///< = CS_GRP_JUMP
M68K_GRP_RET = 3, ///< = CS_GRP_RET
M68K_GRP_IRET = 5, ///< = CS_GRP_IRET
M68K_GRP_BRANCH_RELATIVE = 7, ///< = CS_GRP_BRANCH_RELATIVE
M68K_GRP_ENDING,// <-- mark the end of the list of groups
} m68k_group_type;
#ifdef __cplusplus
}
#endif
#endif
external/capstone/include/capstone/mips.h
Vendored
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external/capstone/include/capstone/mos65xx.h
Vendored
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#ifndef CAPSTONE_MOS65XX_H
#define CAPSTONE_MOS65XX_H
/* Capstone Disassembly Engine */
/* By Sebastian Macke <sebastian@macke.de, 2018 */
#ifdef __cplusplus
extern "C" {
#endif
#include "platform.h"
#include "cs_operand.h"
/// MOS65XX registers and special registers
typedef enum mos65xx_reg {
MOS65XX_REG_INVALID = 0,
MOS65XX_REG_ACC, ///< accumulator
MOS65XX_REG_X, ///< X index register
MOS65XX_REG_Y, ///< Y index register
MOS65XX_REG_P, ///< status register
MOS65XX_REG_SP, ///< stack pointer register
MOS65XX_REG_DP, ///< direct page register
MOS65XX_REG_B, ///< data bank register
MOS65XX_REG_K, ///< program bank register
MOS65XX_REG_ENDING, // <-- mark the end of the list of registers
} mos65xx_reg;
/// MOS65XX Addressing Modes
typedef enum mos65xx_address_mode {
MOS65XX_AM_NONE = 0, ///< No address mode.
MOS65XX_AM_IMP, ///< implied addressing (no addressing mode)
MOS65XX_AM_ACC, ///< accumulator addressing
MOS65XX_AM_IMM, ///< 8/16 Bit immediate value
MOS65XX_AM_REL, ///< relative addressing used by branches
MOS65XX_AM_INT, ///< interrupt addressing
MOS65XX_AM_BLOCK, ///< memory block addressing
MOS65XX_AM_ZP, ///< zeropage addressing
MOS65XX_AM_ZP_X, ///< indexed zeropage addressing by the X index register
MOS65XX_AM_ZP_Y, ///< indexed zeropage addressing by the Y index register
MOS65XX_AM_ZP_REL, ///< zero page address, branch relative address
MOS65XX_AM_ZP_IND, ///< indirect zeropage addressing
MOS65XX_AM_ZP_X_IND, ///< indexed zeropage indirect addressing by the X index register
MOS65XX_AM_ZP_IND_Y, ///< indirect zeropage indexed addressing by the Y index register
MOS65XX_AM_ZP_IND_LONG, ///< zeropage indirect long addressing
MOS65XX_AM_ZP_IND_LONG_Y, ///< zeropage indirect long addressing indexed by Y register
MOS65XX_AM_ABS, ///< absolute addressing
MOS65XX_AM_ABS_X, ///< indexed absolute addressing by the X index register
MOS65XX_AM_ABS_Y, ///< indexed absolute addressing by the Y index register
MOS65XX_AM_ABS_IND, ///< absolute indirect addressing
MOS65XX_AM_ABS_X_IND, ///< indexed absolute indirect addressing by the X index register
MOS65XX_AM_ABS_IND_LONG, ///< absolute indirect long addressing
MOS65XX_AM_ABS_LONG, ///< absolute long address mode
MOS65XX_AM_ABS_LONG_X, ///< absolute long address mode, indexed by X register
MOS65XX_AM_SR, ///< stack relative addressing
MOS65XX_AM_SR_IND_Y, ///< indirect stack relative addressing indexed by the Y index register
} mos65xx_address_mode;
/// MOS65XX instruction
typedef enum mos65xx_insn {
MOS65XX_INS_INVALID = 0,
MOS65XX_INS_ADC,
MOS65XX_INS_AND,
MOS65XX_INS_ASL,
MOS65XX_INS_BBR,
MOS65XX_INS_BBS,
MOS65XX_INS_BCC,
MOS65XX_INS_BCS,
MOS65XX_INS_BEQ,
MOS65XX_INS_BIT,
MOS65XX_INS_BMI,
MOS65XX_INS_BNE,
MOS65XX_INS_BPL,
MOS65XX_INS_BRA,
MOS65XX_INS_BRK,
MOS65XX_INS_BRL,
MOS65XX_INS_BVC,
MOS65XX_INS_BVS,
MOS65XX_INS_CLC,
MOS65XX_INS_CLD,
MOS65XX_INS_CLI,
MOS65XX_INS_CLV,
MOS65XX_INS_CMP,
MOS65XX_INS_COP,
MOS65XX_INS_CPX,
MOS65XX_INS_CPY,
MOS65XX_INS_DEC,
MOS65XX_INS_DEX,
MOS65XX_INS_DEY,
MOS65XX_INS_EOR,
MOS65XX_INS_INC,
MOS65XX_INS_INX,
MOS65XX_INS_INY,
MOS65XX_INS_JML,
MOS65XX_INS_JMP,
MOS65XX_INS_JSL,
MOS65XX_INS_JSR,
MOS65XX_INS_LDA,
MOS65XX_INS_LDX,
MOS65XX_INS_LDY,
MOS65XX_INS_LSR,
MOS65XX_INS_MVN,
MOS65XX_INS_MVP,
MOS65XX_INS_NOP,
MOS65XX_INS_ORA,
MOS65XX_INS_PEA,
MOS65XX_INS_PEI,
MOS65XX_INS_PER,
MOS65XX_INS_PHA,
MOS65XX_INS_PHB,
MOS65XX_INS_PHD,
MOS65XX_INS_PHK,
MOS65XX_INS_PHP,
MOS65XX_INS_PHX,
MOS65XX_INS_PHY,
MOS65XX_INS_PLA,
MOS65XX_INS_PLB,
MOS65XX_INS_PLD,
MOS65XX_INS_PLP,
MOS65XX_INS_PLX,
MOS65XX_INS_PLY,
MOS65XX_INS_REP,
MOS65XX_INS_RMB,
MOS65XX_INS_ROL,
MOS65XX_INS_ROR,
MOS65XX_INS_RTI,
MOS65XX_INS_RTL,
MOS65XX_INS_RTS,
MOS65XX_INS_SBC,
MOS65XX_INS_SEC,
MOS65XX_INS_SED,
MOS65XX_INS_SEI,
MOS65XX_INS_SEP,
MOS65XX_INS_SMB,
MOS65XX_INS_STA,
MOS65XX_INS_STP,
MOS65XX_INS_STX,
MOS65XX_INS_STY,
MOS65XX_INS_STZ,
MOS65XX_INS_TAX,
MOS65XX_INS_TAY,
MOS65XX_INS_TCD,
MOS65XX_INS_TCS,
MOS65XX_INS_TDC,
MOS65XX_INS_TRB,
MOS65XX_INS_TSB,
MOS65XX_INS_TSC,
MOS65XX_INS_TSX,
MOS65XX_INS_TXA,
MOS65XX_INS_TXS,
MOS65XX_INS_TXY,
MOS65XX_INS_TYA,
MOS65XX_INS_TYX,
MOS65XX_INS_WAI,
MOS65XX_INS_WDM,
MOS65XX_INS_XBA,
MOS65XX_INS_XCE,
MOS65XX_INS_ENDING, // <-- mark the end of the list of instructions
} mos65xx_insn;
/// Group of MOS65XX instructions
typedef enum mos65xx_group_type {
MOS65XX_GRP_INVALID = 0, ///< CS_GRP_INVALID
MOS65XX_GRP_JUMP, ///< = CS_GRP_JUMP
MOS65XX_GRP_CALL, ///< = CS_GRP_RET
MOS65XX_GRP_RET, ///< = CS_GRP_RET
MOS65XX_GRP_INT, ///< = CS_GRP_INT
MOS65XX_GRP_IRET = 5, ///< = CS_GRP_IRET
MOS65XX_GRP_BRANCH_RELATIVE = 6, ///< = CS_GRP_BRANCH_RELATIVE
MOS65XX_GRP_ENDING,// <-- mark the end of the list of groups
} mos65xx_group_type;
/// Operand type for instruction's operands
typedef enum mos65xx_op_type {
MOS65XX_OP_INVALID = CS_OP_INVALID, ///< = CS_OP_INVALID (Uninitialized).
MOS65XX_OP_REG = CS_OP_REG, ///< = CS_OP_REG (Register operand).
MOS65XX_OP_IMM = CS_OP_IMM, ///< = CS_OP_IMM (Immediate operand).
MOS65XX_OP_MEM = CS_OP_MEM, ///< = CS_OP_MEM (Memory operand).
} mos65xx_op_type;
/// Instruction operand
typedef struct cs_mos65xx_op {
mos65xx_op_type type; ///< operand type
union {
mos65xx_reg reg; ///< register value for REG operand
uint16_t imm; ///< immediate value for IMM operand
uint32_t mem; ///< address for MEM operand
};
} cs_mos65xx_op;
/// The MOS65XX address mode and its operands
typedef struct cs_mos65xx {
mos65xx_address_mode am;
bool modifies_flags;
/// Number of operands of this instruction,
/// or 0 when instruction has no operand.
uint8_t op_count;
cs_mos65xx_op operands[3]; ///< operands for this instruction.
} cs_mos65xx;
#ifdef __cplusplus
}
#endif
#endif //CAPSTONE_MOS65XX_H
external/capstone/include/capstone/platform.h
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@@ -0,0 +1,122 @@
/* Capstone Disassembly Engine */
/* By Axel Souchet & Nguyen Anh Quynh, 2014 */
#ifndef CAPSTONE_PLATFORM_H
#define CAPSTONE_PLATFORM_H
// handle C99 issue (for pre-2013 VisualStudio)
#if !defined(__CYGWIN__) && !defined(__MINGW32__) && !defined(__MINGW64__) && (defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64))
// MSVC
// stdbool.h
#if (_MSC_VER < 1800) || defined(_KERNEL_MODE)
// this system does not have stdbool.h
#ifndef __cplusplus
typedef unsigned char bool;
#define false 0
#define true 1
#endif // __cplusplus
#else
// VisualStudio 2013+ -> C99 is supported
#include <stdbool.h>
#endif // (_MSC_VER < 1800) || defined(_KERNEL_MODE)
#else
// not MSVC -> C99 is supported
#include <stdbool.h>
#endif // !defined(__CYGWIN__) && !defined(__MINGW32__) && !defined(__MINGW64__) && (defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64))
// handle inttypes.h / stdint.h compatibility
#if defined(_WIN32_WCE) && (_WIN32_WCE < 0x800)
#include "windowsce/stdint.h"
#endif // defined(_WIN32_WCE) && (_WIN32_WCE < 0x800)
#if defined(CAPSTONE_HAS_OSXKERNEL) || (defined(_MSC_VER) && (_MSC_VER <= 1700 || defined(_KERNEL_MODE)))
// this system does not have inttypes.h
#if defined(_MSC_VER) && (_MSC_VER <= 1600 || defined(_KERNEL_MODE))
// this system does not have stdint.h
typedef signed char int8_t;
typedef signed short int16_t;
typedef signed int int32_t;
typedef unsigned char uint8_t;
typedef unsigned short uint16_t;
typedef unsigned int uint32_t;
typedef signed long long int64_t;
typedef unsigned long long uint64_t;
#endif // defined(_MSC_VER) && (_MSC_VER <= 1600 || defined(_KERNEL_MODE))
#if defined(_MSC_VER) && (_MSC_VER < 1600 || defined(_KERNEL_MODE))
#define INT8_MIN (-127i8 - 1)
#define INT16_MIN (-32767i16 - 1)
#define INT32_MIN (-2147483647i32 - 1)
#define INT64_MIN (-9223372036854775807i64 - 1)
#define INT8_MAX 127i8
#define INT16_MAX 32767i16
#define INT32_MAX 2147483647i32
#define INT64_MAX 9223372036854775807i64
#define UINT8_MAX 0xffui8
#define UINT16_MAX 0xffffui16
#define UINT32_MAX 0xffffffffui32
#define UINT64_MAX 0xffffffffffffffffui64
#endif // defined(_MSC_VER) && (_MSC_VER < 1600 || defined(_KERNEL_MODE))
#ifdef CAPSTONE_HAS_OSXKERNEL
// this system has stdint.h
#include <stdint.h>
#endif
#define __PRI_8_LENGTH_MODIFIER__ "hh"
#define __PRI_64_LENGTH_MODIFIER__ "ll"
#define PRId8 __PRI_8_LENGTH_MODIFIER__ "d"
#define PRIi8 __PRI_8_LENGTH_MODIFIER__ "i"
#define PRIo8 __PRI_8_LENGTH_MODIFIER__ "o"
#define PRIu8 __PRI_8_LENGTH_MODIFIER__ "u"
#define PRIx8 __PRI_8_LENGTH_MODIFIER__ "x"
#define PRIX8 __PRI_8_LENGTH_MODIFIER__ "X"
#define PRId16 "hd"
#define PRIi16 "hi"
#define PRIo16 "ho"
#define PRIu16 "hu"
#define PRIx16 "hx"
#define PRIX16 "hX"
#if defined(_MSC_VER) && _MSC_VER <= 1700
#define PRId32 "ld"
#define PRIi32 "li"
#define PRIo32 "lo"
#define PRIu32 "lu"
#define PRIx32 "lx"
#define PRIX32 "lX"
#else // OSX
#define PRId32 "d"
#define PRIi32 "i"
#define PRIo32 "o"
#define PRIu32 "u"
#define PRIx32 "x"
#define PRIX32 "X"
#endif // defined(_MSC_VER) && _MSC_VER <= 1700
#if defined(_MSC_VER) && _MSC_VER <= 1700
// redefine functions from inttypes.h used in cstool
#define strtoull _strtoui64
#endif
#define PRId64 __PRI_64_LENGTH_MODIFIER__ "d"
#define PRIi64 __PRI_64_LENGTH_MODIFIER__ "i"
#define PRIo64 __PRI_64_LENGTH_MODIFIER__ "o"
#define PRIu64 __PRI_64_LENGTH_MODIFIER__ "u"
#define PRIx64 __PRI_64_LENGTH_MODIFIER__ "x"
#define PRIX64 __PRI_64_LENGTH_MODIFIER__ "X"
#else
// this system has inttypes.h by default
#include <inttypes.h>
#endif // defined(CAPSTONE_HAS_OSXKERNEL) || (defined(_MSC_VER) && (_MSC_VER <= 1700 || defined(_KERNEL_MODE)))
#endif
external/capstone/include/capstone/ppc.h
Vendored
+3602
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File diff suppressed because it is too large Load Diff
external/capstone/include/capstone/riscv.h
Vendored
+520
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#ifndef CAPSTONE_RISCV_H
#define CAPSTONE_RISCV_H
/* Capstone Disassembly Engine */
/* RISC-V Backend By Rodrigo Cortes Porto <porto703@gmail.com> &
Shawn Chang <citypw@gmail.com>, HardenedLinux@2018 */
#ifdef __cplusplus
extern "C" {
#endif
#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
#include <stdint.h>
#endif
#include "platform.h"
#include "cs_operand.h"
// GCC MIPS toolchain has a default macro called "mips" which breaks
// compilation
//#undef riscv
#ifdef _MSC_VER
#pragma warning(disable:4201)
#endif
//> Operand type for instruction's operands
typedef enum riscv_op_type {
RISCV_OP_INVALID = CS_OP_INVALID, // = CS_OP_INVALID (Uninitialized).
RISCV_OP_REG = CS_OP_REG, // = CS_OP_REG (Register operand).
RISCV_OP_IMM = CS_OP_IMM, // = CS_OP_IMM (Immediate operand).
RISCV_OP_MEM = CS_OP_MEM, // = CS_OP_MEM (Memory operand).
} riscv_op_type;
// Instruction's operand referring to memory
// This is associated with RISCV_OP_MEM operand type above
typedef struct riscv_op_mem {
unsigned int base; // base register
int64_t disp; // displacement/offset value
} riscv_op_mem;
// Instruction operand
typedef struct cs_riscv_op {
riscv_op_type type; // operand type
union {
unsigned int reg; // register value for REG operand
int64_t imm; // immediate value for IMM operand
riscv_op_mem mem; // base/disp value for MEM operand
};
cs_ac_type access; ///< How is this operand accessed? (READ, WRITE or READ|WRITE)
} cs_riscv_op;
#define NUM_RISCV_OPS 8
// Instruction structure
typedef struct cs_riscv {
// Does this instruction need effective address or not.
bool need_effective_addr;
// Number of operands of this instruction,
// or 0 when instruction has no operand.
uint8_t op_count;
cs_riscv_op operands[NUM_RISCV_OPS]; // operands for this instruction.
} cs_riscv;
//> RISCV registers
typedef enum riscv_reg {
RISCV_REG_INVALID = 0,
//> General purpose registers
RISCV_REG_X0, // "zero"
RISCV_REG_ZERO = RISCV_REG_X0, // "zero"
RISCV_REG_X1, // "ra"
RISCV_REG_RA = RISCV_REG_X1, // "ra"
RISCV_REG_X2, // "sp"
RISCV_REG_SP = RISCV_REG_X2, // "sp"
RISCV_REG_X3, // "gp"
RISCV_REG_GP = RISCV_REG_X3, // "gp"
RISCV_REG_X4, // "tp"
RISCV_REG_TP = RISCV_REG_X4, // "tp"
RISCV_REG_X5, // "t0"
RISCV_REG_T0 = RISCV_REG_X5, // "t0"
RISCV_REG_X6, // "t1"
RISCV_REG_T1 = RISCV_REG_X6, // "t1"
RISCV_REG_X7, // "t2"
RISCV_REG_T2 = RISCV_REG_X7, // "t2"
RISCV_REG_X8, // "s0/fp"
RISCV_REG_S0 = RISCV_REG_X8, // "s0"
RISCV_REG_FP = RISCV_REG_X8, // "fp"
RISCV_REG_X9, // "s1"
RISCV_REG_S1 = RISCV_REG_X9, // "s1"
RISCV_REG_X10, // "a0"
RISCV_REG_A0 = RISCV_REG_X10, // "a0"
RISCV_REG_X11, // "a1"
RISCV_REG_A1 = RISCV_REG_X11, // "a1"
RISCV_REG_X12, // "a2"
RISCV_REG_A2 = RISCV_REG_X12, // "a2"
RISCV_REG_X13, // "a3"
RISCV_REG_A3 = RISCV_REG_X13, // "a3"
RISCV_REG_X14, // "a4"
RISCV_REG_A4 = RISCV_REG_X14, // "a4"
RISCV_REG_X15, // "a5"
RISCV_REG_A5 = RISCV_REG_X15, // "a5"
RISCV_REG_X16, // "a6"
RISCV_REG_A6 = RISCV_REG_X16, // "a6"
RISCV_REG_X17, // "a7"
RISCV_REG_A7 = RISCV_REG_X17, // "a7"
RISCV_REG_X18, // "s2"
RISCV_REG_S2 = RISCV_REG_X18, // "s2"
RISCV_REG_X19, // "s3"
RISCV_REG_S3 = RISCV_REG_X19, // "s3"
RISCV_REG_X20, // "s4"
RISCV_REG_S4 = RISCV_REG_X20, // "s4"
RISCV_REG_X21, // "s5"
RISCV_REG_S5 = RISCV_REG_X21, // "s5"
RISCV_REG_X22, // "s6"
RISCV_REG_S6 = RISCV_REG_X22, // "s6"
RISCV_REG_X23, // "s7"
RISCV_REG_S7 = RISCV_REG_X23, // "s7"
RISCV_REG_X24, // "s8"
RISCV_REG_S8 = RISCV_REG_X24, // "s8"
RISCV_REG_X25, // "s9"
RISCV_REG_S9 = RISCV_REG_X25, // "s9"
RISCV_REG_X26, // "s10"
RISCV_REG_S10 = RISCV_REG_X26, // "s10"
RISCV_REG_X27, // "s11"
RISCV_REG_S11 = RISCV_REG_X27, // "s11"
RISCV_REG_X28, // "t3"
RISCV_REG_T3 = RISCV_REG_X28, // "t3"
RISCV_REG_X29, // "t4"
RISCV_REG_T4 = RISCV_REG_X29, // "t4"
RISCV_REG_X30, // "t5"
RISCV_REG_T5 = RISCV_REG_X30, // "t5"
RISCV_REG_X31, // "t6"
RISCV_REG_T6 = RISCV_REG_X31, // "t6"
//> Floating-point registers
RISCV_REG_F0_32, // "ft0"
RISCV_REG_F0_64, // "ft0"
RISCV_REG_F1_32, // "ft1"
RISCV_REG_F1_64, // "ft1"
RISCV_REG_F2_32, // "ft2"
RISCV_REG_F2_64, // "ft2"
RISCV_REG_F3_32, // "ft3"
RISCV_REG_F3_64, // "ft3"
RISCV_REG_F4_32, // "ft4"
RISCV_REG_F4_64, // "ft4"
RISCV_REG_F5_32, // "ft5"
RISCV_REG_F5_64, // "ft5"
RISCV_REG_F6_32, // "ft6"
RISCV_REG_F6_64, // "ft6"
RISCV_REG_F7_32, // "ft7"
RISCV_REG_F7_64, // "ft7"
RISCV_REG_F8_32, // "fs0"
RISCV_REG_F8_64, // "fs0"
RISCV_REG_F9_32, // "fs1"
RISCV_REG_F9_64, // "fs1"
RISCV_REG_F10_32, // "fa0"
RISCV_REG_F10_64, // "fa0"
RISCV_REG_F11_32, // "fa1"
RISCV_REG_F11_64, // "fa1"
RISCV_REG_F12_32, // "fa2"
RISCV_REG_F12_64, // "fa2"
RISCV_REG_F13_32, // "fa3"
RISCV_REG_F13_64, // "fa3"
RISCV_REG_F14_32, // "fa4"
RISCV_REG_F14_64, // "fa4"
RISCV_REG_F15_32, // "fa5"
RISCV_REG_F15_64, // "fa5"
RISCV_REG_F16_32, // "fa6"
RISCV_REG_F16_64, // "fa6"
RISCV_REG_F17_32, // "fa7"
RISCV_REG_F17_64, // "fa7"
RISCV_REG_F18_32, // "fs2"
RISCV_REG_F18_64, // "fs2"
RISCV_REG_F19_32, // "fs3"
RISCV_REG_F19_64, // "fs3"
RISCV_REG_F20_32, // "fs4"
RISCV_REG_F20_64, // "fs4"
RISCV_REG_F21_32, // "fs5"
RISCV_REG_F21_64, // "fs5"
RISCV_REG_F22_32, // "fs6"
RISCV_REG_F22_64, // "fs6"
RISCV_REG_F23_32, // "fs7"
RISCV_REG_F23_64, // "fs7"
RISCV_REG_F24_32, // "fs8"
RISCV_REG_F24_64, // "fs8"
RISCV_REG_F25_32, // "fs9"
RISCV_REG_F25_64, // "fs9"
RISCV_REG_F26_32, // "fs10"
RISCV_REG_F26_64, // "fs10"
RISCV_REG_F27_32, // "fs11"
RISCV_REG_F27_64, // "fs11"
RISCV_REG_F28_32, // "ft8"
RISCV_REG_F28_64, // "ft8"
RISCV_REG_F29_32, // "ft9"
RISCV_REG_F29_64, // "ft9"
RISCV_REG_F30_32, // "ft10"
RISCV_REG_F30_64, // "ft10"
RISCV_REG_F31_32, // "ft11"
RISCV_REG_F31_64, // "ft11"
RISCV_REG_ENDING, // <-- mark the end of the list or registers
} riscv_reg;
//> RISCV instruction
typedef enum riscv_insn {
RISCV_INS_INVALID = 0,
RISCV_INS_ADD,
RISCV_INS_ADDI,
RISCV_INS_ADDIW,
RISCV_INS_ADDW,
RISCV_INS_AMOADD_D,
RISCV_INS_AMOADD_D_AQ,
RISCV_INS_AMOADD_D_AQ_RL,
RISCV_INS_AMOADD_D_RL,
RISCV_INS_AMOADD_W,
RISCV_INS_AMOADD_W_AQ,
RISCV_INS_AMOADD_W_AQ_RL,
RISCV_INS_AMOADD_W_RL,
RISCV_INS_AMOAND_D,
RISCV_INS_AMOAND_D_AQ,
RISCV_INS_AMOAND_D_AQ_RL,
RISCV_INS_AMOAND_D_RL,
RISCV_INS_AMOAND_W,
RISCV_INS_AMOAND_W_AQ,
RISCV_INS_AMOAND_W_AQ_RL,
RISCV_INS_AMOAND_W_RL,
RISCV_INS_AMOMAXU_D,
RISCV_INS_AMOMAXU_D_AQ,
RISCV_INS_AMOMAXU_D_AQ_RL,
RISCV_INS_AMOMAXU_D_RL,
RISCV_INS_AMOMAXU_W,
RISCV_INS_AMOMAXU_W_AQ,
RISCV_INS_AMOMAXU_W_AQ_RL,
RISCV_INS_AMOMAXU_W_RL,
RISCV_INS_AMOMAX_D,
RISCV_INS_AMOMAX_D_AQ,
RISCV_INS_AMOMAX_D_AQ_RL,
RISCV_INS_AMOMAX_D_RL,
RISCV_INS_AMOMAX_W,
RISCV_INS_AMOMAX_W_AQ,
RISCV_INS_AMOMAX_W_AQ_RL,
RISCV_INS_AMOMAX_W_RL,
RISCV_INS_AMOMINU_D,
RISCV_INS_AMOMINU_D_AQ,
RISCV_INS_AMOMINU_D_AQ_RL,
RISCV_INS_AMOMINU_D_RL,
RISCV_INS_AMOMINU_W,
RISCV_INS_AMOMINU_W_AQ,
RISCV_INS_AMOMINU_W_AQ_RL,
RISCV_INS_AMOMINU_W_RL,
RISCV_INS_AMOMIN_D,
RISCV_INS_AMOMIN_D_AQ,
RISCV_INS_AMOMIN_D_AQ_RL,
RISCV_INS_AMOMIN_D_RL,
RISCV_INS_AMOMIN_W,
RISCV_INS_AMOMIN_W_AQ,
RISCV_INS_AMOMIN_W_AQ_RL,
RISCV_INS_AMOMIN_W_RL,
RISCV_INS_AMOOR_D,
RISCV_INS_AMOOR_D_AQ,
RISCV_INS_AMOOR_D_AQ_RL,
RISCV_INS_AMOOR_D_RL,
RISCV_INS_AMOOR_W,
RISCV_INS_AMOOR_W_AQ,
RISCV_INS_AMOOR_W_AQ_RL,
RISCV_INS_AMOOR_W_RL,
RISCV_INS_AMOSWAP_D,
RISCV_INS_AMOSWAP_D_AQ,
RISCV_INS_AMOSWAP_D_AQ_RL,
RISCV_INS_AMOSWAP_D_RL,
RISCV_INS_AMOSWAP_W,
RISCV_INS_AMOSWAP_W_AQ,
RISCV_INS_AMOSWAP_W_AQ_RL,
RISCV_INS_AMOSWAP_W_RL,
RISCV_INS_AMOXOR_D,
RISCV_INS_AMOXOR_D_AQ,
RISCV_INS_AMOXOR_D_AQ_RL,
RISCV_INS_AMOXOR_D_RL,
RISCV_INS_AMOXOR_W,
RISCV_INS_AMOXOR_W_AQ,
RISCV_INS_AMOXOR_W_AQ_RL,
RISCV_INS_AMOXOR_W_RL,
RISCV_INS_AND,
RISCV_INS_ANDI,
RISCV_INS_AUIPC,
RISCV_INS_BEQ,
RISCV_INS_BGE,
RISCV_INS_BGEU,
RISCV_INS_BLT,
RISCV_INS_BLTU,
RISCV_INS_BNE,
RISCV_INS_CSRRC,
RISCV_INS_CSRRCI,
RISCV_INS_CSRRS,
RISCV_INS_CSRRSI,
RISCV_INS_CSRRW,
RISCV_INS_CSRRWI,
RISCV_INS_C_ADD,
RISCV_INS_C_ADDI,
RISCV_INS_C_ADDI16SP,
RISCV_INS_C_ADDI4SPN,
RISCV_INS_C_ADDIW,
RISCV_INS_C_ADDW,
RISCV_INS_C_AND,
RISCV_INS_C_ANDI,
RISCV_INS_C_BEQZ,
RISCV_INS_C_BNEZ,
RISCV_INS_C_EBREAK,
RISCV_INS_C_FLD,
RISCV_INS_C_FLDSP,
RISCV_INS_C_FLW,
RISCV_INS_C_FLWSP,
RISCV_INS_C_FSD,
RISCV_INS_C_FSDSP,
RISCV_INS_C_FSW,
RISCV_INS_C_FSWSP,
RISCV_INS_C_J,
RISCV_INS_C_JAL,
RISCV_INS_C_JALR,
RISCV_INS_C_JR,
RISCV_INS_C_LD,
RISCV_INS_C_LDSP,
RISCV_INS_C_LI,
RISCV_INS_C_LUI,
RISCV_INS_C_LW,
RISCV_INS_C_LWSP,
RISCV_INS_C_MV,
RISCV_INS_C_NOP,
RISCV_INS_C_OR,
RISCV_INS_C_SD,
RISCV_INS_C_SDSP,
RISCV_INS_C_SLLI,
RISCV_INS_C_SRAI,
RISCV_INS_C_SRLI,
RISCV_INS_C_SUB,
RISCV_INS_C_SUBW,
RISCV_INS_C_SW,
RISCV_INS_C_SWSP,
RISCV_INS_C_UNIMP,
RISCV_INS_C_XOR,
RISCV_INS_DIV,
RISCV_INS_DIVU,
RISCV_INS_DIVUW,
RISCV_INS_DIVW,
RISCV_INS_EBREAK,
RISCV_INS_ECALL,
RISCV_INS_FADD_D,
RISCV_INS_FADD_S,
RISCV_INS_FCLASS_D,
RISCV_INS_FCLASS_S,
RISCV_INS_FCVT_D_L,
RISCV_INS_FCVT_D_LU,
RISCV_INS_FCVT_D_S,
RISCV_INS_FCVT_D_W,
RISCV_INS_FCVT_D_WU,
RISCV_INS_FCVT_LU_D,
RISCV_INS_FCVT_LU_S,
RISCV_INS_FCVT_L_D,
RISCV_INS_FCVT_L_S,
RISCV_INS_FCVT_S_D,
RISCV_INS_FCVT_S_L,
RISCV_INS_FCVT_S_LU,
RISCV_INS_FCVT_S_W,
RISCV_INS_FCVT_S_WU,
RISCV_INS_FCVT_WU_D,
RISCV_INS_FCVT_WU_S,
RISCV_INS_FCVT_W_D,
RISCV_INS_FCVT_W_S,
RISCV_INS_FDIV_D,
RISCV_INS_FDIV_S,
RISCV_INS_FENCE,
RISCV_INS_FENCE_I,
RISCV_INS_FENCE_TSO,
RISCV_INS_FEQ_D,
RISCV_INS_FEQ_S,
RISCV_INS_FLD,
RISCV_INS_FLE_D,
RISCV_INS_FLE_S,
RISCV_INS_FLT_D,
RISCV_INS_FLT_S,
RISCV_INS_FLW,
RISCV_INS_FMADD_D,
RISCV_INS_FMADD_S,
RISCV_INS_FMAX_D,
RISCV_INS_FMAX_S,
RISCV_INS_FMIN_D,
RISCV_INS_FMIN_S,
RISCV_INS_FMSUB_D,
RISCV_INS_FMSUB_S,
RISCV_INS_FMUL_D,
RISCV_INS_FMUL_S,
RISCV_INS_FMV_D_X,
RISCV_INS_FMV_W_X,
RISCV_INS_FMV_X_D,
RISCV_INS_FMV_X_W,
RISCV_INS_FNMADD_D,
RISCV_INS_FNMADD_S,
RISCV_INS_FNMSUB_D,
RISCV_INS_FNMSUB_S,
RISCV_INS_FSD,
RISCV_INS_FSGNJN_D,
RISCV_INS_FSGNJN_S,
RISCV_INS_FSGNJX_D,
RISCV_INS_FSGNJX_S,
RISCV_INS_FSGNJ_D,
RISCV_INS_FSGNJ_S,
RISCV_INS_FSQRT_D,
RISCV_INS_FSQRT_S,
RISCV_INS_FSUB_D,
RISCV_INS_FSUB_S,
RISCV_INS_FSW,
RISCV_INS_JAL,
RISCV_INS_JALR,
RISCV_INS_LB,
RISCV_INS_LBU,
RISCV_INS_LD,
RISCV_INS_LH,
RISCV_INS_LHU,
RISCV_INS_LR_D,
RISCV_INS_LR_D_AQ,
RISCV_INS_LR_D_AQ_RL,
RISCV_INS_LR_D_RL,
RISCV_INS_LR_W,
RISCV_INS_LR_W_AQ,
RISCV_INS_LR_W_AQ_RL,
RISCV_INS_LR_W_RL,
RISCV_INS_LUI,
RISCV_INS_LW,
RISCV_INS_LWU,
RISCV_INS_MRET,
RISCV_INS_MUL,
RISCV_INS_MULH,
RISCV_INS_MULHSU,
RISCV_INS_MULHU,
RISCV_INS_MULW,
RISCV_INS_OR,
RISCV_INS_ORI,
RISCV_INS_REM,
RISCV_INS_REMU,
RISCV_INS_REMUW,
RISCV_INS_REMW,
RISCV_INS_SB,
RISCV_INS_SC_D,
RISCV_INS_SC_D_AQ,
RISCV_INS_SC_D_AQ_RL,
RISCV_INS_SC_D_RL,
RISCV_INS_SC_W,
RISCV_INS_SC_W_AQ,
RISCV_INS_SC_W_AQ_RL,
RISCV_INS_SC_W_RL,
RISCV_INS_SD,
RISCV_INS_SFENCE_VMA,
RISCV_INS_SH,
RISCV_INS_SLL,
RISCV_INS_SLLI,
RISCV_INS_SLLIW,
RISCV_INS_SLLW,
RISCV_INS_SLT,
RISCV_INS_SLTI,
RISCV_INS_SLTIU,
RISCV_INS_SLTU,
RISCV_INS_SRA,
RISCV_INS_SRAI,
RISCV_INS_SRAIW,
RISCV_INS_SRAW,
RISCV_INS_SRET,
RISCV_INS_SRL,
RISCV_INS_SRLI,
RISCV_INS_SRLIW,
RISCV_INS_SRLW,
RISCV_INS_SUB,
RISCV_INS_SUBW,
RISCV_INS_SW,
RISCV_INS_UNIMP,
RISCV_INS_URET,
RISCV_INS_WFI,
RISCV_INS_XOR,
RISCV_INS_XORI,
RISCV_INS_ENDING,
} riscv_insn;
//> Group of RISCV instructions
typedef enum riscv_insn_group {
RISCV_GRP_INVALID = 0, ///< = CS_GRP_INVALID
// Generic groups
// all jump instructions (conditional+direct+indirect jumps)
RISCV_GRP_JUMP, ///< = CS_GRP_JUMP
// all call instructions
RISCV_GRP_CALL, ///< = CS_GRP_CALL
// all return instructions
RISCV_GRP_RET, ///< = CS_GRP_RET
// all interrupt instructions (int+syscall)
RISCV_GRP_INT, ///< = CS_GRP_INT
// all interrupt return instructions
RISCV_GRP_IRET, ///< = CS_GRP_IRET
// all privileged instructions
RISCV_GRP_PRIVILEGE, ///< = CS_GRP_PRIVILEGE
// all relative branching instructions
RISCV_GRP_BRANCH_RELATIVE, ///< = CS_GRP_BRANCH_RELATIVE
// Architecture-specific groups
RISCV_GRP_ISRV32 = 128,
RISCV_GRP_ISRV64,
RISCV_GRP_HASSTDEXTA,
RISCV_GRP_HASSTDEXTC,
RISCV_GRP_HASSTDEXTD,
RISCV_GRP_HASSTDEXTF,
RISCV_GRP_HASSTDEXTM,
RISCV_GRP_ENDING,
} riscv_insn_group;
#ifdef __cplusplus
}
#endif
#endif
external/capstone/include/capstone/sh.h
Vendored
+459
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@@ -0,0 +1,459 @@
#ifndef CAPSTONE_SH_H
#define CAPSTONE_SH_H
/* Capstone Disassembly Engine */
/* By Yoshinori Sato, 2022 */
#ifdef __cplusplus
extern "C" {
#endif
#include "platform.h"
#include "cs_operand.h"
#ifdef _MSC_VER
#pragma warning(disable:4201)
#endif
/// SH registers and special registers
typedef enum {
SH_REG_INVALID = 0,
SH_REG_R0,
SH_REG_R1,
SH_REG_R2,
SH_REG_R3,
SH_REG_R4,
SH_REG_R5,
SH_REG_R6,
SH_REG_R7,
SH_REG_R8,
SH_REG_R9,
SH_REG_R10,
SH_REG_R11,
SH_REG_R12,
SH_REG_R13,
SH_REG_R14,
SH_REG_R15,
SH_REG_R0_BANK,
SH_REG_R1_BANK,
SH_REG_R2_BANK,
SH_REG_R3_BANK,
SH_REG_R4_BANK,
SH_REG_R5_BANK,
SH_REG_R6_BANK,
SH_REG_R7_BANK,
SH_REG_FR0,
SH_REG_FR1,
SH_REG_FR2,
SH_REG_FR3,
SH_REG_FR4,
SH_REG_FR5,
SH_REG_FR6,
SH_REG_FR7,
SH_REG_FR8,
SH_REG_FR9,
SH_REG_FR10,
SH_REG_FR11,
SH_REG_FR12,
SH_REG_FR13,
SH_REG_FR14,
SH_REG_FR15,
SH_REG_DR0,
SH_REG_DR2,
SH_REG_DR4,
SH_REG_DR6,
SH_REG_DR8,
SH_REG_DR10,
SH_REG_DR12,
SH_REG_DR14,
SH_REG_XD0,
SH_REG_XD2,
SH_REG_XD4,
SH_REG_XD6,
SH_REG_XD8,
SH_REG_XD10,
SH_REG_XD12,
SH_REG_XD14,
SH_REG_XF0,
SH_REG_XF1,
SH_REG_XF2,
SH_REG_XF3,
SH_REG_XF4,
SH_REG_XF5,
SH_REG_XF6,
SH_REG_XF7,
SH_REG_XF8,
SH_REG_XF9,
SH_REG_XF10,
SH_REG_XF11,
SH_REG_XF12,
SH_REG_XF13,
SH_REG_XF14,
SH_REG_XF15,
SH_REG_FV0,
SH_REG_FV4,
SH_REG_FV8,
SH_REG_FV12,
SH_REG_XMATRX,
SH_REG_PC,
SH_REG_PR,
SH_REG_MACH,
SH_REG_MACL,
SH_REG_SR,
SH_REG_GBR,
SH_REG_SSR,
SH_REG_SPC,
SH_REG_SGR,
SH_REG_DBR,
SH_REG_VBR,
SH_REG_TBR,
SH_REG_RS,
SH_REG_RE,
SH_REG_MOD,
SH_REG_FPUL,
SH_REG_FPSCR,
SH_REG_DSP_X0,
SH_REG_DSP_X1,
SH_REG_DSP_Y0,
SH_REG_DSP_Y1,
SH_REG_DSP_A0,
SH_REG_DSP_A1,
SH_REG_DSP_A0G,
SH_REG_DSP_A1G,
SH_REG_DSP_M0,
SH_REG_DSP_M1,
SH_REG_DSP_DSR,
SH_REG_DSP_RSV0,
SH_REG_DSP_RSV1,
SH_REG_DSP_RSV2,
SH_REG_DSP_RSV3,
SH_REG_DSP_RSV4,
SH_REG_DSP_RSV5,
SH_REG_DSP_RSV6,
SH_REG_DSP_RSV7,
SH_REG_DSP_RSV8,
SH_REG_DSP_RSV9,
SH_REG_DSP_RSVA,
SH_REG_DSP_RSVB,
SH_REG_DSP_RSVC,
SH_REG_DSP_RSVD,
SH_REG_DSP_RSVE,
SH_REG_DSP_RSVF,
SH_REG_ENDING, // <-- mark the end of the list of registers
} sh_reg;
typedef enum {
SH_OP_INVALID = CS_OP_INVALID, ///< = CS_OP_INVALID (Uninitialized).
SH_OP_REG = CS_OP_REG, ///< = CS_OP_REG (Register operand).
SH_OP_IMM = CS_OP_IMM, ///< = CS_OP_IMM (Immediate operand).
SH_OP_MEM = CS_OP_MEM, ///< = CS_OP_MEM (Memory operand).
} sh_op_type;
typedef enum {
SH_OP_MEM_INVALID = 0, /// <= Invalid
SH_OP_MEM_REG_IND, /// <= Register indirect
SH_OP_MEM_REG_POST, /// <= Register post increment
SH_OP_MEM_REG_PRE, /// <= Register pre decrement
SH_OP_MEM_REG_DISP, /// <= displacement
SH_OP_MEM_REG_R0, /// <= R0 indexed
SH_OP_MEM_GBR_DISP, /// <= GBR based displacement
SH_OP_MEM_GBR_R0, /// <= GBR based R0 indexed
SH_OP_MEM_PCR, /// <= PC relative
SH_OP_MEM_TBR_DISP, /// <= TBR based displaysment
} sh_op_mem_type;
typedef struct sh_op_mem {
sh_op_mem_type address; /// <= memory address
sh_reg reg; /// <= base register
uint32_t disp; /// <= displacement
} sh_op_mem;
typedef enum sh_dsp_insn {
SH_INS_DSP_INVALID = 0,
SH_INS_DSP_NOP = 1,
SH_INS_DSP_MOV,
SH_INS_DSP_PSHL,
SH_INS_DSP_PSHA,
SH_INS_DSP_PMULS,
SH_INS_DSP_PCLR_PMULS,
SH_INS_DSP_PSUB_PMULS,
SH_INS_DSP_PADD_PMULS,
SH_INS_DSP_PSUBC,
SH_INS_DSP_PADDC,
SH_INS_DSP_PCMP,
SH_INS_DSP_PABS,
SH_INS_DSP_PRND,
SH_INS_DSP_PSUB,
SH_INS_DSP_PSUBr,
SH_INS_DSP_PADD,
SH_INS_DSP_PAND,
SH_INS_DSP_PXOR,
SH_INS_DSP_POR,
SH_INS_DSP_PDEC,
SH_INS_DSP_PINC,
SH_INS_DSP_PCLR,
SH_INS_DSP_PDMSB,
SH_INS_DSP_PNEG,
SH_INS_DSP_PCOPY,
SH_INS_DSP_PSTS,
SH_INS_DSP_PLDS,
SH_INS_DSP_PSWAP,
SH_INS_DSP_PWAD,
SH_INS_DSP_PWSB,
} sh_dsp_insn;
typedef enum sh_dsp_operand {
SH_OP_DSP_INVALID,
SH_OP_DSP_REG_PRE,
SH_OP_DSP_REG_IND,
SH_OP_DSP_REG_POST,
SH_OP_DSP_REG_INDEX,
SH_OP_DSP_REG,
SH_OP_DSP_IMM,
} sh_dsp_operand;
typedef enum sh_dsp_cc {
SH_DSP_CC_INVALID,
SH_DSP_CC_NONE,
SH_DSP_CC_DCT,
SH_DSP_CC_DCF,
} sh_dsp_cc;
typedef struct sh_op_dsp {
sh_dsp_insn insn;
sh_dsp_operand operand[2];
sh_reg r[6];
sh_dsp_cc cc;
uint8_t imm;
int size;
} sh_op_dsp;
/// Instruction operand
typedef struct cs_sh_op {
sh_op_type type;
union {
uint64_t imm; ///< immediate value for IMM operand
sh_reg reg; ///< register value for REG operand
sh_op_mem mem; ///< data when operand is targeting memory
sh_op_dsp dsp; ///< dsp instruction
};
} cs_sh_op;
/// SH instruction
typedef enum sh_insn {
SH_INS_INVALID,
SH_INS_ADD_r,
SH_INS_ADD,
SH_INS_ADDC,
SH_INS_ADDV,
SH_INS_AND,
SH_INS_BAND,
SH_INS_BANDNOT,
SH_INS_BCLR,
SH_INS_BF,
SH_INS_BF_S,
SH_INS_BLD,
SH_INS_BLDNOT,
SH_INS_BOR,
SH_INS_BORNOT,
SH_INS_BRA,
SH_INS_BRAF,
SH_INS_BSET,
SH_INS_BSR,
SH_INS_BSRF,
SH_INS_BST,
SH_INS_BT,
SH_INS_BT_S,
SH_INS_BXOR,
SH_INS_CLIPS,
SH_INS_CLIPU,
SH_INS_CLRDMXY,
SH_INS_CLRMAC,
SH_INS_CLRS,
SH_INS_CLRT,
SH_INS_CMP_EQ,
SH_INS_CMP_GE,
SH_INS_CMP_GT,
SH_INS_CMP_HI,
SH_INS_CMP_HS,
SH_INS_CMP_PL,
SH_INS_CMP_PZ,
SH_INS_CMP_STR,
SH_INS_DIV0S,
SH_INS_DIV0U,
SH_INS_DIV1,
SH_INS_DIVS,
SH_INS_DIVU,
SH_INS_DMULS_L,
SH_INS_DMULU_L,
SH_INS_DT,
SH_INS_EXTS_B,
SH_INS_EXTS_W,
SH_INS_EXTU_B,
SH_INS_EXTU_W,
SH_INS_FABS,
SH_INS_FADD,
SH_INS_FCMP_EQ,
SH_INS_FCMP_GT,
SH_INS_FCNVDS,
SH_INS_FCNVSD,
SH_INS_FDIV,
SH_INS_FIPR,
SH_INS_FLDI0,
SH_INS_FLDI1,
SH_INS_FLDS,
SH_INS_FLOAT,
SH_INS_FMAC,
SH_INS_FMOV,
SH_INS_FMUL,
SH_INS_FNEG,
SH_INS_FPCHG,
SH_INS_FRCHG,
SH_INS_FSCA,
SH_INS_FSCHG,
SH_INS_FSQRT,
SH_INS_FSRRA,
SH_INS_FSTS,
SH_INS_FSUB,
SH_INS_FTRC,
SH_INS_FTRV,
SH_INS_ICBI,
SH_INS_JMP,
SH_INS_JSR,
SH_INS_JSR_N,
SH_INS_LDBANK,
SH_INS_LDC,
SH_INS_LDRC,
SH_INS_LDRE,
SH_INS_LDRS,
SH_INS_LDS,
SH_INS_LDTLB,
SH_INS_MAC_L,
SH_INS_MAC_W,
SH_INS_MOV,
SH_INS_MOVA,
SH_INS_MOVCA,
SH_INS_MOVCO,
SH_INS_MOVI20,
SH_INS_MOVI20S,
SH_INS_MOVLI,
SH_INS_MOVML,
SH_INS_MOVMU,
SH_INS_MOVRT,
SH_INS_MOVT,
SH_INS_MOVU,
SH_INS_MOVUA,
SH_INS_MUL_L,
SH_INS_MULR,
SH_INS_MULS_W,
SH_INS_MULU_W,
SH_INS_NEG,
SH_INS_NEGC,
SH_INS_NOP,
SH_INS_NOT,
SH_INS_NOTT,
SH_INS_OCBI,
SH_INS_OCBP,
SH_INS_OCBWB,
SH_INS_OR,
SH_INS_PREF,
SH_INS_PREFI,
SH_INS_RESBANK,
SH_INS_ROTCL,
SH_INS_ROTCR,
SH_INS_ROTL,
SH_INS_ROTR,
SH_INS_RTE,
SH_INS_RTS,
SH_INS_RTS_N,
SH_INS_RTV_N,
SH_INS_SETDMX,
SH_INS_SETDMY,
SH_INS_SETRC,
SH_INS_SETS,
SH_INS_SETT,
SH_INS_SHAD,
SH_INS_SHAL,
SH_INS_SHAR,
SH_INS_SHLD,
SH_INS_SHLL,
SH_INS_SHLL16,
SH_INS_SHLL2,
SH_INS_SHLL8,
SH_INS_SHLR,
SH_INS_SHLR16,
SH_INS_SHLR2,
SH_INS_SHLR8,
SH_INS_SLEEP,
SH_INS_STBANK,
SH_INS_STC,
SH_INS_STS,
SH_INS_SUB,
SH_INS_SUBC,
SH_INS_SUBV,
SH_INS_SWAP_B,
SH_INS_SWAP_W,
SH_INS_SYNCO,
SH_INS_TAS,
SH_INS_TRAPA,
SH_INS_TST,
SH_INS_XOR,
SH_INS_XTRCT,
SH_INS_DSP,
SH_INS_ENDING, // <-- mark the end of the list of instructions
} sh_insn;
/// Instruction structure
typedef struct cs_sh {
sh_insn insn;
uint8_t size;
uint8_t op_count;
cs_sh_op operands[3];
} cs_sh;
/// Group of SH instructions
typedef enum sh_insn_group {
SH_GRP_INVALID = 0, ///< CS_GRUP_INVALID
SH_GRP_JUMP, ///< = CS_GRP_JUMP
SH_GRP_CALL, ///< = CS_GRP_CALL
SH_GRP_INT, ///< = CS_GRP_INT
SH_GRP_RET, ///< = CS_GRP_RET
SH_GRP_IRET, ///< = CS_GRP_IRET
SH_GRP_PRIVILEGE, ///< = CS_GRP_PRIVILEGE
SH_GRP_BRANCH_RELATIVE, ///< = CS_GRP_BRANCH_RELATIVE
SH_GRP_SH1,
SH_GRP_SH2,
SH_GRP_SH2E,
SH_GRP_SH2DSP,
SH_GRP_SH2A,
SH_GRP_SH2AFPU,
SH_GRP_SH3,
SH_GRP_SH3DSP,
SH_GRP_SH4,
SH_GRP_SH4A,
SH_GRP_ENDING,// <-- mark the end of the list of groups
} sh_insn_group;
#ifdef __cplusplus
}
#endif
#endif
external/capstone/include/capstone/sparc.h
Vendored
+1292
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File diff suppressed because it is too large Load Diff
external/capstone/include/capstone/systemz.h
Vendored
+3028
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File diff suppressed because it is too large Load Diff
external/capstone/include/capstone/systemz_compatibility.h
Vendored
+2966
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File diff suppressed because it is too large Load Diff
external/capstone/include/capstone/tms320c64x.h
Vendored
+360
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@@ -0,0 +1,360 @@
/* Capstone Disassembly Engine */
/* TMS320C64x Backend by Fotis Loukos <me@fotisl.com> 2016 */
#ifndef CAPSTONE_TMS320C64X_H
#define CAPSTONE_TMS320C64X_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include "platform.h"
#include "cs_operand.h"
#ifdef _MSC_VER
#pragma warning(disable:4201)
#endif
typedef enum tms320c64x_op_type {
TMS320C64X_OP_INVALID = CS_OP_INVALID, ///< = CS_OP_INVALID (Uninitialized).
TMS320C64X_OP_REG = CS_OP_REG, ///< = CS_OP_REG (Register operand).
TMS320C64X_OP_IMM = CS_OP_IMM, ///< = CS_OP_IMM (Immediate operand).
TMS320C64X_OP_REGPAIR = CS_OP_SPECIAL + 0, ///< Register pair for double word ops
TMS320C64X_OP_MEM = CS_OP_MEM, ///< = CS_OP_MEM (Memory operand).
} tms320c64x_op_type;
typedef enum tms320c64x_mem_disp {
TMS320C64X_MEM_DISP_INVALID = 0,
TMS320C64X_MEM_DISP_CONSTANT,
TMS320C64X_MEM_DISP_REGISTER,
} tms320c64x_mem_disp;
typedef enum tms320c64x_mem_dir {
TMS320C64X_MEM_DIR_INVALID = 0,
TMS320C64X_MEM_DIR_FW,
TMS320C64X_MEM_DIR_BW,
} tms320c64x_mem_dir;
typedef enum tms320c64x_mem_mod {
TMS320C64X_MEM_MOD_INVALID = 0,
TMS320C64X_MEM_MOD_NO,
TMS320C64X_MEM_MOD_PRE,
TMS320C64X_MEM_MOD_POST,
} tms320c64x_mem_mod;
typedef struct tms320c64x_op_mem {
unsigned int base; ///< base register
unsigned int disp; ///< displacement/offset value
unsigned int unit; ///< unit of base and offset register
unsigned int scaled; ///< offset scaled
unsigned int disptype; ///< displacement type
unsigned int direction; ///< direction
unsigned int modify; ///< modification
} tms320c64x_op_mem;
typedef struct cs_tms320c64x_op {
tms320c64x_op_type type; ///< operand type
union {
unsigned int reg; ///< register value for REG operand or first register for REGPAIR operand
int32_t imm; ///< immediate value for IMM operand
tms320c64x_op_mem mem; ///< base/disp value for MEM operand
};
} cs_tms320c64x_op;
typedef struct cs_tms320c64x {
uint8_t op_count;
cs_tms320c64x_op operands[8]; ///< operands for this instruction.
struct {
unsigned int reg;
unsigned int zero;
} condition;
struct {
unsigned int unit;
unsigned int side;
unsigned int crosspath;
} funit;
unsigned int parallel;
} cs_tms320c64x;
typedef enum tms320c64x_reg {
TMS320C64X_REG_INVALID = 0,
TMS320C64X_REG_AMR,
TMS320C64X_REG_CSR,
TMS320C64X_REG_DIER,
TMS320C64X_REG_DNUM,
TMS320C64X_REG_ECR,
TMS320C64X_REG_GFPGFR,
TMS320C64X_REG_GPLYA,
TMS320C64X_REG_GPLYB,
TMS320C64X_REG_ICR,
TMS320C64X_REG_IER,
TMS320C64X_REG_IERR,
TMS320C64X_REG_ILC,
TMS320C64X_REG_IRP,
TMS320C64X_REG_ISR,
TMS320C64X_REG_ISTP,
TMS320C64X_REG_ITSR,
TMS320C64X_REG_NRP,
TMS320C64X_REG_NTSR,
TMS320C64X_REG_REP,
TMS320C64X_REG_RILC,
TMS320C64X_REG_SSR,
TMS320C64X_REG_TSCH,
TMS320C64X_REG_TSCL,
TMS320C64X_REG_TSR,
TMS320C64X_REG_A0,
TMS320C64X_REG_A1,
TMS320C64X_REG_A2,
TMS320C64X_REG_A3,
TMS320C64X_REG_A4,
TMS320C64X_REG_A5,
TMS320C64X_REG_A6,
TMS320C64X_REG_A7,
TMS320C64X_REG_A8,
TMS320C64X_REG_A9,
TMS320C64X_REG_A10,
TMS320C64X_REG_A11,
TMS320C64X_REG_A12,
TMS320C64X_REG_A13,
TMS320C64X_REG_A14,
TMS320C64X_REG_A15,
TMS320C64X_REG_A16,
TMS320C64X_REG_A17,
TMS320C64X_REG_A18,
TMS320C64X_REG_A19,
TMS320C64X_REG_A20,
TMS320C64X_REG_A21,
TMS320C64X_REG_A22,
TMS320C64X_REG_A23,
TMS320C64X_REG_A24,
TMS320C64X_REG_A25,
TMS320C64X_REG_A26,
TMS320C64X_REG_A27,
TMS320C64X_REG_A28,
TMS320C64X_REG_A29,
TMS320C64X_REG_A30,
TMS320C64X_REG_A31,
TMS320C64X_REG_B0,
TMS320C64X_REG_B1,
TMS320C64X_REG_B2,
TMS320C64X_REG_B3,
TMS320C64X_REG_B4,
TMS320C64X_REG_B5,
TMS320C64X_REG_B6,
TMS320C64X_REG_B7,
TMS320C64X_REG_B8,
TMS320C64X_REG_B9,
TMS320C64X_REG_B10,
TMS320C64X_REG_B11,
TMS320C64X_REG_B12,
TMS320C64X_REG_B13,
TMS320C64X_REG_B14,
TMS320C64X_REG_B15,
TMS320C64X_REG_B16,
TMS320C64X_REG_B17,
TMS320C64X_REG_B18,
TMS320C64X_REG_B19,
TMS320C64X_REG_B20,
TMS320C64X_REG_B21,
TMS320C64X_REG_B22,
TMS320C64X_REG_B23,
TMS320C64X_REG_B24,
TMS320C64X_REG_B25,
TMS320C64X_REG_B26,
TMS320C64X_REG_B27,
TMS320C64X_REG_B28,
TMS320C64X_REG_B29,
TMS320C64X_REG_B30,
TMS320C64X_REG_B31,
TMS320C64X_REG_PCE1,
TMS320C64X_REG_ENDING, // <-- mark the end of the list of registers
// Alias registers
TMS320C64X_REG_EFR = TMS320C64X_REG_ECR,
TMS320C64X_REG_IFR = TMS320C64X_REG_ISR,
} tms320c64x_reg;
typedef enum tms320c64x_insn {
TMS320C64X_INS_INVALID = 0,
TMS320C64X_INS_ABS,
TMS320C64X_INS_ABS2,
TMS320C64X_INS_ADD,
TMS320C64X_INS_ADD2,
TMS320C64X_INS_ADD4,
TMS320C64X_INS_ADDAB,
TMS320C64X_INS_ADDAD,
TMS320C64X_INS_ADDAH,
TMS320C64X_INS_ADDAW,
TMS320C64X_INS_ADDK,
TMS320C64X_INS_ADDKPC,
TMS320C64X_INS_ADDU,
TMS320C64X_INS_AND,
TMS320C64X_INS_ANDN,
TMS320C64X_INS_AVG2,
TMS320C64X_INS_AVGU4,
TMS320C64X_INS_B,
TMS320C64X_INS_BDEC,
TMS320C64X_INS_BITC4,
TMS320C64X_INS_BNOP,
TMS320C64X_INS_BPOS,
TMS320C64X_INS_CLR,
TMS320C64X_INS_CMPEQ,
TMS320C64X_INS_CMPEQ2,
TMS320C64X_INS_CMPEQ4,
TMS320C64X_INS_CMPGT,
TMS320C64X_INS_CMPGT2,
TMS320C64X_INS_CMPGTU4,
TMS320C64X_INS_CMPLT,
TMS320C64X_INS_CMPLTU,
TMS320C64X_INS_DEAL,
TMS320C64X_INS_DOTP2,
TMS320C64X_INS_DOTPN2,
TMS320C64X_INS_DOTPNRSU2,
TMS320C64X_INS_DOTPRSU2,
TMS320C64X_INS_DOTPSU4,
TMS320C64X_INS_DOTPU4,
TMS320C64X_INS_EXT,
TMS320C64X_INS_EXTU,
TMS320C64X_INS_GMPGTU,
TMS320C64X_INS_GMPY4,
TMS320C64X_INS_LDB,
TMS320C64X_INS_LDBU,
TMS320C64X_INS_LDDW,
TMS320C64X_INS_LDH,
TMS320C64X_INS_LDHU,
TMS320C64X_INS_LDNDW,
TMS320C64X_INS_LDNW,
TMS320C64X_INS_LDW,
TMS320C64X_INS_LMBD,
TMS320C64X_INS_MAX2,
TMS320C64X_INS_MAXU4,
TMS320C64X_INS_MIN2,
TMS320C64X_INS_MINU4,
TMS320C64X_INS_MPY,
TMS320C64X_INS_MPY2,
TMS320C64X_INS_MPYH,
TMS320C64X_INS_MPYHI,
TMS320C64X_INS_MPYHIR,
TMS320C64X_INS_MPYHL,
TMS320C64X_INS_MPYHLU,
TMS320C64X_INS_MPYHSLU,
TMS320C64X_INS_MPYHSU,
TMS320C64X_INS_MPYHU,
TMS320C64X_INS_MPYHULS,
TMS320C64X_INS_MPYHUS,
TMS320C64X_INS_MPYLH,
TMS320C64X_INS_MPYLHU,
TMS320C64X_INS_MPYLI,
TMS320C64X_INS_MPYLIR,
TMS320C64X_INS_MPYLSHU,
TMS320C64X_INS_MPYLUHS,
TMS320C64X_INS_MPYSU,
TMS320C64X_INS_MPYSU4,
TMS320C64X_INS_MPYU,
TMS320C64X_INS_MPYU4,
TMS320C64X_INS_MPYUS,
TMS320C64X_INS_MVC,
TMS320C64X_INS_MVD,
TMS320C64X_INS_MVK,
TMS320C64X_INS_MVKL,
TMS320C64X_INS_MVKLH,
TMS320C64X_INS_NOP,
TMS320C64X_INS_NORM,
TMS320C64X_INS_OR,
TMS320C64X_INS_PACK2,
TMS320C64X_INS_PACKH2,
TMS320C64X_INS_PACKH4,
TMS320C64X_INS_PACKHL2,
TMS320C64X_INS_PACKL4,
TMS320C64X_INS_PACKLH2,
TMS320C64X_INS_ROTL,
TMS320C64X_INS_SADD,
TMS320C64X_INS_SADD2,
TMS320C64X_INS_SADDU4,
TMS320C64X_INS_SADDUS2,
TMS320C64X_INS_SAT,
TMS320C64X_INS_SET,
TMS320C64X_INS_SHFL,
TMS320C64X_INS_SHL,
TMS320C64X_INS_SHLMB,
TMS320C64X_INS_SHR,
TMS320C64X_INS_SHR2,
TMS320C64X_INS_SHRMB,
TMS320C64X_INS_SHRU,
TMS320C64X_INS_SHRU2,
TMS320C64X_INS_SMPY,
TMS320C64X_INS_SMPY2,
TMS320C64X_INS_SMPYH,
TMS320C64X_INS_SMPYHL,
TMS320C64X_INS_SMPYLH,
TMS320C64X_INS_SPACK2,
TMS320C64X_INS_SPACKU4,
TMS320C64X_INS_SSHL,
TMS320C64X_INS_SSHVL,
TMS320C64X_INS_SSHVR,
TMS320C64X_INS_SSUB,
TMS320C64X_INS_STB,
TMS320C64X_INS_STDW,
TMS320C64X_INS_STH,
TMS320C64X_INS_STNDW,
TMS320C64X_INS_STNW,
TMS320C64X_INS_STW,
TMS320C64X_INS_SUB,
TMS320C64X_INS_SUB2,
TMS320C64X_INS_SUB4,
TMS320C64X_INS_SUBAB,
TMS320C64X_INS_SUBABS4,
TMS320C64X_INS_SUBAH,
TMS320C64X_INS_SUBAW,
TMS320C64X_INS_SUBC,
TMS320C64X_INS_SUBU,
TMS320C64X_INS_SWAP4,
TMS320C64X_INS_UNPKHU4,
TMS320C64X_INS_UNPKLU4,
TMS320C64X_INS_XOR,
TMS320C64X_INS_XPND2,
TMS320C64X_INS_XPND4,
// Aliases
TMS320C64X_INS_IDLE,
TMS320C64X_INS_MV,
TMS320C64X_INS_NEG,
TMS320C64X_INS_NOT,
TMS320C64X_INS_SWAP2,
TMS320C64X_INS_ZERO,
TMS320C64X_INS_ENDING, // <-- mark the end of the list of instructions
} tms320c64x_insn;
typedef enum tms320c64x_insn_group {
TMS320C64X_GRP_INVALID = 0, ///< = CS_GRP_INVALID
TMS320C64X_GRP_JUMP, ///< = CS_GRP_JUMP
TMS320C64X_GRP_FUNIT_D = 128,
TMS320C64X_GRP_FUNIT_L,
TMS320C64X_GRP_FUNIT_M,
TMS320C64X_GRP_FUNIT_S,
TMS320C64X_GRP_FUNIT_NO,
TMS320C64X_GRP_ENDING, // <-- mark the end of the list of groups
} tms320c64x_insn_group;
typedef enum tms320c64x_funit {
TMS320C64X_FUNIT_INVALID = 0,
TMS320C64X_FUNIT_D,
TMS320C64X_FUNIT_L,
TMS320C64X_FUNIT_M,
TMS320C64X_FUNIT_S,
TMS320C64X_FUNIT_NO
} tms320c64x_funit;
#ifdef __cplusplus
}
#endif
#endif
external/capstone/include/capstone/tricore.h
Vendored
+617
View File
@@ -0,0 +1,617 @@
#ifndef CAPSTONE_TRICORE_H
#define CAPSTONE_TRICORE_H
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2014 */
#ifdef __cplusplus
extern "C" {
#endif
#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
#include <stdint.h>
#endif
#include "cs_operand.h"
#include "platform.h"
#ifdef _MSC_VER
#pragma warning(disable : 4201)
#endif
/// Operand type for instruction's operands
typedef enum tricore_op_type {
TRICORE_OP_INVALID = CS_OP_INVALID, ///< CS_OP_INVALID (Uninitialized).
TRICORE_OP_REG = CS_OP_REG, ///< CS_OP_REG (Register operand).
TRICORE_OP_IMM = CS_OP_IMM, ///< CS_OP_IMM (Immediate operand).
TRICORE_OP_MEM = CS_OP_MEM, ///< CS_OP_MEM (Memory operand).
} tricore_op_type;
/// Instruction's operand referring to memory
/// This is associated with TRICORE_OP_MEM operand type above
typedef struct tricore_op_mem {
uint8_t base; ///< base register
int64_t disp; ///< displacement/offset value
} tricore_op_mem;
/// Instruction operand
typedef struct cs_tricore_op {
tricore_op_type type; ///< operand type
union {
unsigned int reg; ///< register value for REG operand
int64_t imm; ///< immediate value for IMM operand
tricore_op_mem mem; ///< base/disp value for MEM operand
};
/// This field is combined of cs_ac_type.
/// NOTE: this field is irrelevant if engine is compiled in DIET mode.
cs_ac_type access; ///< How is this operand accessed? (READ, WRITE or READ|WRITE)
} cs_tricore_op;
#define NUM_TRICORE_OPS 8
/// Instruction structure
typedef struct cs_tricore {
uint8_t op_count; ///< number of operands of this instruction.
cs_tricore_op
operands[NUM_TRICORE_OPS]; ///< operands for this instruction.
/// TODO: Mark the modified flags register in td files and regenerate inc files
bool update_flags; ///< whether the flags register is updated.
} cs_tricore;
/// TriCore registers
typedef enum tricore_reg {
// generated content <TriCoreGenCSRegEnum.inc> begin
// clang-format off
TRICORE_REG_INVALID = 0,
TRICORE_REG_FCX = 1,
TRICORE_REG_PC = 2,
TRICORE_REG_PCXI = 3,
TRICORE_REG_PSW = 4,
TRICORE_REG_A0 = 5,
TRICORE_REG_A1 = 6,
TRICORE_REG_A2 = 7,
TRICORE_REG_A3 = 8,
TRICORE_REG_A4 = 9,
TRICORE_REG_A5 = 10,
TRICORE_REG_A6 = 11,
TRICORE_REG_A7 = 12,
TRICORE_REG_A8 = 13,
TRICORE_REG_A9 = 14,
TRICORE_REG_A10 = 15,
TRICORE_REG_A11 = 16,
TRICORE_REG_A12 = 17,
TRICORE_REG_A13 = 18,
TRICORE_REG_A14 = 19,
TRICORE_REG_A15 = 20,
TRICORE_REG_D0 = 21,
TRICORE_REG_D1 = 22,
TRICORE_REG_D2 = 23,
TRICORE_REG_D3 = 24,
TRICORE_REG_D4 = 25,
TRICORE_REG_D5 = 26,
TRICORE_REG_D6 = 27,
TRICORE_REG_D7 = 28,
TRICORE_REG_D8 = 29,
TRICORE_REG_D9 = 30,
TRICORE_REG_D10 = 31,
TRICORE_REG_D11 = 32,
TRICORE_REG_D12 = 33,
TRICORE_REG_D13 = 34,
TRICORE_REG_D14 = 35,
TRICORE_REG_D15 = 36,
TRICORE_REG_E0 = 37,
TRICORE_REG_E2 = 38,
TRICORE_REG_E4 = 39,
TRICORE_REG_E6 = 40,
TRICORE_REG_E8 = 41,
TRICORE_REG_E10 = 42,
TRICORE_REG_E12 = 43,
TRICORE_REG_E14 = 44,
TRICORE_REG_P0 = 45,
TRICORE_REG_P2 = 46,
TRICORE_REG_P4 = 47,
TRICORE_REG_P6 = 48,
TRICORE_REG_P8 = 49,
TRICORE_REG_P10 = 50,
TRICORE_REG_P12 = 51,
TRICORE_REG_P14 = 52,
TRICORE_REG_A0_A1 = 53,
TRICORE_REG_A2_A3 = 54,
TRICORE_REG_A4_A5 = 55,
TRICORE_REG_A6_A7 = 56,
TRICORE_REG_A8_A9 = 57,
TRICORE_REG_A10_A11 = 58,
TRICORE_REG_A12_A13 = 59,
TRICORE_REG_A14_A15 = 60,
TRICORE_REG_ENDING, // 61
// clang-format on
// generated content <TriCoreGenCSRegEnum.inc> end
} tricore_reg;
/// TriCore instruction
typedef enum tricore_insn {
// generated content <TriCoreGenCSInsnEnum.inc> begin
// clang-format off
TRICORE_INS_INVALID,
TRICORE_INS_ABSDIFS_B,
TRICORE_INS_ABSDIFS_H,
TRICORE_INS_ABSDIFS,
TRICORE_INS_ABSDIF_B,
TRICORE_INS_ABSDIF_H,
TRICORE_INS_ABSDIF,
TRICORE_INS_ABSS_B,
TRICORE_INS_ABSS_H,
TRICORE_INS_ABSS,
TRICORE_INS_ABS_B,
TRICORE_INS_ABS_DF,
TRICORE_INS_ABS_F,
TRICORE_INS_ABS_H,
TRICORE_INS_ABS,
TRICORE_INS_ADDC,
TRICORE_INS_ADDIH_A,
TRICORE_INS_ADDIH,
TRICORE_INS_ADDI,
TRICORE_INS_ADDSC_AT,
TRICORE_INS_ADDSC_A,
TRICORE_INS_ADDS_BU,
TRICORE_INS_ADDS_B,
TRICORE_INS_ADDS_H,
TRICORE_INS_ADDS_HU,
TRICORE_INS_ADDS_U,
TRICORE_INS_ADDS,
TRICORE_INS_ADDX,
TRICORE_INS_ADD_A,
TRICORE_INS_ADD_B,
TRICORE_INS_ADD_DF,
TRICORE_INS_ADD_F,
TRICORE_INS_ADD_H,
TRICORE_INS_ADD,
TRICORE_INS_ANDN_T,
TRICORE_INS_ANDN,
TRICORE_INS_AND_ANDN_T,
TRICORE_INS_AND_AND_T,
TRICORE_INS_AND_EQ,
TRICORE_INS_AND_GE_U,
TRICORE_INS_AND_GE,
TRICORE_INS_AND_LT_U,
TRICORE_INS_AND_LT,
TRICORE_INS_AND_NE,
TRICORE_INS_AND_NOR_T,
TRICORE_INS_AND_OR_T,
TRICORE_INS_AND_T,
TRICORE_INS_AND,
TRICORE_INS_BISR,
TRICORE_INS_BMERGE,
TRICORE_INS_BSPLIT,
TRICORE_INS_CACHEA_I,
TRICORE_INS_CACHEA_WI,
TRICORE_INS_CACHEA_W,
TRICORE_INS_CACHEI_I,
TRICORE_INS_CACHEI_WI,
TRICORE_INS_CACHEI_W,
TRICORE_INS_CADDN_A,
TRICORE_INS_CADDN,
TRICORE_INS_CADD_A,
TRICORE_INS_CADD,
TRICORE_INS_CALLA,
TRICORE_INS_CALLI,
TRICORE_INS_CALL,
TRICORE_INS_CLO_B,
TRICORE_INS_CLO_H,
TRICORE_INS_CLO,
TRICORE_INS_CLS_B,
TRICORE_INS_CLS_H,
TRICORE_INS_CLS,
TRICORE_INS_CLZ_B,
TRICORE_INS_CLZ_H,
TRICORE_INS_CLZ,
TRICORE_INS_CMOVN,
TRICORE_INS_CMOV,
TRICORE_INS_CMPSWAP_W,
TRICORE_INS_CMP_DF,
TRICORE_INS_CMP_F,
TRICORE_INS_CRC32B_W,
TRICORE_INS_CRC32L_W,
TRICORE_INS_CRC32_B,
TRICORE_INS_CRCN,
TRICORE_INS_CSUBN_A,
TRICORE_INS_CSUBN,
TRICORE_INS_CSUB_A,
TRICORE_INS_CSUB,
TRICORE_INS_DEBUG,
TRICORE_INS_DEXTR,
TRICORE_INS_DFTOF,
TRICORE_INS_DFTOIN,
TRICORE_INS_DFTOIZ,
TRICORE_INS_DFTOI,
TRICORE_INS_DFTOLZ,
TRICORE_INS_DFTOL,
TRICORE_INS_DFTOULZ,
TRICORE_INS_DFTOUL,
TRICORE_INS_DFTOUZ,
TRICORE_INS_DFTOU,
TRICORE_INS_DIFSC_A,
TRICORE_INS_DISABLE,
TRICORE_INS_DIV64_U,
TRICORE_INS_DIV64,
TRICORE_INS_DIV_DF,
TRICORE_INS_DIV_F,
TRICORE_INS_DIV_U,
TRICORE_INS_DIV,
TRICORE_INS_DSYNC,
TRICORE_INS_DVADJ,
TRICORE_INS_DVINIT_BU,
TRICORE_INS_DVINIT_B,
TRICORE_INS_DVINIT_HU,
TRICORE_INS_DVINIT_H,
TRICORE_INS_DVINIT_U,
TRICORE_INS_DVINIT,
TRICORE_INS_DVSTEP_U,
TRICORE_INS_DVSTEP,
TRICORE_INS_ENABLE,
TRICORE_INS_EQANY_B,
TRICORE_INS_EQANY_H,
TRICORE_INS_EQZ_A,
TRICORE_INS_EQ_A,
TRICORE_INS_EQ_B,
TRICORE_INS_EQ_H,
TRICORE_INS_EQ_W,
TRICORE_INS_EQ,
TRICORE_INS_EXTR_U,
TRICORE_INS_EXTR,
TRICORE_INS_FCALLA,
TRICORE_INS_FCALLI,
TRICORE_INS_FCALL,
TRICORE_INS_FRET,
TRICORE_INS_FTODF,
TRICORE_INS_FTOHP,
TRICORE_INS_FTOIN,
TRICORE_INS_FTOIZ,
TRICORE_INS_FTOI,
TRICORE_INS_FTOQ31Z,
TRICORE_INS_FTOQ31,
TRICORE_INS_FTOUZ,
TRICORE_INS_FTOU,
TRICORE_INS_GE_A,
TRICORE_INS_GE_U,
TRICORE_INS_GE,
TRICORE_INS_HPTOF,
TRICORE_INS_IMASK,
TRICORE_INS_INSERT,
TRICORE_INS_INSN_T,
TRICORE_INS_INS_T,
TRICORE_INS_ISYNC,
TRICORE_INS_ITODF,
TRICORE_INS_ITOF,
TRICORE_INS_IXMAX_U,
TRICORE_INS_IXMAX,
TRICORE_INS_IXMIN_U,
TRICORE_INS_IXMIN,
TRICORE_INS_JA,
TRICORE_INS_JEQ_A,
TRICORE_INS_JEQ,
TRICORE_INS_JGEZ,
TRICORE_INS_JGE_U,
TRICORE_INS_JGE,
TRICORE_INS_JGTZ,
TRICORE_INS_JI,
TRICORE_INS_JLA,
TRICORE_INS_JLEZ,
TRICORE_INS_JLI,
TRICORE_INS_JLTZ,
TRICORE_INS_JLT_U,
TRICORE_INS_JLT,
TRICORE_INS_JL,
TRICORE_INS_JNED,
TRICORE_INS_JNEI,
TRICORE_INS_JNE_A,
TRICORE_INS_JNE,
TRICORE_INS_JNZ_A,
TRICORE_INS_JNZ_T,
TRICORE_INS_JNZ,
TRICORE_INS_JZ_A,
TRICORE_INS_JZ_T,
TRICORE_INS_JZ,
TRICORE_INS_J,
TRICORE_INS_LDLCX,
TRICORE_INS_LDMST,
TRICORE_INS_LDUCX,
TRICORE_INS_LD_A,
TRICORE_INS_LD_BU,
TRICORE_INS_LD_B,
TRICORE_INS_LD_DA,
TRICORE_INS_LD_D,
TRICORE_INS_LD_HU,
TRICORE_INS_LD_H,
TRICORE_INS_LD_Q,
TRICORE_INS_LD_W,
TRICORE_INS_LEA,
TRICORE_INS_LHA,
TRICORE_INS_LOOPU,
TRICORE_INS_LOOP,
TRICORE_INS_LTODF,
TRICORE_INS_LT_A,
TRICORE_INS_LT_B,
TRICORE_INS_LT_BU,
TRICORE_INS_LT_H,
TRICORE_INS_LT_HU,
TRICORE_INS_LT_U,
TRICORE_INS_LT_W,
TRICORE_INS_LT_WU,
TRICORE_INS_LT,
TRICORE_INS_MADDMS_H,
TRICORE_INS_MADDMS_U,
TRICORE_INS_MADDMS,
TRICORE_INS_MADDM_H,
TRICORE_INS_MADDM_Q,
TRICORE_INS_MADDM_U,
TRICORE_INS_MADDM,
TRICORE_INS_MADDRS_H,
TRICORE_INS_MADDRS_Q,
TRICORE_INS_MADDR_H,
TRICORE_INS_MADDR_Q,
TRICORE_INS_MADDSUMS_H,
TRICORE_INS_MADDSUM_H,
TRICORE_INS_MADDSURS_H,
TRICORE_INS_MADDSUR_H,
TRICORE_INS_MADDSUS_H,
TRICORE_INS_MADDSU_H,
TRICORE_INS_MADDS_H,
TRICORE_INS_MADDS_Q,
TRICORE_INS_MADDS_U,
TRICORE_INS_MADDS,
TRICORE_INS_MADD_DF,
TRICORE_INS_MADD_F,
TRICORE_INS_MADD_H,
TRICORE_INS_MADD_Q,
TRICORE_INS_MADD_U,
TRICORE_INS_MADD,
TRICORE_INS_MAX_B,
TRICORE_INS_MAX_BU,
TRICORE_INS_MAX_DF,
TRICORE_INS_MAX_F,
TRICORE_INS_MAX_H,
TRICORE_INS_MAX_HU,
TRICORE_INS_MAX_U,
TRICORE_INS_MAX,
TRICORE_INS_MFCR,
TRICORE_INS_MIN_B,
TRICORE_INS_MIN_BU,
TRICORE_INS_MIN_DF,
TRICORE_INS_MIN_F,
TRICORE_INS_MIN_H,
TRICORE_INS_MIN_HU,
TRICORE_INS_MIN_U,
TRICORE_INS_MIN,
TRICORE_INS_MOVH_A,
TRICORE_INS_MOVH,
TRICORE_INS_MOVZ_A,
TRICORE_INS_MOV_AA,
TRICORE_INS_MOV_A,
TRICORE_INS_MOV_D,
TRICORE_INS_MOV_U,
TRICORE_INS_MOV,
TRICORE_INS_MSUBADMS_H,
TRICORE_INS_MSUBADM_H,
TRICORE_INS_MSUBADRS_H,
TRICORE_INS_MSUBADR_H,
TRICORE_INS_MSUBADS_H,
TRICORE_INS_MSUBAD_H,
TRICORE_INS_MSUBMS_H,
TRICORE_INS_MSUBMS_U,
TRICORE_INS_MSUBMS,
TRICORE_INS_MSUBM_H,
TRICORE_INS_MSUBM_Q,
TRICORE_INS_MSUBM_U,
TRICORE_INS_MSUBM,
TRICORE_INS_MSUBRS_H,
TRICORE_INS_MSUBRS_Q,
TRICORE_INS_MSUBR_H,
TRICORE_INS_MSUBR_Q,
TRICORE_INS_MSUBS_H,
TRICORE_INS_MSUBS_Q,
TRICORE_INS_MSUBS_U,
TRICORE_INS_MSUBS,
TRICORE_INS_MSUB_DF,
TRICORE_INS_MSUB_F,
TRICORE_INS_MSUB_H,
TRICORE_INS_MSUB_Q,
TRICORE_INS_MSUB_U,
TRICORE_INS_MSUB,
TRICORE_INS_MTCR,
TRICORE_INS_MULMS_H,
TRICORE_INS_MULM_H,
TRICORE_INS_MULM_U,
TRICORE_INS_MULM,
TRICORE_INS_MULR_H,
TRICORE_INS_MULR_Q,
TRICORE_INS_MULS_U,
TRICORE_INS_MULS,
TRICORE_INS_MUL_DF,
TRICORE_INS_MUL_F,
TRICORE_INS_MUL_H,
TRICORE_INS_MUL_Q,
TRICORE_INS_MUL_U,
TRICORE_INS_MUL,
TRICORE_INS_NAND_T,
TRICORE_INS_NAND,
TRICORE_INS_NEG_DF,
TRICORE_INS_NEG_F,
TRICORE_INS_NEZ_A,
TRICORE_INS_NE_A,
TRICORE_INS_NE,
TRICORE_INS_NOP,
TRICORE_INS_NOR_T,
TRICORE_INS_NOR,
TRICORE_INS_NOT,
TRICORE_INS_ORN_T,
TRICORE_INS_ORN,
TRICORE_INS_OR_ANDN_T,
TRICORE_INS_OR_AND_T,
TRICORE_INS_OR_EQ,
TRICORE_INS_OR_GE_U,
TRICORE_INS_OR_GE,
TRICORE_INS_OR_LT_U,
TRICORE_INS_OR_LT,
TRICORE_INS_OR_NE,
TRICORE_INS_OR_NOR_T,
TRICORE_INS_OR_OR_T,
TRICORE_INS_OR_T,
TRICORE_INS_OR,
TRICORE_INS_PACK,
TRICORE_INS_PARITY,
TRICORE_INS_POPCNT_W,
TRICORE_INS_Q31TOF,
TRICORE_INS_QSEED_DF,
TRICORE_INS_QSEED_F,
TRICORE_INS_REM64_U,
TRICORE_INS_REM64,
TRICORE_INS_RESTORE,
TRICORE_INS_RET,
TRICORE_INS_RFE,
TRICORE_INS_RFM,
TRICORE_INS_RSLCX,
TRICORE_INS_RSTV,
TRICORE_INS_RSUBS_U,
TRICORE_INS_RSUBS,
TRICORE_INS_RSUB,
TRICORE_INS_SAT_BU,
TRICORE_INS_SAT_B,
TRICORE_INS_SAT_HU,
TRICORE_INS_SAT_H,
TRICORE_INS_SELN_A,
TRICORE_INS_SELN,
TRICORE_INS_SEL_A,
TRICORE_INS_SEL,
TRICORE_INS_SHAS,
TRICORE_INS_SHA_B,
TRICORE_INS_SHA_H,
TRICORE_INS_SHA,
TRICORE_INS_SHUFFLE,
TRICORE_INS_SH_ANDN_T,
TRICORE_INS_SH_AND_T,
TRICORE_INS_SH_B,
TRICORE_INS_SH_EQ,
TRICORE_INS_SH_GE_U,
TRICORE_INS_SH_GE,
TRICORE_INS_SH_H,
TRICORE_INS_SH_LT_U,
TRICORE_INS_SH_LT,
TRICORE_INS_SH_NAND_T,
TRICORE_INS_SH_NE,
TRICORE_INS_SH_NOR_T,
TRICORE_INS_SH_ORN_T,
TRICORE_INS_SH_OR_T,
TRICORE_INS_SH_XNOR_T,
TRICORE_INS_SH_XOR_T,
TRICORE_INS_SH,
TRICORE_INS_STLCX,
TRICORE_INS_STUCX,
TRICORE_INS_ST_A,
TRICORE_INS_ST_B,
TRICORE_INS_ST_DA,
TRICORE_INS_ST_D,
TRICORE_INS_ST_H,
TRICORE_INS_ST_Q,
TRICORE_INS_ST_T,
TRICORE_INS_ST_W,
TRICORE_INS_SUBC,
TRICORE_INS_SUBSC_A,
TRICORE_INS_SUBS_BU,
TRICORE_INS_SUBS_B,
TRICORE_INS_SUBS_HU,
TRICORE_INS_SUBS_H,
TRICORE_INS_SUBS_U,
TRICORE_INS_SUBS,
TRICORE_INS_SUBX,
TRICORE_INS_SUB_A,
TRICORE_INS_SUB_B,
TRICORE_INS_SUB_DF,
TRICORE_INS_SUB_F,
TRICORE_INS_SUB_H,
TRICORE_INS_SUB,
TRICORE_INS_SVLCX,
TRICORE_INS_SWAPMSK_W,
TRICORE_INS_SWAP_A,
TRICORE_INS_SWAP_W,
TRICORE_INS_SYSCALL,
TRICORE_INS_TLBDEMAP,
TRICORE_INS_TLBFLUSH_A,
TRICORE_INS_TLBFLUSH_B,
TRICORE_INS_TLBMAP,
TRICORE_INS_TLBPROBE_A,
TRICORE_INS_TLBPROBE_I,
TRICORE_INS_TRAPSV,
TRICORE_INS_TRAPV,
TRICORE_INS_ULTODF,
TRICORE_INS_UNPACK,
TRICORE_INS_UPDFL,
TRICORE_INS_UTODF,
TRICORE_INS_UTOF,
TRICORE_INS_WAIT,
TRICORE_INS_XNOR_T,
TRICORE_INS_XNOR,
TRICORE_INS_XOR_EQ,
TRICORE_INS_XOR_GE_U,
TRICORE_INS_XOR_GE,
TRICORE_INS_XOR_LT_U,
TRICORE_INS_XOR_LT,
TRICORE_INS_XOR_NE,
TRICORE_INS_XOR_T,
TRICORE_INS_XOR,
// clang-format on
// generated content <TriCoreGenCSInsnEnum.inc> end
TRICORE_INS_ENDING, // <-- mark the end of the list of instructions
} tricore_insn;
/// Group of TriCore instructions
typedef enum tricore_insn_group {
TRICORE_GRP_INVALID, ///< = CS_GRP_INVALID
/// Generic groups
TRICORE_GRP_CALL, ///< = CS_GRP_CALL
TRICORE_GRP_JUMP, ///< = CS_GRP_JUMP
TRICORE_GRP_ENDING, ///< mark the end of the list of groups
} tricore_insn_group;
typedef enum tricore_feature_t {
TRICORE_FEATURE_INVALID = 0,
// generated content <TriCoreGenCSFeatureEnum.inc> begin
// clang-format off
TRICORE_FEATURE_HASV110 = 128,
TRICORE_FEATURE_HASV120,
TRICORE_FEATURE_HASV130,
TRICORE_FEATURE_HASV131,
TRICORE_FEATURE_HASV160,
TRICORE_FEATURE_HASV161,
TRICORE_FEATURE_HASV162,
TRICORE_FEATURE_HASV180,
TRICORE_FEATURE_HASV120_UP,
TRICORE_FEATURE_HASV130_UP,
TRICORE_FEATURE_HASV131_UP,
TRICORE_FEATURE_HASV160_UP,
TRICORE_FEATURE_HASV161_UP,
TRICORE_FEATURE_HASV162_UP,
TRICORE_FEATURE_HASV180_UP,
TRICORE_FEATURE_HASV120_DN,
TRICORE_FEATURE_HASV130_DN,
TRICORE_FEATURE_HASV131_DN,
TRICORE_FEATURE_HASV160_DN,
TRICORE_FEATURE_HASV161_DN,
TRICORE_FEATURE_HASV162_DN,
TRICORE_FEATURE_HASV180_DN,
// clang-format on
// generated content <TriCoreGenCSFeatureEnum.inc> end
TRICORE_FEATURE_ENDING, ///< mark the end of the list of features
} tricore_feature;
#ifdef __cplusplus
}
#endif
#endif
external/capstone/include/capstone/wasm.h
Vendored
+251
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@@ -0,0 +1,251 @@
/* Capstone Disassembly Engine */
/* By Spike <spikeinhouse@gmail.com>, xwings 2019 */
#ifndef CAPSTONE_WASM_H
#define CAPSTONE_WASM_H
#ifdef __cplusplus
extern "C" {
#endif
#include "platform.h"
#include "cs_operand.h"
#ifdef _MSC_VER
#pragma warning(disable:4201)
#endif
typedef enum wasm_op_type {
WASM_OP_INVALID = CS_OP_INVALID,
WASM_OP_IMM = CS_OP_IMM,
WASM_OP_NONE = CS_OP_SPECIAL + 0,
WASM_OP_INT7 = CS_OP_SPECIAL + 1,
WASM_OP_VARUINT32 = CS_OP_SPECIAL + 2,
WASM_OP_VARUINT64 = CS_OP_SPECIAL + 3,
WASM_OP_UINT32 = CS_OP_SPECIAL + 4,
WASM_OP_UINT64 = CS_OP_SPECIAL + 5,
WASM_OP_BRTABLE = CS_OP_SPECIAL + 6,
} wasm_op_type;
typedef struct cs_wasm_brtable {
uint32_t length;
uint64_t address;
uint32_t default_target;
} cs_wasm_brtable;
typedef struct cs_wasm_op {
wasm_op_type type;
uint32_t size;
union {
int8_t int7;
uint32_t varuint32;
uint64_t varuint64;
uint32_t uint32;
uint64_t uint64;
uint32_t immediate[2];
cs_wasm_brtable brtable;
};
} cs_wasm_op;
/// Instruction structure
typedef struct cs_wasm {
uint8_t op_count;
cs_wasm_op operands[2];
} cs_wasm;
/// WASM instruction
typedef enum wasm_insn {
WASM_INS_UNREACHABLE = 0x0,
WASM_INS_NOP = 0x1,
WASM_INS_BLOCK = 0x2,
WASM_INS_LOOP = 0x3,
WASM_INS_IF = 0x4,
WASM_INS_ELSE = 0x5,
WASM_INS_END = 0xb,
WASM_INS_BR = 0xc,
WASM_INS_BR_IF = 0xd,
WASM_INS_BR_TABLE = 0xe,
WASM_INS_RETURN = 0xf,
WASM_INS_CALL = 0x10,
WASM_INS_CALL_INDIRECT = 0x11,
WASM_INS_DROP = 0x1a,
WASM_INS_SELECT = 0x1b,
WASM_INS_GET_LOCAL = 0x20,
WASM_INS_SET_LOCAL = 0x21,
WASM_INS_TEE_LOCAL = 0x22,
WASM_INS_GET_GLOBAL = 0x23,
WASM_INS_SET_GLOBAL = 0x24,
WASM_INS_I32_LOAD = 0x28,
WASM_INS_I64_LOAD = 0x29,
WASM_INS_F32_LOAD = 0x2a,
WASM_INS_F64_LOAD = 0x2b,
WASM_INS_I32_LOAD8_S = 0x2c,
WASM_INS_I32_LOAD8_U = 0x2d,
WASM_INS_I32_LOAD16_S = 0x2e,
WASM_INS_I32_LOAD16_U = 0x2f,
WASM_INS_I64_LOAD8_S = 0x30,
WASM_INS_I64_LOAD8_U = 0x31,
WASM_INS_I64_LOAD16_S = 0x32,
WASM_INS_I64_LOAD16_U = 0x33,
WASM_INS_I64_LOAD32_S = 0x34,
WASM_INS_I64_LOAD32_U = 0x35,
WASM_INS_I32_STORE = 0x36,
WASM_INS_I64_STORE = 0x37,
WASM_INS_F32_STORE = 0x38,
WASM_INS_F64_STORE = 0x39,
WASM_INS_I32_STORE8 = 0x3a,
WASM_INS_I32_STORE16 = 0x3b,
WASM_INS_I64_STORE8 = 0x3c,
WASM_INS_I64_STORE16 = 0x3d,
WASM_INS_I64_STORE32 = 0x3e,
WASM_INS_CURRENT_MEMORY = 0x3f,
WASM_INS_GROW_MEMORY = 0x40,
WASM_INS_I32_CONST = 0x41,
WASM_INS_I64_CONST = 0x42,
WASM_INS_F32_CONST = 0x43,
WASM_INS_F64_CONST = 0x44,
WASM_INS_I32_EQZ = 0x45,
WASM_INS_I32_EQ = 0x46,
WASM_INS_I32_NE = 0x47,
WASM_INS_I32_LT_S = 0x48,
WASM_INS_I32_LT_U = 0x49,
WASM_INS_I32_GT_S = 0x4a,
WASM_INS_I32_GT_U = 0x4b,
WASM_INS_I32_LE_S = 0x4c,
WASM_INS_I32_LE_U = 0x4d,
WASM_INS_I32_GE_S = 0x4e,
WASM_INS_I32_GE_U = 0x4f,
WASM_INS_I64_EQZ = 0x50,
WASM_INS_I64_EQ = 0x51,
WASM_INS_I64_NE = 0x52,
WASM_INS_I64_LT_S = 0x53,
WASM_INS_I64_LT_U = 0x54,
WASN_INS_I64_GT_S = 0x55,
WASM_INS_I64_GT_U = 0x56,
WASM_INS_I64_LE_S = 0x57,
WASM_INS_I64_LE_U = 0x58,
WASM_INS_I64_GE_S = 0x59,
WASM_INS_I64_GE_U = 0x5a,
WASM_INS_F32_EQ = 0x5b,
WASM_INS_F32_NE = 0x5c,
WASM_INS_F32_LT = 0x5d,
WASM_INS_F32_GT = 0x5e,
WASM_INS_F32_LE = 0x5f,
WASM_INS_F32_GE = 0x60,
WASM_INS_F64_EQ = 0x61,
WASM_INS_F64_NE = 0x62,
WASM_INS_F64_LT = 0x63,
WASM_INS_F64_GT = 0x64,
WASM_INS_F64_LE = 0x65,
WASM_INS_F64_GE = 0x66,
WASM_INS_I32_CLZ = 0x67,
WASM_INS_I32_CTZ = 0x68,
WASM_INS_I32_POPCNT = 0x69,
WASM_INS_I32_ADD = 0x6a,
WASM_INS_I32_SUB = 0x6b,
WASM_INS_I32_MUL = 0x6c,
WASM_INS_I32_DIV_S = 0x6d,
WASM_INS_I32_DIV_U = 0x6e,
WASM_INS_I32_REM_S = 0x6f,
WASM_INS_I32_REM_U = 0x70,
WASM_INS_I32_AND = 0x71,
WASM_INS_I32_OR = 0x72,
WASM_INS_I32_XOR = 0x73,
WASM_INS_I32_SHL = 0x74,
WASM_INS_I32_SHR_S = 0x75,
WASM_INS_I32_SHR_U = 0x76,
WASM_INS_I32_ROTL = 0x77,
WASM_INS_I32_ROTR = 0x78,
WASM_INS_I64_CLZ = 0x79,
WASM_INS_I64_CTZ = 0x7a,
WASM_INS_I64_POPCNT = 0x7b,
WASM_INS_I64_ADD = 0x7c,
WASM_INS_I64_SUB = 0x7d,
WASM_INS_I64_MUL = 0x7e,
WASM_INS_I64_DIV_S = 0x7f,
WASM_INS_I64_DIV_U = 0x80,
WASM_INS_I64_REM_S = 0x81,
WASM_INS_I64_REM_U = 0x82,
WASM_INS_I64_AND = 0x83,
WASM_INS_I64_OR = 0x84,
WASM_INS_I64_XOR = 0x85,
WASM_INS_I64_SHL = 0x86,
WASM_INS_I64_SHR_S = 0x87,
WASM_INS_I64_SHR_U = 0x88,
WASM_INS_I64_ROTL = 0x89,
WASM_INS_I64_ROTR = 0x8a,
WASM_INS_F32_ABS = 0x8b,
WASM_INS_F32_NEG = 0x8c,
WASM_INS_F32_CEIL = 0x8d,
WASM_INS_F32_FLOOR = 0x8e,
WASM_INS_F32_TRUNC = 0x8f,
WASM_INS_F32_NEAREST = 0x90,
WASM_INS_F32_SQRT = 0x91,
WASM_INS_F32_ADD = 0x92,
WASM_INS_F32_SUB = 0x93,
WASM_INS_F32_MUL = 0x94,
WASM_INS_F32_DIV = 0x95,
WASM_INS_F32_MIN = 0x96,
WASM_INS_F32_MAX = 0x97,
WASM_INS_F32_COPYSIGN = 0x98,
WASM_INS_F64_ABS = 0x99,
WASM_INS_F64_NEG = 0x9a,
WASM_INS_F64_CEIL = 0x9b,
WASM_INS_F64_FLOOR = 0x9c,
WASM_INS_F64_TRUNC = 0x9d,
WASM_INS_F64_NEAREST = 0x9e,
WASM_INS_F64_SQRT = 0x9f,
WASM_INS_F64_ADD = 0xa0,
WASM_INS_F64_SUB = 0xa1,
WASM_INS_F64_MUL = 0xa2,
WASM_INS_F64_DIV = 0xa3,
WASM_INS_F64_MIN = 0xa4,
WASM_INS_F64_MAX = 0xa5,
WASM_INS_F64_COPYSIGN = 0xa6,
WASM_INS_I32_WARP_I64 = 0xa7,
WASP_INS_I32_TRUNC_S_F32 = 0xa8,
WASM_INS_I32_TRUNC_U_F32 = 0xa9,
WASM_INS_I32_TRUNC_S_F64 = 0xaa,
WASM_INS_I32_TRUNC_U_F64 = 0xab,
WASM_INS_I64_EXTEND_S_I32 = 0xac,
WASM_INS_I64_EXTEND_U_I32 = 0xad,
WASM_INS_I64_TRUNC_S_F32 = 0xae,
WASM_INS_I64_TRUNC_U_F32 = 0xaf,
WASM_INS_I64_TRUNC_S_F64 = 0xb0,
WASM_INS_I64_TRUNC_U_F64 = 0xb1,
WASM_INS_F32_CONVERT_S_I32 = 0xb2,
WASM_INS_F32_CONVERT_U_I32 = 0xb3,
WASM_INS_F32_CONVERT_S_I64 = 0xb4,
WASM_INS_F32_CONVERT_U_I64 = 0xb5,
WASM_INS_F32_DEMOTE_F64 = 0xb6,
WASM_INS_F64_CONVERT_S_I32 = 0xb7,
WASM_INS_F64_CONVERT_U_I32 = 0xb8,
WASM_INS_F64_CONVERT_S_I64 = 0xb9,
WASM_INS_F64_CONVERT_U_I64 = 0xba,
WASM_INS_F64_PROMOTE_F32 = 0xbb,
WASM_INS_I32_REINTERPRET_F32 = 0xbc,
WASM_INS_I64_REINTERPRET_F64 = 0xbd,
WASM_INS_F32_REINTERPRET_I32 = 0xbe,
WASM_INS_F64_REINTERPRET_I64 = 0xbf,
WASM_INS_INVALID = 512,
WASM_INS_ENDING,
} wasm_insn;
/// Group of WASM instructions
typedef enum wasm_insn_group {
WASM_GRP_INVALID = 0, ///< = CS_GRP_INVALID
WASM_GRP_NUMBERIC = 8,
WASM_GRP_PARAMETRIC,
WASM_GRP_VARIABLE,
WASM_GRP_MEMORY,
WASM_GRP_CONTROL,
WASM_GRP_ENDING, ///< <-- mark the end of the list of groups
} wasm_insn_group;
#ifdef __cplusplus
}
#endif
#endif
external/capstone/include/capstone/x86.h
Vendored
+1988
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File diff suppressed because it is too large Load Diff
external/capstone/include/capstone/xcore.h
Vendored
+236
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@@ -0,0 +1,236 @@
#ifndef CAPSTONE_XCORE_H
#define CAPSTONE_XCORE_H
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2014-2015 */
#ifdef __cplusplus
extern "C" {
#endif
#include "platform.h"
#include "cs_operand.h"
#ifdef _MSC_VER
#pragma warning(disable:4201)
#endif
/// Operand type for instruction's operands
typedef enum xcore_op_type {
XCORE_OP_INVALID = CS_OP_INVALID, ///< = CS_OP_INVALID (Uninitialized).
XCORE_OP_REG = CS_OP_REG, ///< = CS_OP_REG (Register operand).
XCORE_OP_IMM = CS_OP_IMM, ///< = CS_OP_IMM (Immediate operand).
XCORE_OP_MEM = CS_OP_MEM, ///< = CS_OP_MEM (Memory operand).
} xcore_op_type;
/// XCore registers
typedef enum xcore_reg {
XCORE_REG_INVALID = 0,
XCORE_REG_CP,
XCORE_REG_DP,
XCORE_REG_LR,
XCORE_REG_SP,
XCORE_REG_R0,
XCORE_REG_R1,
XCORE_REG_R2,
XCORE_REG_R3,
XCORE_REG_R4,
XCORE_REG_R5,
XCORE_REG_R6,
XCORE_REG_R7,
XCORE_REG_R8,
XCORE_REG_R9,
XCORE_REG_R10,
XCORE_REG_R11,
// pseudo registers
XCORE_REG_PC, ///< pc
// internal thread registers
// see The-XMOS-XS1-Architecture(X7879A).pdf
XCORE_REG_SCP, ///< save pc
XCORE_REG_SSR, //< save status
XCORE_REG_ET, //< exception type
XCORE_REG_ED, //< exception data
XCORE_REG_SED, //< save exception data
XCORE_REG_KEP, //< kernel entry pointer
XCORE_REG_KSP, //< kernel stack pointer
XCORE_REG_ID, //< thread ID
XCORE_REG_ENDING, // <-- mark the end of the list of registers
} xcore_reg;
/// Instruction's operand referring to memory
/// This is associated with XCORE_OP_MEM operand type above
typedef struct xcore_op_mem {
uint8_t base; ///< base register, can be safely interpreted as
///< a value of type `xcore_reg`, but it is only
///< one byte wide
uint8_t index; ///< index register, same conditions apply here
int32_t disp; ///< displacement/offset value
int direct; ///< +1: forward, -1: backward
} xcore_op_mem;
/// Instruction operand
typedef struct cs_xcore_op {
xcore_op_type type; ///< operand type
union {
xcore_reg reg; ///< register value for REG operand
int32_t imm; ///< immediate value for IMM operand
xcore_op_mem mem; ///< base/disp value for MEM operand
};
} cs_xcore_op;
/// Instruction structure
typedef struct cs_xcore {
/// Number of operands of this instruction,
/// or 0 when instruction has no operand.
uint8_t op_count;
cs_xcore_op operands[8]; ///< operands for this instruction.
} cs_xcore;
/// XCore instruction
typedef enum xcore_insn {
XCORE_INS_INVALID = 0,
XCORE_INS_ADD,
XCORE_INS_ANDNOT,
XCORE_INS_AND,
XCORE_INS_ASHR,
XCORE_INS_BAU,
XCORE_INS_BITREV,
XCORE_INS_BLA,
XCORE_INS_BLAT,
XCORE_INS_BL,
XCORE_INS_BF,
XCORE_INS_BT,
XCORE_INS_BU,
XCORE_INS_BRU,
XCORE_INS_BYTEREV,
XCORE_INS_CHKCT,
XCORE_INS_CLRE,
XCORE_INS_CLRPT,
XCORE_INS_CLRSR,
XCORE_INS_CLZ,
XCORE_INS_CRC8,
XCORE_INS_CRC32,
XCORE_INS_DCALL,
XCORE_INS_DENTSP,
XCORE_INS_DGETREG,
XCORE_INS_DIVS,
XCORE_INS_DIVU,
XCORE_INS_DRESTSP,
XCORE_INS_DRET,
XCORE_INS_ECALLF,
XCORE_INS_ECALLT,
XCORE_INS_EDU,
XCORE_INS_EEF,
XCORE_INS_EET,
XCORE_INS_EEU,
XCORE_INS_ENDIN,
XCORE_INS_ENTSP,
XCORE_INS_EQ,
XCORE_INS_EXTDP,
XCORE_INS_EXTSP,
XCORE_INS_FREER,
XCORE_INS_FREET,
XCORE_INS_GETD,
XCORE_INS_GET,
XCORE_INS_GETN,
XCORE_INS_GETR,
XCORE_INS_GETSR,
XCORE_INS_GETST,
XCORE_INS_GETTS,
XCORE_INS_INCT,
XCORE_INS_INIT,
XCORE_INS_INPW,
XCORE_INS_INSHR,
XCORE_INS_INT,
XCORE_INS_IN,
XCORE_INS_KCALL,
XCORE_INS_KENTSP,
XCORE_INS_KRESTSP,
XCORE_INS_KRET,
XCORE_INS_LADD,
XCORE_INS_LD16S,
XCORE_INS_LD8U,
XCORE_INS_LDA16,
XCORE_INS_LDAP,
XCORE_INS_LDAW,
XCORE_INS_LDC,
XCORE_INS_LDW,
XCORE_INS_LDIVU,
XCORE_INS_LMUL,
XCORE_INS_LSS,
XCORE_INS_LSUB,
XCORE_INS_LSU,
XCORE_INS_MACCS,
XCORE_INS_MACCU,
XCORE_INS_MJOIN,
XCORE_INS_MKMSK,
XCORE_INS_MSYNC,
XCORE_INS_MUL,
XCORE_INS_NEG,
XCORE_INS_NOT,
XCORE_INS_OR,
XCORE_INS_OUTCT,
XCORE_INS_OUTPW,
XCORE_INS_OUTSHR,
XCORE_INS_OUTT,
XCORE_INS_OUT,
XCORE_INS_PEEK,
XCORE_INS_REMS,
XCORE_INS_REMU,
XCORE_INS_RETSP,
XCORE_INS_SETCLK,
XCORE_INS_SET,
XCORE_INS_SETC,
XCORE_INS_SETD,
XCORE_INS_SETEV,
XCORE_INS_SETN,
XCORE_INS_SETPSC,
XCORE_INS_SETPT,
XCORE_INS_SETRDY,
XCORE_INS_SETSR,
XCORE_INS_SETTW,
XCORE_INS_SETV,
XCORE_INS_SEXT,
XCORE_INS_SHL,
XCORE_INS_SHR,
XCORE_INS_SSYNC,
XCORE_INS_ST16,
XCORE_INS_ST8,
XCORE_INS_STW,
XCORE_INS_SUB,
XCORE_INS_SYNCR,
XCORE_INS_TESTCT,
XCORE_INS_TESTLCL,
XCORE_INS_TESTWCT,
XCORE_INS_TSETMR,
XCORE_INS_START,
XCORE_INS_WAITEF,
XCORE_INS_WAITET,
XCORE_INS_WAITEU,
XCORE_INS_XOR,
XCORE_INS_ZEXT,
XCORE_INS_ENDING, // <-- mark the end of the list of instructions
} xcore_insn;
/// Group of XCore instructions
typedef enum xcore_insn_group {
XCORE_GRP_INVALID = 0, ///< = CS_GRP_INVALID
// Generic groups
// all jump instructions (conditional+direct+indirect jumps)
XCORE_GRP_JUMP, ///< = CS_GRP_JUMP
XCORE_GRP_ENDING, // <-- mark the end of the list of groups
} xcore_insn_group;
#ifdef __cplusplus
}
#endif
#endif
external/capstone/include/capstone/xtensa.h
Vendored
+1730
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File diff suppressed because it is too large Load Diff
external/capstone/include/platform.h
Vendored
+110
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@@ -0,0 +1,110 @@
/* Capstone Disassembly Engine */
/* By Axel Souchet & Nguyen Anh Quynh, 2014 */
#ifndef CAPSTONE_PLATFORM_H
#define CAPSTONE_PLATFORM_H
// handle C99 issue (for pre-2013 VisualStudio)
#if !defined(__CYGWIN__) && !defined(__MINGW32__) && !defined(__MINGW64__) && (defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64))
// MSVC
// stdbool.h
#if (_MSC_VER < 1800) || defined(_KERNEL_MODE)
// this system does not have stdbool.h
#ifndef __cplusplus
typedef unsigned char bool;
#define false 0
#define true 1
#endif
#else
// VisualStudio 2013+ -> C99 is supported
#include <stdbool.h>
#endif
#else
// not MSVC -> C99 is supported
#include <stdbool.h>
#endif
// handle C99 issue (for pre-2013 VisualStudio)
#if defined(CAPSTONE_HAS_OSXKERNEL) || (defined(_MSC_VER) && (_MSC_VER <= 1700 || defined(_KERNEL_MODE)))
// this system does not have inttypes.h
#if defined(_MSC_VER) && (_MSC_VER < 1600 || defined(_KERNEL_MODE))
// this system does not have stdint.h
typedef signed char int8_t;
typedef signed short int16_t;
typedef signed int int32_t;
typedef unsigned char uint8_t;
typedef unsigned short uint16_t;
typedef unsigned int uint32_t;
typedef signed long long int64_t;
typedef unsigned long long uint64_t;
#define INT8_MIN (-127i8 - 1)
#define INT16_MIN (-32767i16 - 1)
#define INT32_MIN (-2147483647i32 - 1)
#define INT64_MIN (-9223372036854775807i64 - 1)
#define INT8_MAX 127i8
#define INT16_MAX 32767i16
#define INT32_MAX 2147483647i32
#define INT64_MAX 9223372036854775807i64
#define UINT8_MAX 0xffui8
#define UINT16_MAX 0xffffui16
#define UINT32_MAX 0xffffffffui32
#define UINT64_MAX 0xffffffffffffffffui64
#endif
#define __PRI_8_LENGTH_MODIFIER__ "hh"
#define __PRI_64_LENGTH_MODIFIER__ "ll"
#define PRId8 __PRI_8_LENGTH_MODIFIER__ "d"
#define PRIi8 __PRI_8_LENGTH_MODIFIER__ "i"
#define PRIo8 __PRI_8_LENGTH_MODIFIER__ "o"
#define PRIu8 __PRI_8_LENGTH_MODIFIER__ "u"
#define PRIx8 __PRI_8_LENGTH_MODIFIER__ "x"
#define PRIX8 __PRI_8_LENGTH_MODIFIER__ "X"
#define PRId16 "hd"
#define PRIi16 "hi"
#define PRIo16 "ho"
#define PRIu16 "hu"
#define PRIx16 "hx"
#define PRIX16 "hX"
#if defined(_MSC_VER) && _MSC_VER <= 1700
#define PRId32 "ld"
#define PRIi32 "li"
#define PRIo32 "lo"
#define PRIu32 "lu"
#define PRIx32 "lx"
#define PRIX32 "lX"
#else // OSX
#define PRId32 "d"
#define PRIi32 "i"
#define PRIo32 "o"
#define PRIu32 "u"
#define PRIx32 "x"
#define PRIX32 "X"
#endif
#if defined(_MSC_VER) && _MSC_VER <= 1700
// redefine functions from inttypes.h used in cstool
#define strtoull _strtoui64
#endif
#define PRId64 __PRI_64_LENGTH_MODIFIER__ "d"
#define PRIi64 __PRI_64_LENGTH_MODIFIER__ "i"
#define PRIo64 __PRI_64_LENGTH_MODIFIER__ "o"
#define PRIu64 __PRI_64_LENGTH_MODIFIER__ "u"
#define PRIx64 __PRI_64_LENGTH_MODIFIER__ "x"
#define PRIX64 __PRI_64_LENGTH_MODIFIER__ "X"
#else
// this system has inttypes.h by default
#include <inttypes.h>
#endif
#endif
external/capstone/include/windowsce/intrin.h
Vendored
+12
View File
@@ -0,0 +1,12 @@
#if defined(_MSC_VER) && defined(_WIN32_WCE) && (_WIN32_WCE < 0x800) && !defined(__INTRIN_H_) && !defined(_INTRIN)
#define _STDINT
#ifdef _M_ARM
#include <armintr.h>
#if (_WIN32_WCE >= 0x700) && defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__)
#include <arm_neon.h>
#endif
#endif // _M_ARM
#endif
external/capstone/include/windowsce/stdint.h
Vendored
+133
View File
@@ -0,0 +1,133 @@
#if defined(_MSC_VER) && defined(_WIN32_WCE) && (_WIN32_WCE < 0x800) && !defined(_STDINT_H_) && !defined(_STDINT)
#define _STDINT
typedef __int8
int8_t,
int_least8_t;
typedef __int16
int16_t,
int_least16_t;
typedef __int32
int32_t,
int_least32_t,
int_fast8_t,
int_fast16_t,
int_fast32_t;
typedef __int64
int64_t,
intmax_t,
int_least64_t,
int_fast64_t;
typedef unsigned __int8
uint8_t,
uint_least8_t;
typedef unsigned __int16
uint16_t,
uint_least16_t;
typedef unsigned __int32
uint32_t,
uint_least32_t,
uint_fast8_t,
uint_fast16_t,
uint_fast32_t;
typedef unsigned __int64
uint64_t,
uintmax_t,
uint_least64_t,
uint_fast64_t;
#ifndef _INTPTR_T_DEFINED
#define _INTPTR_T_DEFINED
typedef __int32 intptr_t;
#endif
#ifndef _UINTPTR_T_DEFINED
#define _UINTPTR_T_DEFINED
typedef unsigned __int32 uintptr_t;
#endif
#define INT8_MIN (-127i8 - 1)
#define INT16_MIN (-32767i16 - 1)
#define INT32_MIN (-2147483647i32 - 1)
#define INT64_MIN (-9223372036854775807i64 - 1)
#define INT8_MAX 127i8
#define INT16_MAX 32767i16
#define INT32_MAX 2147483647i32
#define INT64_MAX 9223372036854775807i64
#define UINT8_MAX 0xffui8
#define UINT16_MAX 0xffffui16
#define UINT32_MAX 0xffffffffui32
#define UINT64_MAX 0xffffffffffffffffui64
#define INT_LEAST8_MIN INT8_MIN
#define INT_LEAST16_MIN INT16_MIN
#define INT_LEAST32_MIN INT32_MIN
#define INT_LEAST64_MIN INT64_MIN
#define INT_LEAST8_MAX INT8_MAX
#define INT_LEAST16_MAX INT16_MAX
#define INT_LEAST32_MAX INT32_MAX
#define INT_LEAST64_MAX INT64_MAX
#define UINT_LEAST8_MAX UINT8_MAX
#define UINT_LEAST16_MAX UINT16_MAX
#define UINT_LEAST32_MAX UINT32_MAX
#define UINT_LEAST64_MAX UINT64_MAX
#define INT_FAST8_MIN INT8_MIN
#define INT_FAST16_MIN INT32_MIN
#define INT_FAST32_MIN INT32_MIN
#define INT_FAST64_MIN INT64_MIN
#define INT_FAST8_MAX INT8_MAX
#define INT_FAST16_MAX INT32_MAX
#define INT_FAST32_MAX INT32_MAX
#define INT_FAST64_MAX INT64_MAX
#define UINT_FAST8_MAX UINT8_MAX
#define UINT_FAST16_MAX UINT32_MAX
#define UINT_FAST32_MAX UINT32_MAX
#define UINT_FAST64_MAX UINT64_MAX
#define INTPTR_MIN INT32_MIN
#define INTPTR_MAX INT32_MAX
#define UINTPTR_MAX UINT32_MAX
#define INTMAX_MIN INT64_MIN
#define INTMAX_MAX INT64_MAX
#define UINTMAX_MAX UINT64_MAX
#define PTRDIFF_MIN INTPTR_MIN
#define PTRDIFF_MAX INTPTR_MAX
#ifndef SIZE_MAX
#define SIZE_MAX UINTPTR_MAX
#endif
#define SIG_ATOMIC_MIN INT32_MIN
#define SIG_ATOMIC_MAX INT32_MAX
#define WCHAR_MIN 0x0000
#define WCHAR_MAX 0xffff
#define WINT_MIN 0x0000
#define WINT_MAX 0xffff
#define INT8_C(x) (x)
#define INT16_C(x) (x)
#define INT32_C(x) (x)
#define INT64_C(x) (x ## LL)
#define UINT8_C(x) (x)
#define UINT16_C(x) (x)
#define UINT32_C(x) (x ## U)
#define UINT64_C(x) (x ## ULL)
#define INTMAX_C(x) INT64_C(x)
#define UINTMAX_C(x) UINT64_C(x)
#endif