more instructions and formatter
This commit is contained in:
SimoneN64
@@ -67,7 +67,7 @@ void Core::Run(float volumeL, float volumeR) {
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InterruptRaise(mmio.mi, regs, Interrupt::VI);
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}
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for(; cycles < mem.mmio.vi.cyclesPerHalfline; cycles++, frameCycles++) {
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for(; cycles < mem.mmio.vi.cyclesPerHalfline;) {
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u32 taken = cpu->Step();
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taken += PopStalledCycles();
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static u32 cpuSteps = 0;
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@@ -33,51 +33,56 @@ void JIT::CheckCompareInterrupt() {
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Fn JIT::Recompile() {
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bool stable = true;
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cycles = 0;
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prologue();
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mov(rbp, u64(this));
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mov(rdi, u64(this) + THIS_OFFSET(regs));
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//prologue();
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//mov(rbp, u64(this));
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//mov(rdi, u64(this) + THIS_OFFSET(regs));
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u64 pc = regs.pc;
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while(stable) {
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cycles++;
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CheckCompareInterrupt();
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mov(rax, REG(byte, delaySlot));
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mov(REG(byte, prevDelaySlot), rax);
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mov(REG(byte, delaySlot), 0);
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// mov(rax, REG(byte, delaySlot));
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// mov(REG(byte, prevDelaySlot), rax);
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// mov(REG(byte, delaySlot), 0);
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u32 paddr = 0;
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if (!MapVAddr(regs, LOAD, regs.pc, paddr)) {
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mov(rsi, regs.pc);
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emitCall(HandleTLBException);
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mov(rsi, u64(GetTLBExceptionCode(regs.cop0.tlbError, LOAD)));
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CodeGenerator::xor_(rdx, rdx);
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CodeGenerator::xor_(rcx, rcx);
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emitCall(FireException);
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goto _epilogue;
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if (!MapVAddr(regs, LOAD, pc, paddr)) {
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//mov(rsi, regs.pc);
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//emitCall(HandleTLBException);
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//mov(rsi, u64(GetTLBExceptionCode(regs.cop0.tlbError, LOAD)));
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//CodeGenerator::xor_(rdx, rdx);
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//CodeGenerator::xor_(rcx, rcx);
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//emitCall(FireException);
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//goto _epilogue;
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}
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pc += 4;
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u32 instr = mem.Read<u32>(regs, paddr);
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stable = isStable(instr);
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Emit(instr);
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if (ShouldServiceInterrupt()) {
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mov(rsi, u64(ExceptionCode::Interrupt));
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CodeGenerator::xor_(rdx, rdx);
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CodeGenerator::xor_(rcx, rcx);
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push(rax);
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call(FireException);
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goto _epilogue;
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//mov(rsi, u64(ExceptionCode::Interrupt));
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//CodeGenerator::xor_(rdx, rdx);
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//CodeGenerator::xor_(rcx, rcx);
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//push(rax);
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//call(FireException);
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//goto _epilogue;
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}
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mov(rax, REG(qword, pc));
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mov(REG(qword, oldPC), rax);
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mov(rax, REG(qword, nextPC));
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mov(REG(qword, pc), rax);
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CodeGenerator::add(REG(qword, nextPC), 4);
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//mov(rax, REG(qword, pc));
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//mov(REG(qword, oldPC), rax);
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//mov(rax, REG(qword, nextPC));
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//mov(REG(qword, pc), rax);
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//CodeGenerator::add(REG(qword, nextPC), 4);
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}
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_epilogue:
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epilogue();
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ready();
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return getCode<Fn>();
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//epilogue();
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//ready();
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//return getCode<Fn>();
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ir.optimize();
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exit(1);
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return nullptr;
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}
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int JIT::Step() {
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@@ -90,6 +95,7 @@ int JIT::Step() {
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blocks[BLOCKCACHE_OUTER_INDEX(regs.pc)][BLOCKCACHE_INNER_INDEX(regs.pc)] = Recompile();
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}
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return blocks[BLOCKCACHE_OUTER_INDEX(regs.pc)][BLOCKCACHE_INNER_INDEX(regs.pc)]();
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//return blocks[BLOCKCACHE_OUTER_INDEX(regs.pc)][BLOCKCACHE_INNER_INDEX(regs.pc)]();
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return 1;
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}
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}
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@@ -137,6 +137,7 @@ private:
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void addiu(u32);
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void andi(u32);
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void and_(u32);
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Entry branch(u32);
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void bltz(u32);
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void bgez(u32);
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void bltzl(u32);
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@@ -1,14 +1,207 @@
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#include <IR.hpp>
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#include <fmt/format.h>
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namespace n64 {
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template <> struct fmt::formatter<Entry> : formatter<string_view> {
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auto format(Entry e, format_context& ctx) const {
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std::string op = "Unknown";
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switch (e.op) {
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case Entry::MOV:
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op = "MOV";
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break;
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case Entry::ADD:
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op = "ADD";
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break;
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case Entry::SUB:
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op = "SUB";
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break;
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case Entry::UMUL:
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op = "UMUL";
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break;
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case Entry::SMUL:
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op = "SMUL";
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break;
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case Entry::DIV:
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op = "DIV";
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break;
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case Entry::AND:
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op = "AND";
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break;
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case Entry::NOR:
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op = "NOR";
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break;
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case Entry::XOR:
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op = "XOR";
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break;
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case Entry::OR:
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op = "OR";
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break;
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case Entry::SRL:
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op = "SRL";
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break;
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case Entry::SLL:
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op = "SLL";
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break;
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case Entry::SRA:
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op = "SRA";
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break;
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case Entry::LOADS8:
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op = "LOADS8";
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break;
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case Entry::LOADS8_SHIFT:
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op = "LOADS8_SHIFT";
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break;
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case Entry::STORE8:
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op = "STORE8";
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break;
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case Entry::STORE8_SHIFT:
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op = "STORE8_SHIFT";
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break;
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case Entry::LOADS16:
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op = "LOADS16";
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break;
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case Entry::LOADS16_SHIFT:
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op = "LOADS16_SHIFT";
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break;
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case Entry::STORE16:
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op = "STORE16";
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break;
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case Entry::STORE16_SHIFT:
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op = "STORE16_SHIFT";
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break;
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case Entry::LOADS32:
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op = "LOADS32";
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break;
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case Entry::LOADS32_SHIFT:
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op = "LOADS32_SHIFT";
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break;
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case Entry::STORE32:
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op = "STORE32";
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break;
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case Entry::STORE32_SHIFT:
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op = "STORE32_SHIFT";
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break;
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case Entry::LOADS64:
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op = "LOADS64";
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break;
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case Entry::LOADS64_SHIFT:
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op = "LOADS64_SHIFT";
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break;
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case Entry::STORE64:
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op = "STORE64";
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break;
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case Entry::STORE64_SHIFT:
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op = "STORE64_SHIFT";
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break;
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case Entry::LOADU8:
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op = "LOADU8";
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break;
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case Entry::LOADU8_SHIFT:
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op = "LOADU8_SHIFT";
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break;
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case Entry::LOADU16:
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op = "LOADU16";
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break;
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case Entry::LOADU16_SHIFT:
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op = "LOADU16_SHIFT";
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break;
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case Entry::LOADU32:
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op = "LOADU32";
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break;
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case Entry::LOADU32_SHIFT:
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op = "LOADU32_SHIFT";
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break;
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case Entry::LOADU64:
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op = "LOADU64";
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break;
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case Entry::LOADU64_SHIFT:
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op = "LOADU64_SHIFT";
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break;
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case Entry::BRANCH:
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op = "BRANCH";
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break;
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case Entry::JUMP:
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op = "JUMP";
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break;
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}
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bool put_comma = false;
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op += " ";
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if (e.dst.isReg()) {
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if (e.dst.index_or_imm.has_value()) {
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if (e.dst.index_or_imm.value() == 0) {
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op = "NOP";
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return formatter<string_view>::format(op, ctx);
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} else {
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std::string dst = fmt::format("R{}", e.dst.index_or_imm.value());
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op += dst;
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put_comma = true;
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}
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}
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} else {
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if(e.dst.type != Entry::Operand::NONE) {
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std::string dst = fmt::format("0x{:0X}", e.dst.index_or_imm.value());
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op += dst;
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put_comma = true;
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}
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}
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if (e.op1.isReg()) {
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if (e.op1.index_or_imm.has_value()) {
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std::string op1 = fmt::format("R{}", e.op1.index_or_imm.value());
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if(put_comma) {
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op += ", ";
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}
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op += op1;
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put_comma = true;
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}
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} else {
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if (e.op1.index_or_imm.has_value()) {
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std::string op1 = fmt::format("0x{:0X}", e.op1.index_or_imm.value());
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if(put_comma) {
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op += ", ";
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}
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op += op1;
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put_comma = true;
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}
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}
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if (e.op2.isReg()) {
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if (e.op2.index_or_imm.has_value()) {
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std::string op2 = fmt::format("R{}", e.op2.index_or_imm.value());
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if(put_comma) {
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op += ", ";
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}
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op += op2;
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put_comma = true;
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}
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} else {
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if (e.op2.index_or_imm.has_value()) {
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std::string op2 = fmt::format("0x{:0X}", e.op2.index_or_imm.value());
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if(put_comma) {
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op += ", ";
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}
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op += op2;
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put_comma = true;
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}
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}
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op += '\n';
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return formatter<string_view>::format(op, ctx);
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}
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};
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Entry::Entry(Opcode op, Operand dst, Operand op1, Operand op2)
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: op(op), dst(dst), op1(op1), op2(op2) {}
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Entry::Entry(Opcode op, Operand op1, Operand op2)
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: op(op), op1(op1), op2(op2) {}
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Entry::Entry(Opcode op, Operand op1, std::optional<BranchCond> bc, Operand op2)
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: op(op), op1(op1), branchCond(bc), op2(op2) {}
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Entry::Entry(Opcode op, Operand bDest, Operand op1, std::optional<BranchCond> bc, Operand op2)
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: op(op), bDest(bDest), op1(op1), branchCond(bc), op2(op2) {}
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Entry::Entry(Opcode op, Operand bDest)
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: op(op), bDest(bDest) {}
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Entry::Entry(Opcode op, Operand dst, Operand op1, Operand op2, Shift s)
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: op(op), dst(dst), op1(op1), op2(op2), shift(s) {}
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@@ -17,6 +210,12 @@ void IR::push(const Entry& e) {
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code.push_back(e);
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}
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void IR::optimize() {
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for(auto e : code) {
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fmt::print("{}", e);
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}
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}
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auto IR::begin() {
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return code.begin();
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}
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@@ -34,25 +34,36 @@ struct Entry {
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NONE, REG_F64, REG_F32, IMM_F64, IMM_F32,
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REG_S64, REG_S32, REG_U64, REG_U32, REG_U5, IMM_S16,
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IMM_S32, IMM_S64, IMM_U16, IMM_U32, IMM_U64, IMM_U5,
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MEM_U8, MEM_U16, MEM_U32, MEM_U64
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} type;
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MEM_U8, MEM_U16, MEM_U32, MEM_U64, PC64, NEXTPC64,
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LO, HI
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} type = NONE;
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bool isReg() {
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return type == REG_S64 || type == REG_F32 || type == REG_F64 || type == REG_S32
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|| type == REG_U64 || type == REG_U32 || type == REG_U5;
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}
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std::optional<u64> index_or_imm = std::nullopt;
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Operand() = default;
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Operand(Type t, std::optional <u64> imm = std::nullopt)
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: type(t), index_or_imm(imm) {}
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} dst = Operand::NONE, op1 = Operand::NONE, op2 = Operand::NONE;
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} dst, op1, op2;
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[[nodiscard]] const Operand& GetDst() const { return dst; }
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enum BranchCond {
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EQ, NE, LT, GT, LE, GE
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AL, EQ, NE, LT, GT, LE, GE
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};
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std::optional<BranchCond> branchCond = std::nullopt;
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std::optional<Shift> shift = std::nullopt;
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Operand bDest = Operand::NONE;
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Entry(Opcode op, Operand dst, Operand op1, Operand op2);
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Entry(Opcode op, Operand op1, Operand op2);
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Entry(Opcode op, Operand op1, std::optional<BranchCond> bc, Operand op2);
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Entry(Opcode op, Operand bDest, Operand op1, std::optional<BranchCond> bc, Operand op2);
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Entry(Opcode op, Operand bDest);
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Entry(Opcode op, Operand dst, Operand op1, Operand op2, Shift s);
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};
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@@ -60,6 +71,7 @@ struct IR {
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void push(const Entry&);
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auto begin();
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auto end();
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void optimize();
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private:
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std::vector<Entry> code{};
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};
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@@ -37,125 +37,149 @@ void JIT::dadd(u32 instr) {
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ir.push(e);
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}
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Entry JIT::branch(u32 instr) {
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auto dst = Entry::Operand{ Entry::Operand::IMM_S64, u64(s64(s16(instr))) << 2 };
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auto pc = Entry::Operand{Entry::Operand::PC64};
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Entry add_(Entry::ADD, dst, dst, pc);
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ir.push(add_);
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return add_;
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}
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void JIT::bltz(u32 instr) {
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auto dst = branch(instr);
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auto op1 = Entry::Operand{ Entry::Operand::REG_S64, u8(RS(instr)) };
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auto op2 = Entry::Operand{ Entry::Operand::IMM_U64, 0 };
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Entry e(Entry::BRANCH, op1, Entry::BranchCond::LT, op2);
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Entry e(Entry::BRANCH, dst.GetDst(), op1, Entry::BranchCond::LT, op2);
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ir.push(e);
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}
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void JIT::bgez(u32 instr) {
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auto dst = branch(instr);
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auto op1 = Entry::Operand{ Entry::Operand::REG_S64, u8(RS(instr)) };
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auto op2 = Entry::Operand{ Entry::Operand::IMM_U64, 0 };
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Entry e(Entry::BRANCH, op1, Entry::BranchCond::GE, op2);
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Entry e(Entry::BRANCH, dst.GetDst(), op1, Entry::BranchCond::GE, op2);
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ir.push(e);
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}
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void JIT::bltzl(u32 instr) {
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auto dst = branch(instr);
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auto op1 = Entry::Operand{ Entry::Operand::REG_S64, u8(RS(instr)) };
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auto op2 = Entry::Operand{ Entry::Operand::IMM_U64, 0 };
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auto opc = Entry::Opcode(u16(Entry::BRANCH) | Entry::LIKELY);
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Entry e(opc, op1, Entry::BranchCond::LT, op2);
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Entry e(opc, dst.GetDst(), op1, Entry::BranchCond::LT, op2);
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ir.push(e);
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}
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void JIT::bgezl(u32 instr) {
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auto dst = branch(instr);
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auto op1 = Entry::Operand{ Entry::Operand::REG_S64, u8(RS(instr)) };
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auto op2 = Entry::Operand{ Entry::Operand::IMM_U64, 0 };
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auto opc = Entry::Opcode(u16(Entry::BRANCH) | Entry::LIKELY);
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Entry e(opc, op1, Entry::BranchCond::GE, op2);
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Entry e(opc, dst.GetDst(), op1, Entry::BranchCond::GE, op2);
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ir.push(e);
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}
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void JIT::bltzal(u32 instr) {
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auto dst = branch(instr);
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auto op1 = Entry::Operand{ Entry::Operand::REG_S64, u8(RS(instr)) };
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auto op2 = Entry::Operand{ Entry::Operand::IMM_U64, 0 };
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auto opc = Entry::Opcode(u16(Entry::BRANCH) | Entry::LINK);
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Entry e(opc, op1, Entry::BranchCond::LT, op2);
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Entry e(opc, dst.GetDst(), op1, Entry::BranchCond::LT, op2);
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ir.push(e);
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}
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void JIT::bgezal(u32 instr) {
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auto dst = branch(instr);
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auto op1 = Entry::Operand{ Entry::Operand::REG_S64, u8(RS(instr)) };
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auto op2 = Entry::Operand{ Entry::Operand::IMM_U64, 0 };
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auto opc = Entry::Opcode(u16(Entry::BRANCH) | Entry::LINK);
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Entry e(opc, op1, Entry::BranchCond::GE, op2);
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Entry e(opc, dst.GetDst(), op1, Entry::BranchCond::GE, op2);
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ir.push(e);
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}
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void JIT::bltzall(u32 instr) {
|
||||
auto dst = branch(instr);
|
||||
auto op1 = Entry::Operand{ Entry::Operand::REG_S64, u8(RS(instr)) };
|
||||
auto op2 = Entry::Operand{ Entry::Operand::IMM_U64, 0 };
|
||||
auto opc = Entry::Opcode(u16(Entry::BRANCH) | Entry::LINK | Entry::LIKELY);
|
||||
Entry e(opc, op1, Entry::BranchCond::LT, op2);
|
||||
Entry e(opc, dst.GetDst(), op1, Entry::BranchCond::LT, op2);
|
||||
ir.push(e);
|
||||
}
|
||||
|
||||
void JIT::bgezall(u32 instr) {
|
||||
auto dst = branch(instr);
|
||||
auto op1 = Entry::Operand{ Entry::Operand::REG_S64, u8(RS(instr)) };
|
||||
auto op2 = Entry::Operand{ Entry::Operand::IMM_U64, 0 };
|
||||
auto opc = Entry::Opcode(u16(Entry::BRANCH) | Entry::LINK | Entry::LIKELY);
|
||||
Entry e(opc, op1, Entry::BranchCond::GE, op2);
|
||||
Entry e(opc, dst.GetDst(), op1, Entry::BranchCond::GE, op2);
|
||||
ir.push(e);
|
||||
}
|
||||
|
||||
void JIT::beq(u32 instr) {
|
||||
auto dst = branch(instr);
|
||||
auto op1 = Entry::Operand{ Entry::Operand::REG_S64, u8(RS(instr)) };
|
||||
auto op2 = Entry::Operand{ Entry::Operand::REG_S64, u8(RT(instr)) };
|
||||
Entry e(Entry::BRANCH, op1, Entry::BranchCond::EQ, op2);
|
||||
Entry e(Entry::BRANCH, dst.GetDst(), op1, Entry::BranchCond::EQ, op2);
|
||||
ir.push(e);
|
||||
}
|
||||
|
||||
void JIT::bne(u32 instr) {
|
||||
auto dst = branch(instr);
|
||||
auto op1 = Entry::Operand{ Entry::Operand::REG_S64, u8(RS(instr)) };
|
||||
auto op2 = Entry::Operand{ Entry::Operand::REG_S64, u8(RT(instr)) };
|
||||
Entry e(Entry::BRANCH, op1, Entry::BranchCond::NE, op2);
|
||||
Entry e(Entry::BRANCH, dst.GetDst(), op1, Entry::BranchCond::NE, op2);
|
||||
ir.push(e);
|
||||
}
|
||||
|
||||
void JIT::blez(u32 instr) {
|
||||
auto dst = branch(instr);
|
||||
auto op1 = Entry::Operand{ Entry::Operand::REG_S64, u8(RS(instr)) };
|
||||
auto op2 = Entry::Operand{ Entry::Operand::IMM_S64, 0 };
|
||||
Entry e(Entry::BRANCH, op1, Entry::BranchCond::LE, op2);
|
||||
Entry e(Entry::BRANCH, dst.GetDst(), op1, Entry::BranchCond::LE, op2);
|
||||
ir.push(e);
|
||||
}
|
||||
|
||||
void JIT::bgtz(u32 instr) {
|
||||
auto dst = branch(instr);
|
||||
auto op1 = Entry::Operand{ Entry::Operand::REG_S64, u8(RS(instr)) };
|
||||
auto op2 = Entry::Operand{ Entry::Operand::IMM_S64, 0 };
|
||||
Entry e(Entry::BRANCH, op1, Entry::BranchCond::GT, op2);
|
||||
Entry e(Entry::BRANCH, dst.GetDst(), op1, Entry::BranchCond::GT, op2);
|
||||
ir.push(e);
|
||||
}
|
||||
|
||||
void JIT::beql(u32 instr) {
|
||||
auto dst = branch(instr);
|
||||
auto op1 = Entry::Operand{ Entry::Operand::REG_S64, u8(RS(instr)) };
|
||||
auto op2 = Entry::Operand{ Entry::Operand::REG_S64, u8(RT(instr)) };
|
||||
auto opc = Entry::Opcode(u16(Entry::BRANCH) | Entry::LIKELY);
|
||||
Entry e(opc, op1, Entry::BranchCond::EQ, op2);
|
||||
Entry e(opc, dst.GetDst(), op1, Entry::BranchCond::EQ, op2);
|
||||
ir.push(e);
|
||||
}
|
||||
|
||||
void JIT::bnel(u32 instr) {
|
||||
auto dst = branch(instr);
|
||||
auto op1 = Entry::Operand{ Entry::Operand::REG_S64, u8(RS(instr)) };
|
||||
auto op2 = Entry::Operand{ Entry::Operand::REG_S64, u8(RT(instr)) };
|
||||
auto opc = Entry::Opcode(u16(Entry::BRANCH) | Entry::LIKELY);
|
||||
Entry e(opc, op1, Entry::BranchCond::NE, op2);
|
||||
Entry e(opc, dst.GetDst(), op1, Entry::BranchCond::NE, op2);
|
||||
ir.push(e);
|
||||
}
|
||||
|
||||
void JIT::blezl(u32 instr) {
|
||||
auto dst = branch(instr);
|
||||
auto op1 = Entry::Operand{ Entry::Operand::REG_S64, u8(RS(instr)) };
|
||||
auto op2 = Entry::Operand{ Entry::Operand::IMM_S64, 0 };
|
||||
auto opc = Entry::Opcode(u16(Entry::BRANCH) | Entry::LIKELY);
|
||||
Entry e(opc, op1, Entry::BranchCond::LE, op2);
|
||||
Entry e(opc, dst.GetDst(), op1, Entry::BranchCond::LE, op2);
|
||||
ir.push(e);
|
||||
}
|
||||
|
||||
void JIT::bgtzl(u32 instr) {
|
||||
auto dst = branch(instr);
|
||||
auto op1 = Entry::Operand{ Entry::Operand::REG_S64, u8(RS(instr)) };
|
||||
auto op2 = Entry::Operand{ Entry::Operand::IMM_S64, 0 };
|
||||
auto opc = Entry::Opcode(u16(Entry::BRANCH) | Entry::LIKELY);
|
||||
Entry e(opc, op1, Entry::BranchCond::GT, op2);
|
||||
Entry e(opc, dst.GetDst(), op1, Entry::BranchCond::GT, op2);
|
||||
ir.push(e);
|
||||
}
|
||||
|
||||
@@ -423,29 +447,32 @@ void JIT::nor(u32 instr) {
|
||||
}
|
||||
|
||||
void JIT::j(u32 instr) {
|
||||
s32 target = (instr & 0x3ffffff) << 2;
|
||||
s64 address = (regs.oldPC & ~0xfffffff) | target;
|
||||
|
||||
mov(byte[rdi + offsetof(Registers, delaySlot)], 1);
|
||||
mov(qword[rdi + offsetof(Registers, nextPC)], address);
|
||||
auto dst = Entry::Operand{Entry::Operand::IMM_S64};
|
||||
auto op1 = Entry::Operand{Entry::Operand::PC64};
|
||||
auto op2 = Entry::Operand{Entry::Operand::IMM_S64, ~0xfffffff};
|
||||
Entry and_(Entry::AND, dst, op1, op2);
|
||||
ir.push(and_);
|
||||
op2 = Entry::Operand{Entry::Operand::IMM_S64, (instr & 0x3ffffff) << 2};
|
||||
Entry or_(Entry::OR, dst, dst, op2);
|
||||
ir.push(or_);
|
||||
Entry e(Entry::BRANCH, or_.GetDst());
|
||||
}
|
||||
|
||||
void JIT::jal(u32 instr) {
|
||||
mov(rax, qword[rdi + offsetof(Registers, nextPC)]);
|
||||
mov(GPR(qword, 31), rax);
|
||||
Entry link(Entry::MOV,
|
||||
Entry::Operand{Entry::Operand::REG_S64, 31},
|
||||
Entry::Operand{Entry::Operand::NEXTPC64});
|
||||
ir.push(link);
|
||||
j(instr);
|
||||
}
|
||||
|
||||
void JIT::jalr(u32 instr) {
|
||||
mov(byte[rdi + offsetof(Registers, delaySlot)], 1);
|
||||
mov(rax, GPR(qword, RS(instr)));
|
||||
mov(qword[rdi + offsetof(Registers, nextPC)], rax);
|
||||
|
||||
if (RD(instr) != 0) [[likely]] {
|
||||
mov(rax, qword[rdi + offsetof(Registers, pc)]);
|
||||
CodeGenerator::add(rax, 4);
|
||||
mov(GPR(qword, RD(instr)), rax);
|
||||
}
|
||||
auto addr = Entry::Operand{Entry::Operand::REG_U64, RS(instr)};
|
||||
Entry e(Entry::BRANCH, addr);
|
||||
Entry link(Entry::MOV,
|
||||
Entry::Operand{Entry::Operand::REG_S64, RD(instr)},
|
||||
Entry::Operand{Entry::Operand::PC64});
|
||||
ir.push(link);
|
||||
}
|
||||
|
||||
void JIT::slti(u32 instr) {
|
||||
@@ -706,9 +733,8 @@ void JIT::dsra32(u32 instr) {
|
||||
}
|
||||
|
||||
void JIT::jr(u32 instr) {
|
||||
mov(rax, GPR(qword, RS(instr)));
|
||||
mov(REG(byte, delaySlot), 1);
|
||||
mov(REG(qword, nextPC), rax);
|
||||
auto addr = Entry::Operand{Entry::Operand::REG_U64, RS(instr)};
|
||||
Entry e(Entry::BRANCH, addr);
|
||||
}
|
||||
|
||||
void JIT::dsub(u32 instr) {
|
||||
@@ -764,23 +790,27 @@ void JIT::mult(u32 instr) {
|
||||
}
|
||||
|
||||
void JIT::mflo(u32 instr) {
|
||||
if (RD(instr) != 0) [[likely]] {
|
||||
regs.gpr[RD(instr)] = regs.lo;
|
||||
}
|
||||
auto dst = Entry::Operand{Entry::Operand::REG_S64, RD(instr)};
|
||||
auto src = Entry::Operand{Entry::Operand::LO};
|
||||
ir.push({Entry::MOV, dst, src});
|
||||
}
|
||||
|
||||
void JIT::mfhi(u32 instr) {
|
||||
if (RD(instr) != 0) [[likely]] {
|
||||
regs.gpr[RD(instr)] = regs.hi;
|
||||
}
|
||||
auto dst = Entry::Operand{Entry::Operand::REG_S64, RD(instr)};
|
||||
auto src = Entry::Operand{Entry::Operand::HI};
|
||||
ir.push({Entry::MOV, dst, src});
|
||||
}
|
||||
|
||||
void JIT::mtlo(u32 instr) {
|
||||
regs.lo = regs.gpr[RS(instr)];
|
||||
auto dst = Entry::Operand{Entry::Operand::LO};
|
||||
auto src = Entry::Operand{Entry::Operand::REG_S64, RS(instr)};
|
||||
ir.push({Entry::MOV, dst, src});
|
||||
}
|
||||
|
||||
void JIT::mthi(u32 instr) {
|
||||
regs.hi = regs.gpr[RS(instr)];
|
||||
auto dst = Entry::Operand{Entry::Operand::HI};
|
||||
auto src = Entry::Operand{Entry::Operand::REG_S64, RS(instr)};
|
||||
ir.push({Entry::MOV, dst, src});
|
||||
}
|
||||
|
||||
void JIT::mtc2(u32 instr) {
|
||||
|
||||
Reference in New Issue
Block a user