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This commit is contained in:
iris
2026-05-28 17:57:46 +02:00
parent 430ccdab40
commit 920b77d381
6 changed files with 19 additions and 15 deletions
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src/backend/core/Cache.cpp
+2 -2
View File
@@ -52,7 +52,7 @@ void DataCache::WriteBack<false>(u64 vaddr, u32 paddr) {
u32 origPhysAddr = (line.ptag << 12) | (paddr & 0xfff);
u32 lineStart = GetDCacheLineStart(origPhysAddr);
Core::GetInstance().interpreter.EvictCachedBlock(vaddr);
Core::GetInstance().interpreter.cachedState.EvictCachedBlock(vaddr);
for (int i = 0; i < 16; i++) {
mmio.rdp.WriteRDRAM(lineStart + i, line.data[i]);
}
@@ -87,7 +87,7 @@ void InstructionCache::WriteBack(u64 vaddr, u32 paddr, u32 ptag) {
if (line.ptag == ptag && line.valid) {
u32 origPhysAddr = (line.ptag << 12) | (paddr & 0xfff);
u32 lineStart = GetICacheLineStart(origPhysAddr);
Core::GetInstance().interpreter.EvictCachedBlock(vaddr);
Core::GetInstance().interpreter.cachedState.EvictCachedBlock(vaddr);
for (int i = 0; i < 16; i++) {
mmio.rdp.WriteRDRAM(lineStart + i, line.data[i]);
}
src/backend/core/Interpreter.hpp
-1
View File
@@ -51,7 +51,6 @@ struct Interpreter final {
u32 CacheBlock(u32 addr);
void SignalException(u32 addr) { cachedState.exception = true; }
void EvictCachedBlock(u32 addr) { cachedState.blocks[CACHE_GET_BLOCK(addr)] = {}; }
void Reset() {
cop2Latch = {};
src/backend/core/JITUtils.hpp
+2
View File
@@ -27,6 +27,8 @@ struct CachedState {
std::vector<CachedBlock<MAX_LINES / 4> *> blocks = {};
bool exception = false;
void EvictCachedBlock(u64 addr) { blocks[addr / MAX_LINES] = {}; }
void Reset() {
for (auto block : blocks) {
if (block)
src/backend/core/RSP.hpp
+3
View File
@@ -232,6 +232,7 @@ struct RSP {
FORCE_INLINE void WriteWord(u32 addr, const u32 val) {
addr &= 0xfff;
cachedState.EvictCachedBlock(addr);
SET_RSP_WORD(addr, val);
}
@@ -242,6 +243,7 @@ struct RSP {
FORCE_INLINE void WriteHalf(u32 addr, const u16 val) {
addr &= 0xfff;
cachedState.EvictCachedBlock(addr);
SET_RSP_HALF(addr, val);
}
@@ -252,6 +254,7 @@ struct RSP {
FORCE_INLINE void WriteByte(u32 addr, const u8 val) {
addr &= 0xfff;
cachedState.EvictCachedBlock(addr);
RSP_BYTE(addr) = val;
}
src/backend/core/interpreter/cop1instructions.cpp
+2 -2
View File
@@ -1310,7 +1310,7 @@ void Cop1::swc1(const Instruction instr) {
regs.cop0.HandleTLBException(addr);
regs.cop0.FireException(Cop0::GetTLBExceptionCode(regs.cop0.tlbError, Cop0::STORE), 0, regs.oldPC);
} else {
Core::GetInstance().interpreter.EvictCachedBlock(addr);
Core::GetInstance().interpreter.cachedState.EvictCachedBlock(addr);
mem.Write<u32>(physical, FGR_T<u32>(regs.cop0.status, instr.ft()));
}
}
@@ -1338,7 +1338,7 @@ void Cop1::sdc1(const Instruction instr) {
regs.cop0.HandleTLBException(addr);
regs.cop0.FireException(Cop0::GetTLBExceptionCode(regs.cop0.tlbError, Cop0::STORE), 0, regs.oldPC);
} else {
Core::GetInstance().interpreter.EvictCachedBlock(addr);
Core::GetInstance().interpreter.cachedState.EvictCachedBlock(addr);
mem.Write(physical, FGR_T<u64>(regs.cop0.status, instr.ft()));
}
}
src/backend/core/interpreter/instructions.cpp
+10 -10
View File
@@ -407,7 +407,7 @@ void Interpreter::sb(const Instruction instr) {
regs.cop0.HandleTLBException(address);
regs.cop0.FireException(Cop0::GetTLBExceptionCode(regs.cop0.tlbError, Cop0::STORE), 0, regs.oldPC);
} else {
EvictCachedBlock(address);
cachedState.EvictCachedBlock(address);
mem.Write<u8>(paddr, regs.Read<s64>(instr.rt()));
}
}
@@ -431,7 +431,7 @@ void Interpreter::sc(const Instruction instr) {
regs.cop0.HandleTLBException(address);
regs.cop0.FireException(Cop0::GetTLBExceptionCode(regs.cop0.tlbError, Cop0::STORE), 0, regs.oldPC);
} else {
EvictCachedBlock(address);
cachedState.EvictCachedBlock(address);
mem.Write<u32>(paddr, regs.Read<s64>(instr.rt()));
regs.Write(instr.rt(), 1);
}
@@ -464,7 +464,7 @@ void Interpreter::scd(const Instruction instr) {
regs.cop0.HandleTLBException(address);
regs.cop0.FireException(Cop0::GetTLBExceptionCode(regs.cop0.tlbError, Cop0::STORE), 0, regs.oldPC);
} else {
EvictCachedBlock(address);
cachedState.EvictCachedBlock(address);
mem.Write<u32>(paddr, regs.Read<s64>(instr.rt()));
regs.Write(instr.rt(), 1);
}
@@ -481,7 +481,7 @@ void Interpreter::sh(const Instruction instr) {
regs.cop0.HandleTLBException(address);
regs.cop0.FireException(Cop0::GetTLBExceptionCode(regs.cop0.tlbError, Cop0::STORE), 0, regs.oldPC);
} else {
EvictCachedBlock(address);
cachedState.EvictCachedBlock(address);
mem.Write<u16>(physical, regs.Read<s64>(instr.rt()));
}
}
@@ -500,7 +500,7 @@ void Interpreter::sw(const Instruction instr) {
regs.cop0.HandleTLBException(address);
regs.cop0.FireException(Cop0::GetTLBExceptionCode(regs.cop0.tlbError, Cop0::STORE), 0, regs.oldPC);
} else {
EvictCachedBlock(address);
cachedState.EvictCachedBlock(address);
mem.Write<u32>(physical, regs.Read<s64>(instr.rt()));
}
}
@@ -518,7 +518,7 @@ void Interpreter::sd(const Instruction instr) {
regs.cop0.HandleTLBException(address);
regs.cop0.FireException(Cop0::GetTLBExceptionCode(regs.cop0.tlbError, Cop0::STORE), 0, regs.oldPC);
} else {
EvictCachedBlock(address);
cachedState.EvictCachedBlock(address);
mem.Write(physical, regs.Read<s64>(instr.rt()));
}
}
@@ -534,7 +534,7 @@ void Interpreter::sdl(const Instruction instr) {
const u64 mask = 0xFFFFFFFFFFFFFFFF >> shift;
const u64 data = mem.Read<u64>(paddr & ~7);
const u64 rt = regs.Read<s64>(instr.rt());
EvictCachedBlock(address);
cachedState.EvictCachedBlock(address);
mem.Write(paddr & ~7, (data & ~mask) | (rt >> shift));
}
}
@@ -550,7 +550,7 @@ void Interpreter::sdr(const Instruction instr) {
const u64 mask = 0xFFFFFFFFFFFFFFFF << shift;
const u64 data = mem.Read<u64>(paddr & ~7);
const u64 rt = regs.Read<s64>(instr.rt());
EvictCachedBlock(address);
cachedState.EvictCachedBlock(address);
mem.Write(paddr & ~7, (data & ~mask) | (rt << shift));
}
}
@@ -566,7 +566,7 @@ void Interpreter::swl(const Instruction instr) {
const u32 mask = 0xFFFFFFFF >> shift;
const u32 data = mem.Read<u32>(paddr & ~3);
const u32 rt = regs.Read<s64>(instr.rt());
EvictCachedBlock(address);
cachedState.EvictCachedBlock(address);
mem.Write<u32>(paddr & ~3, (data & ~mask) | (rt >> shift));
}
}
@@ -582,7 +582,7 @@ void Interpreter::swr(const Instruction instr) {
const u32 mask = 0xFFFFFFFF << shift;
const u32 data = mem.Read<u32>(paddr & ~3);
const u32 rt = regs.Read<s64>(instr.rt());
EvictCachedBlock(address);
cachedState.EvictCachedBlock(address);
mem.Write<u32>(paddr & ~3, (data & ~mask) | (rt << shift));
}
}