iris/kaizen
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

Small fixes and improvements

Browse Source
This commit is contained in:
SimoneN64
2023-03-19 15:24:59 +01:00
parent 357b5839ca
commit 95655b7001
7 changed files with 70 additions and 64 deletions
Download Patch File Download Diff File Expand all files Collapse all files

16
src/backend/core/mmio/SI.cpp
View File

@@ -12,6 +12,8 @@ void SI::Reset() {
dramAddr = 0;
pifAddr = 0;
memset(&pif.joybusDevices, 0, sizeof(JoybusDevice) * 6);
memset(&pif.bootrom, 0, PIF_BOOTROM_SIZE);
memset(&pif.ram, 0, PIF_RAM_SIZE);
}
auto SI::Read(MI& mi, u32 addr) const -> u32 {
@@ -36,17 +38,17 @@ void DMA(Mem& mem, Registers& regs) {
SI& si = mem.mmio.si;
si.status.dmaBusy = false;
if(si.toDram) {
si.pif.ProcessPIFCommands(mem);
si.pif.ProcessCommands(mem);
for(int i = 0; i < 64; i++) {
mem.mmio.rdp.rdram[BYTE_ADDRESS(si.dramAddr + i)] = si.pif.pifRam[i];
mem.mmio.rdp.rdram[BYTE_ADDRESS(si.dramAddr + i)] = si.pif.Read(si.pifAddr + i);
}
Util::debug("SI DMA from PIF RAM to RDRAM ({:08X} to {:08X})\n", si.pifAddr, si.dramAddr);
//Util::debug("SI DMA from PIF RAM to RDRAM ({:08X} to {:08X})\n", si.pifAddr, si.dramAddr);
} else {
for(int i = 0; i < 64; i++) {
si.pif.pifRam[i] = mem.mmio.rdp.rdram[BYTE_ADDRESS(si.dramAddr + i)];
si.pif.Write(si.pifAddr + i, mem.mmio.rdp.rdram[BYTE_ADDRESS(si.dramAddr + i)]);
}
Util::debug("SI DMA from RDRAM to PIF RAM ({:08X} to {:08X})\n", si.dramAddr, si.pifAddr);
si.pif.ProcessPIFCommands(mem);
//Util::debug("SI DMA from RDRAM to PIF RAM ({:08X} to {:08X})\n", si.dramAddr, si.pifAddr);
si.pif.ProcessCommands(mem);
}
InterruptRaise(mem.mmio.mi, regs, Interrupt::SI);
}
@@ -66,7 +68,7 @@ void SI::Write(Mem& mem, Registers& regs, u32 addr, u32 val) {
pifAddr = val & 0x1FFFFFFF;
status.dmaBusy = true;
toDram = false;
scheduler.enqueueRelative({4065*3, DMA});
scheduler.enqueueRelative({SI_DMA_DELAY, DMA});
} break;
case 0x04800018:
InterruptLower(mem.mmio.mi, regs, Interrupt::SI);