Basic software fastmem + update parallel-rdp

src/n64/core/Mem.cpp

@@ -10,6 +10,28 @@ Mem::Mem() {
 }
 
 void Mem::Reset() {
+  readPages.resize(PAGE_COUNT);
+  writePages.resize(PAGE_COUNT);
+  std::fill(readPages.begin(), readPages.end(), 0);
+  std::fill(writePages.begin(), writePages.end(), 0);
+
+  for(int i = 0; i < 2048; i++) {
+    const auto pointer = (uintptr_t) &mmio.rdp.dram[(i * PAGE_SIZE) & RDRAM_DSIZE];
+    readPages[i + 0x80000] = pointer;
+    readPages[i + 0xA0000] = pointer;
+    writePages[i + 0x80000] = pointer;
+    writePages[i + 0xA0000] = pointer;
+  }
+
+  readPages[0x84000] = (uintptr_t) &mmio.rsp.dmem[0];
+  readPages[0xA4000] = (uintptr_t) &mmio.rsp.dmem[0];
+  readPages[0x84001] = (uintptr_t) &mmio.rsp.imem[0];
+  readPages[0xA4001] = (uintptr_t) &mmio.rsp.imem[0];
+  writePages[0x84000] = (uintptr_t) &mmio.rsp.dmem[0];
+  writePages[0xA4000] = (uintptr_t) &mmio.rsp.dmem[0];
+  writePages[0x84001] = (uintptr_t) &mmio.rsp.imem[0];
+  writePages[0xA4001] = (uintptr_t) &mmio.rsp.imem[0];
+
   sram.resize(SRAM_SIZE);
   std::fill(sram.begin(), sram.end(), 0);
   romMask = 0;
@@ -72,22 +94,32 @@ template bool MapVAddr<false>(Registers& regs, TLBAccessType accessType, u64 vad
 
 template <bool tlb>
 u8 Mem::Read8(n64::Registers &regs, u64 vaddr, s64 pc) {
+  const auto page = (vaddr & 0xFFFFFFFF) >> 12;
+  const auto offset = vaddr & 0xFFF;
+  const auto pointer = readPages[page];
+
+  if(pointer) {
+    return ((u8*)pointer)[BYTE_ADDRESS(offset)];
+  } else {
     u32 paddr = vaddr;
-  if(!MapVAddr<tlb>(regs, LOAD, vaddr, paddr)) {
+    if (!MapVAddr<tlb>(regs, LOAD, vaddr, paddr)) {
       HandleTLBException(regs, vaddr);
       FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, LOAD), 0, pc);
     }
 
-  switch(paddr) {
+    switch (paddr) {
       case 0x00000000 ... 0x007FFFFF:
         return mmio.rdp.dram[BYTE_ADDRESS(paddr)];
       case 0x04000000 ... 0x0403FFFF:
-      if((paddr >> 12) & 1)
+        if ((paddr >> 12) & 1)
           return mmio.rsp.imem[BYTE_ADDRESS(paddr) & IMEM_DSIZE];
         else
           return mmio.rsp.dmem[BYTE_ADDRESS(paddr) & DMEM_DSIZE];
-    case 0x04040000 ... 0x040FFFFF: case 0x04100000 ... 0x041FFFFF:
+      case 0x04040000 ... 0x040FFFFF:
-    case 0x04600000 ... 0x048FFFFF: case 0x04300000 ...	0x044FFFFF: return 0xff;
+      case 0x04100000 ... 0x041FFFFF:
+      case 0x04600000 ... 0x048FFFFF:
+      case 0x04300000 ...  0x044FFFFF:
+        return 0xff;
       case 0x04500000 ... 0x045FFFFF: {
         u32 w = mmio.ai.Read(paddr & ~3);
         int offs = 3 - (paddr & 3);
@@ -100,31 +132,44 @@ u8 Mem::Read8(n64::Registers &regs, u64 vaddr, s64 pc) {
         return pifBootrom[BYTE_ADDRESS(paddr) - 0x1FC00000];
       case 0x1FC007C0 ... 0x1FC007FF:
         return pifRam[paddr - 0x1FC007C0];
-    case 0x00800000 ... 0x03FFFFFF: case 0x04200000 ... 0x042FFFFF:
+      case 0x00800000 ... 0x03FFFFFF:
-    case 0x04900000 ... 0x0FFFFFFF: case 0x1FC00800 ... 0xFFFFFFFF: return 0;
+      case 0x04200000 ... 0x042FFFFF:
+      case 0x04900000 ... 0x0FFFFFFF:
+      case 0x1FC00800 ... 0xFFFFFFFF:
+        return 0;
       default:
-      util::panic("Unimplemented 8-bit read at address {:08X} (PC = {:016X})\n", paddr, (u64)regs.pc);
+        util::panic("Unimplemented 8-bit read at address {:08X} (PC = {:016X})\n", paddr, (u64) regs.pc);
+    }
   }
 }
 
 template <bool tlb>
 u16 Mem::Read16(n64::Registers &regs, u64 vaddr, s64 pc) {
+  const auto page = (vaddr & 0xFFFFFFFF) >> 12;
+  const auto offset = vaddr & 0xFFF;
+  const auto pointer = readPages[page];
+
+  if(pointer) {
+    return util::ReadAccess<u16>((u8*)pointer, HALF_ADDRESS(offset));
+  } else {
     u32 paddr = vaddr;
-  if(!MapVAddr<tlb>(regs, LOAD, vaddr, paddr)) {
+    if (!MapVAddr<tlb>(regs, LOAD, vaddr, paddr)) {
       HandleTLBException(regs, vaddr);
       FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, LOAD), 0, pc);
     }
 
-  switch(paddr) {
+    switch (paddr) {
       case 0x00000000 ... 0x007FFFFF:
         return util::ReadAccess<u16>(mmio.rdp.dram.data(), HALF_ADDRESS(paddr));
       case 0x04000000 ... 0x0403FFFF:
-      if((paddr >> 12) & 1)
+        if ((paddr >> 12) & 1)
           return util::ReadAccess<u16>(mmio.rsp.imem, HALF_ADDRESS(paddr) & IMEM_DSIZE);
         else
           return util::ReadAccess<u16>(mmio.rsp.dmem, HALF_ADDRESS(paddr) & DMEM_DSIZE);
-    case 0x04040000 ... 0x040FFFFF: case 0x04100000 ... 0x041FFFFF:
+      case 0x04040000 ... 0x040FFFFF:
-    case 0x04300000 ...	0x044FFFFF: case 0x04500000 ... 0x048FFFFF:
+      case 0x04100000 ... 0x041FFFFF:
+      case 0x04300000 ...  0x044FFFFF:
+      case 0x04500000 ... 0x048FFFFF:
         return mmio.Read(paddr);
       case 0x10000000 ... 0x1FBFFFFF:
         paddr = (paddr + 2) & ~3;
@@ -133,14 +178,26 @@ u16 Mem::Read16(n64::Registers &regs, u64 vaddr, s64 pc) {
         return util::ReadAccess<u16>(pifBootrom, HALF_ADDRESS(paddr) - 0x1FC00000);
       case 0x1FC007C0 ... 0x1FC007FF:
         return be16toh(util::ReadAccess<u16>(pifRam, paddr - 0x1FC007C0));
-    case 0x00800000 ... 0x03FFFFFF: case 0x04200000 ... 0x042FFFFF:
+      case 0x00800000 ... 0x03FFFFFF:
-    case 0x04900000 ... 0x0FFFFFFF: case 0x1FC00800 ... 0xFFFFFFFF: return 0;
+      case 0x04200000 ... 0x042FFFFF:
-    default: util::panic("Unimplemented 16-bit read at address {:08X} (PC = {:016X})\n", paddr, (u64)regs.pc);
+      case 0x04900000 ... 0x0FFFFFFF:
+      case 0x1FC00800 ... 0xFFFFFFFF:
+        return 0;
+      default:
+        util::panic("Unimplemented 16-bit read at address {:08X} (PC = {:016X})\n", paddr, (u64) regs.pc);
+    }
   }
 }
 
 template <bool tlb>
 u32 Mem::Read32(n64::Registers &regs, u64 vaddr, s64 pc) {
+  const auto page = (vaddr & 0xFFFFFFFF) >> 12;
+  const auto offset = vaddr & 0xFFF;
+  const auto pointer = readPages[page];
+
+  if(pointer) {
+    return util::ReadAccess<u32>((u8*)pointer, offset);
+  } else {
     u32 paddr = vaddr;
     if(!MapVAddr<tlb>(regs, LOAD, vaddr, paddr)) {
       HandleTLBException(regs, vaddr);
@@ -169,26 +226,36 @@ u32 Mem::Read32(n64::Registers &regs, u64 vaddr, s64 pc) {
       default:
         util::panic("Unimplemented 32-bit read at address {:08X} (PC = {:016X})\n", paddr, (u64) regs.pc);
     }
+  }
 }
 
 template <bool tlb>
 u64 Mem::Read64(n64::Registers &regs, u64 vaddr, s64 pc) {
+  const auto page = (vaddr & 0xFFFFFFFF) >> 12;
+  const auto offset = vaddr & 0xFFF;
+  const auto pointer = readPages[page];
+
+  if(pointer) {
+    return util::ReadAccess<u64>((u8*)pointer, offset);
+  } else {
     u32 paddr = vaddr;
-  if(!MapVAddr<tlb>(regs, LOAD, vaddr, paddr)) {
+    if (!MapVAddr<tlb>(regs, LOAD, vaddr, paddr)) {
       HandleTLBException(regs, vaddr);
       FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, LOAD), 0, pc);
     }
 
-  switch(paddr) {
+    switch (paddr) {
       case 0x00000000 ... 0x007FFFFF:
         return util::ReadAccess<u64>(mmio.rdp.dram.data(), paddr);
       case 0x04000000 ... 0x0403FFFF:
-      if((paddr >> 12) & 1)
+        if ((paddr >> 12) & 1)
           return util::ReadAccess<u64>(mmio.rsp.imem, paddr & IMEM_DSIZE);
         else
           return util::ReadAccess<u64>(mmio.rsp.dmem, paddr & DMEM_DSIZE);
-    case 0x04040000 ... 0x040FFFFF: case 0x04100000 ... 0x041FFFFF:
+      case 0x04040000 ... 0x040FFFFF:
-    case 0x04300000 ...	0x044FFFFF: case 0x04500000 ... 0x048FFFFF:
+      case 0x04100000 ... 0x041FFFFF:
+      case 0x04300000 ...  0x044FFFFF:
+      case 0x04500000 ... 0x048FFFFF:
         return mmio.Read(paddr);
       case 0x10000000 ... 0x1FBFFFFF:
         return util::ReadAccess<u64>(cart.data(), paddr & romMask);
@@ -196,9 +263,14 @@ u64 Mem::Read64(n64::Registers &regs, u64 vaddr, s64 pc) {
         return util::ReadAccess<u64>(pifBootrom, paddr - 0x1FC00000);
       case 0x1FC007C0 ... 0x1FC007FF:
         return be64toh(util::ReadAccess<u64>(pifRam, paddr - 0x1FC007C0));
-    case 0x00800000 ... 0x03FFFFFF: case 0x04200000 ... 0x042FFFFF:
+      case 0x00800000 ... 0x03FFFFFF:
-    case 0x04900000 ... 0x0FFFFFFF: case 0x1FC00800 ... 0xFFFFFFFF: return 0;
+      case 0x04200000 ... 0x042FFFFF:
-    default: util::panic("Unimplemented 32-bit read at address {:08X} (PC = {:016X})\n", paddr, (u64)regs.pc);
+      case 0x04900000 ... 0x0FFFFFFF:
+      case 0x1FC00800 ... 0xFFFFFFFF:
+        return 0;
+      default:
+        util::panic("Unimplemented 32-bit read at address {:08X} (PC = {:016X})\n", paddr, (u64) regs.pc);
+    }
   }
 }
 
@@ -213,79 +285,121 @@ template u64 Mem::Read64<true>(n64::Registers &regs, u64 vaddr, s64 pc);
 
 template <bool tlb>
 void Mem::Write8(Registers& regs, u64 vaddr, u32 val, s64 pc) {
+  const auto page = (vaddr & 0xFFFFFFFF) >> 12;
+  const auto offset = vaddr & 0xFFF;
+  const auto pointer = writePages[page];
+
+  if(pointer) {
+    ((u8*)pointer)[BYTE_ADDRESS(offset)] = val;
+  } else {
     u32 paddr = vaddr;
-  if(!MapVAddr<tlb>(regs, STORE, vaddr, paddr)) {
+    if (!MapVAddr<tlb>(regs, STORE, vaddr, paddr)) {
       HandleTLBException(regs, vaddr);
       FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, STORE), 0, pc);
     }
 
-  switch(paddr) {
+    switch (paddr) {
       case 0x00000000 ... 0x007FFFFF:
         mmio.rdp.dram[BYTE_ADDRESS(paddr)] = val;
         break;
       case 0x04000000 ... 0x0403FFFF:
         val = val << (8 * (3 - (paddr & 3)));
         paddr = (paddr & DMEM_DSIZE) & ~3;
-      if(paddr & 0x1000)
+        if (paddr & 0x1000)
           util::WriteAccess<u32>(mmio.rsp.imem, paddr & IMEM_DSIZE, val);
         else
           util::WriteAccess<u32>(mmio.rsp.dmem, paddr & DMEM_DSIZE, val);
         break;
-    case 0x04040000 ... 0x040FFFFF: case 0x04100000 ... 0x041FFFFF:
+      case 0x04040000 ... 0x040FFFFF:
-    case 0x04300000 ...	0x044FFFFF: case 0x04500000 ... 0x048FFFFF: util::panic("MMIO Write8!\n");
+      case 0x04100000 ... 0x041FFFFF:
-    case 0x10000000 ... 0x13FFFFFF: break;
+      case 0x04300000 ...  0x044FFFFF:
+      case 0x04500000 ... 0x048FFFFF:
+        util::panic("MMIO Write8!\n");
+      case 0x10000000 ... 0x13FFFFFF:
+        break;
       case 0x1FC007C0 ... 0x1FC007FF:
         val = val << (8 * (3 - (paddr & 3)));
         paddr = (paddr - 0x1FC007C0) & ~3;
         util::WriteAccess<u32>(pifRam, paddr, htobe32(val));
         ProcessPIFCommands(pifRam, mmio.si.controller, *this);
         break;
-    case 0x00800000 ... 0x03FFFFFF: case 0x04200000 ... 0x042FFFFF:
+      case 0x00800000 ... 0x03FFFFFF:
-    case 0x08000000 ... 0x0FFFFFFF: case 0x04900000 ... 0x07FFFFFF:
+      case 0x04200000 ... 0x042FFFFF:
-    case 0x1FC00800 ... 0x7FFFFFFF: case 0x80000000 ... 0xFFFFFFFF: break;
+      case 0x08000000 ... 0x0FFFFFFF:
+      case 0x04900000 ... 0x07FFFFFF:
+      case 0x1FC00800 ... 0x7FFFFFFF:
+      case 0x80000000 ... 0xFFFFFFFF:
+        break;
       default:
-      util::panic("Unimplemented 8-bit write at address {:08X} with value {:0X} (PC = {:016X})\n", paddr, val, (u64)regs.pc);
+        util::panic("Unimplemented 8-bit write at address {:08X} with value {:0X} (PC = {:016X})\n", paddr, val,
+                    (u64) regs.pc);
+    }
   }
 }
 
 template <bool tlb>
 void Mem::Write16(Registers& regs, u64 vaddr, u32 val, s64 pc) {
+  const auto page = (vaddr & 0xFFFFFFFF) >> 12;
+  const auto offset = vaddr & 0xFFF;
+  const auto pointer = writePages[page];
+
+  if(pointer) {
+    util::WriteAccess<u16>((u8*)pointer, HALF_ADDRESS(offset), val);
+  } else {
     u32 paddr = vaddr;
-  if(!MapVAddr<tlb>(regs, STORE, vaddr, paddr)) {
+    if (!MapVAddr<tlb>(regs, STORE, vaddr, paddr)) {
       HandleTLBException(regs, vaddr);
       FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, STORE), 0, pc);
     }
 
-  switch(paddr) {
+    switch (paddr) {
       case 0x00000000 ... 0x007FFFFF:
         util::WriteAccess<u16>(mmio.rdp.dram.data(), HALF_ADDRESS(paddr), val);
         break;
       case 0x04000000 ... 0x0403FFFF:
         val = val << (16 * !(paddr & 2));
         paddr &= ~3;
-      if(paddr & 0x1000)
+        if (paddr & 0x1000)
           util::WriteAccess<u32>(mmio.rsp.imem, paddr & IMEM_DSIZE, val);
         else
           util::WriteAccess<u32>(mmio.rsp.dmem, paddr & DMEM_DSIZE, val);
         break;
-    case 0x04040000 ... 0x040FFFFF: case 0x04100000 ... 0x041FFFFF:
+      case 0x04040000 ... 0x040FFFFF:
-    case 0x04300000 ...	0x044FFFFF: case 0x04500000 ... 0x048FFFFF: util::panic("MMIO Write16!\n");
+      case 0x04100000 ... 0x041FFFFF:
-    case 0x10000000 ... 0x13FFFFFF: break;
+      case 0x04300000 ...  0x044FFFFF:
+      case 0x04500000 ... 0x048FFFFF:
+        util::panic("MMIO Write16!\n");
+      case 0x10000000 ... 0x13FFFFFF:
+        break;
       case 0x1FC007C0 ... 0x1FC007FF:
         val = val << (16 * !(paddr & 2));
         paddr &= ~3;
         util::WriteAccess<u32>(pifRam, paddr - 0x1FC007C0, htobe32(val));
         ProcessPIFCommands(pifRam, mmio.si.controller, *this);
         break;
-    case 0x00800000 ... 0x03FFFFFF: case 0x04200000 ... 0x042FFFFF:
+      case 0x00800000 ... 0x03FFFFFF:
-    case 0x08000000 ... 0x0FFFFFFF: case 0x04900000 ... 0x07FFFFFF:
+      case 0x04200000 ... 0x042FFFFF:
-    case 0x1FC00800 ... 0x7FFFFFFF: case 0x80000000 ... 0xFFFFFFFF: break;
+      case 0x08000000 ... 0x0FFFFFFF:
-    default: util::panic("Unimplemented 16-bit write at address {:08X} with value {:0X} (PC = {:016X})\n", paddr, val, (u64)regs.pc);
+      case 0x04900000 ... 0x07FFFFFF:
+      case 0x1FC00800 ... 0x7FFFFFFF:
+      case 0x80000000 ... 0xFFFFFFFF:
+        break;
+      default:
+        util::panic("Unimplemented 16-bit write at address {:08X} with value {:0X} (PC = {:016X})\n", paddr, val,
+                    (u64) regs.pc);
+    }
   }
 }
 
 template <bool tlb>
 void Mem::Write32(Registers& regs, u64 vaddr, u32 val, s64 pc) {
+  const auto page = (vaddr & 0xFFFFFFFF) >> 12;
+  const auto offset = vaddr & 0xFFF;
+  const auto pointer = writePages[page];
+
+  if(pointer) {
+    util::WriteAccess<u32>((u8*)pointer, offset, val);
+  } else {
     u32 paddr = vaddr;
     if(!MapVAddr<tlb>(regs, STORE, vaddr, paddr)) {
       HandleTLBException(regs, vaddr);
@@ -325,38 +439,57 @@ void Mem::Write32(Registers& regs, u64 vaddr, u32 val, s64 pc) {
       case 0x1FC00800 ... 0x7FFFFFFF: case 0x80000000 ... 0xFFFFFFFF: break;
       default: util::panic("Unimplemented 32-bit write at address {:08X} with value {:0X} (PC = {:016X})\n", paddr, val, (u64)regs.pc);
     }
+  }
 }
 
 template <bool tlb>
 void Mem::Write64(Registers& regs, u64 vaddr, u64 val, s64 pc) {
+  const auto page = (vaddr & 0xFFFFFFFF) >> 12;
+  const auto offset = vaddr & 0xFFF;
+  const auto pointer = writePages[page];
+
+  if(pointer) {
+    util::WriteAccess<u64>((u8*)pointer, offset, val);
+  } else {
     u32 paddr = vaddr;
-  if(!MapVAddr<tlb>(regs, STORE, vaddr, paddr)) {
+    if (!MapVAddr<tlb>(regs, STORE, vaddr, paddr)) {
       HandleTLBException(regs, vaddr);
       FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, STORE), 0, pc);
     }
 
-  switch(paddr) {
+    switch (paddr) {
       case 0x00000000 ... 0x007FFFFF:
         util::WriteAccess<u64>(mmio.rdp.dram.data(), paddr, val);
         break;
       case 0x04000000 ... 0x0403FFFF:
         val >>= 32;
-      if(paddr & 0x1000)
+        if (paddr & 0x1000)
           util::WriteAccess<u32>(mmio.rsp.imem, paddr & IMEM_DSIZE, val);
         else
           util::WriteAccess<u32>(mmio.rsp.dmem, paddr & DMEM_DSIZE, val);
         break;
-    case 0x04040000 ... 0x040FFFFF: case 0x04100000 ... 0x041FFFFF:
+      case 0x04040000 ... 0x040FFFFF:
-    case 0x04300000 ...	0x044FFFFF: case 0x04500000 ... 0x048FFFFF: util::panic("MMIO Write64!\n");
+      case 0x04100000 ... 0x041FFFFF:
-    case 0x10000000 ... 0x13FFFFFF: break;
+      case 0x04300000 ...  0x044FFFFF:
+      case 0x04500000 ... 0x048FFFFF:
+        util::panic("MMIO Write64!\n");
+      case 0x10000000 ... 0x13FFFFFF:
+        break;
       case 0x1FC007C0 ... 0x1FC007FF:
         util::WriteAccess<u64>(pifRam, paddr - 0x1FC007C0, htobe64(val));
         ProcessPIFCommands(pifRam, mmio.si.controller, *this);
         break;
-    case 0x00800000 ... 0x03FFFFFF: case 0x04200000 ... 0x042FFFFF:
+      case 0x00800000 ... 0x03FFFFFF:
-    case 0x08000000 ... 0x0FFFFFFF: case 0x04900000 ... 0x07FFFFFF:
+      case 0x04200000 ... 0x042FFFFF:
-    case 0x1FC00800 ... 0x7FFFFFFF: case 0x80000000 ... 0xFFFFFFFF: break;
+      case 0x08000000 ... 0x0FFFFFFF:
-    default: util::panic("Unimplemented 64-bit write at address {:08X} with value {:0X} (PC = {:016X})\n", paddr, val, (u64)regs.pc);
+      case 0x04900000 ... 0x07FFFFFF:
+      case 0x1FC00800 ... 0x7FFFFFFF:
+      case 0x80000000 ... 0xFFFFFFFF:
+        break;
+      default:
+        util::panic("Unimplemented 64-bit write at address {:08X} with value {:0X} (PC = {:016X})\n", paddr, val,
+                    (u64) regs.pc);
+    }
   }
 }
 

src/n64/core/Mem.hpp

@@ -82,6 +82,7 @@ private:
   std::vector<u8> cart, sram;
   u8 pifBootrom[PIF_BOOTROM_SIZE]{};
   u8 isviewer[ISVIEWER_SIZE]{};
+  std::vector<uintptr_t> writePages, readPages;
   size_t romMask;
 
   void SetCICType(u32& cicType, u32 checksum) {

src/n64/memory_regions.hpp

@@ -30,3 +30,19 @@
 #define CART_REGION 0x10000000 ... 0x1FBFFFFF
 #define PIF_ROM_REGION 0x1FC00000 ... 0x1FC007BF
 #define PIF_RAM_REGION 0x1FC007C0 ... 0x1FC007FF
+
+constexpr size_t operator""_kb(unsigned long long int x) {
+  return 1024ULL * x;
+}
+
+constexpr size_t operator""_mb(unsigned long long int x) {
+  return 1024_kb * x;
+}
+
+constexpr size_t operator""_gb(unsigned long long int x) {
+  return 1024_mb * x;
+}
+
+#define ADDRESS_RANGE_SIZE 4_gb
+#define PAGE_SIZE 4_kb
+#define PAGE_COUNT ((ADDRESS_RANGE_SIZE) / (PAGE_SIZE))