Basic software fastmem + update parallel-rdp
This commit is contained in:
CocoSimone
Submodule external/parallel-rdp/parallel-rdp-standalone updated: cc7c8801f7...6559addc5d
@@ -10,6 +10,28 @@ Mem::Mem() {
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}
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void Mem::Reset() {
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readPages.resize(PAGE_COUNT);
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writePages.resize(PAGE_COUNT);
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std::fill(readPages.begin(), readPages.end(), 0);
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std::fill(writePages.begin(), writePages.end(), 0);
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for(int i = 0; i < 2048; i++) {
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const auto pointer = (uintptr_t) &mmio.rdp.dram[(i * PAGE_SIZE) & RDRAM_DSIZE];
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readPages[i + 0x80000] = pointer;
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readPages[i + 0xA0000] = pointer;
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writePages[i + 0x80000] = pointer;
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writePages[i + 0xA0000] = pointer;
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}
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readPages[0x84000] = (uintptr_t) &mmio.rsp.dmem[0];
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readPages[0xA4000] = (uintptr_t) &mmio.rsp.dmem[0];
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readPages[0x84001] = (uintptr_t) &mmio.rsp.imem[0];
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readPages[0xA4001] = (uintptr_t) &mmio.rsp.imem[0];
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writePages[0x84000] = (uintptr_t) &mmio.rsp.dmem[0];
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writePages[0xA4000] = (uintptr_t) &mmio.rsp.dmem[0];
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writePages[0x84001] = (uintptr_t) &mmio.rsp.imem[0];
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writePages[0xA4001] = (uintptr_t) &mmio.rsp.imem[0];
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sram.resize(SRAM_SIZE);
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std::fill(sram.begin(), sram.end(), 0);
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romMask = 0;
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@@ -72,133 +94,183 @@ template bool MapVAddr<false>(Registers& regs, TLBAccessType accessType, u64 vad
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template <bool tlb>
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u8 Mem::Read8(n64::Registers ®s, u64 vaddr, s64 pc) {
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u32 paddr = vaddr;
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if(!MapVAddr<tlb>(regs, LOAD, vaddr, paddr)) {
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HandleTLBException(regs, vaddr);
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FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, LOAD), 0, pc);
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}
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const auto page = (vaddr & 0xFFFFFFFF) >> 12;
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const auto offset = vaddr & 0xFFF;
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const auto pointer = readPages[page];
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switch(paddr) {
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case 0x00000000 ... 0x007FFFFF:
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return mmio.rdp.dram[BYTE_ADDRESS(paddr)];
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case 0x04000000 ... 0x0403FFFF:
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if((paddr >> 12) & 1)
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return mmio.rsp.imem[BYTE_ADDRESS(paddr) & IMEM_DSIZE];
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else
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return mmio.rsp.dmem[BYTE_ADDRESS(paddr) & DMEM_DSIZE];
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case 0x04040000 ... 0x040FFFFF: case 0x04100000 ... 0x041FFFFF:
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case 0x04600000 ... 0x048FFFFF: case 0x04300000 ... 0x044FFFFF: return 0xff;
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case 0x04500000 ... 0x045FFFFF: {
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u32 w = mmio.ai.Read(paddr & ~3);
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int offs = 3 - (paddr & 3);
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return (w >> (offs * 8)) & 0xff;
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if(pointer) {
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return ((u8*)pointer)[BYTE_ADDRESS(offset)];
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} else {
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u32 paddr = vaddr;
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if (!MapVAddr<tlb>(regs, LOAD, vaddr, paddr)) {
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HandleTLBException(regs, vaddr);
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FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, LOAD), 0, pc);
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}
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switch (paddr) {
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case 0x00000000 ... 0x007FFFFF:
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return mmio.rdp.dram[BYTE_ADDRESS(paddr)];
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case 0x04000000 ... 0x0403FFFF:
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if ((paddr >> 12) & 1)
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return mmio.rsp.imem[BYTE_ADDRESS(paddr) & IMEM_DSIZE];
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else
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return mmio.rsp.dmem[BYTE_ADDRESS(paddr) & DMEM_DSIZE];
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case 0x04040000 ... 0x040FFFFF:
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case 0x04100000 ... 0x041FFFFF:
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case 0x04600000 ... 0x048FFFFF:
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case 0x04300000 ... 0x044FFFFF:
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return 0xff;
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case 0x04500000 ... 0x045FFFFF: {
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u32 w = mmio.ai.Read(paddr & ~3);
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int offs = 3 - (paddr & 3);
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return (w >> (offs * 8)) & 0xff;
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}
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case 0x10000000 ... 0x1FBFFFFF:
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paddr = (paddr + 2) & ~2;
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return cart[BYTE_ADDRESS(paddr) & romMask];
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case 0x1FC00000 ... 0x1FC007BF:
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return pifBootrom[BYTE_ADDRESS(paddr) - 0x1FC00000];
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case 0x1FC007C0 ... 0x1FC007FF:
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return pifRam[paddr - 0x1FC007C0];
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case 0x00800000 ... 0x03FFFFFF:
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case 0x04200000 ... 0x042FFFFF:
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case 0x04900000 ... 0x0FFFFFFF:
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case 0x1FC00800 ... 0xFFFFFFFF:
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return 0;
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default:
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util::panic("Unimplemented 8-bit read at address {:08X} (PC = {:016X})\n", paddr, (u64) regs.pc);
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}
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case 0x10000000 ... 0x1FBFFFFF:
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paddr = (paddr + 2) & ~2;
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return cart[BYTE_ADDRESS(paddr) & romMask];
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case 0x1FC00000 ... 0x1FC007BF:
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return pifBootrom[BYTE_ADDRESS(paddr) - 0x1FC00000];
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case 0x1FC007C0 ... 0x1FC007FF:
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return pifRam[paddr - 0x1FC007C0];
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case 0x00800000 ... 0x03FFFFFF: case 0x04200000 ... 0x042FFFFF:
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case 0x04900000 ... 0x0FFFFFFF: case 0x1FC00800 ... 0xFFFFFFFF: return 0;
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default:
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util::panic("Unimplemented 8-bit read at address {:08X} (PC = {:016X})\n", paddr, (u64)regs.pc);
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}
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}
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template <bool tlb>
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u16 Mem::Read16(n64::Registers ®s, u64 vaddr, s64 pc) {
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u32 paddr = vaddr;
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if(!MapVAddr<tlb>(regs, LOAD, vaddr, paddr)) {
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HandleTLBException(regs, vaddr);
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FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, LOAD), 0, pc);
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}
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const auto page = (vaddr & 0xFFFFFFFF) >> 12;
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const auto offset = vaddr & 0xFFF;
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const auto pointer = readPages[page];
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switch(paddr) {
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case 0x00000000 ... 0x007FFFFF:
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return util::ReadAccess<u16>(mmio.rdp.dram.data(), HALF_ADDRESS(paddr));
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case 0x04000000 ... 0x0403FFFF:
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if((paddr >> 12) & 1)
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return util::ReadAccess<u16>(mmio.rsp.imem, HALF_ADDRESS(paddr) & IMEM_DSIZE);
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else
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return util::ReadAccess<u16>(mmio.rsp.dmem, HALF_ADDRESS(paddr) & DMEM_DSIZE);
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case 0x04040000 ... 0x040FFFFF: case 0x04100000 ... 0x041FFFFF:
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case 0x04300000 ... 0x044FFFFF: case 0x04500000 ... 0x048FFFFF:
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return mmio.Read(paddr);
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case 0x10000000 ... 0x1FBFFFFF:
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paddr = (paddr + 2) & ~3;
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return util::ReadAccess<u16>(cart.data(), HALF_ADDRESS(paddr) & romMask);
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case 0x1FC00000 ... 0x1FC007BF:
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return util::ReadAccess<u16>(pifBootrom, HALF_ADDRESS(paddr) - 0x1FC00000);
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case 0x1FC007C0 ... 0x1FC007FF:
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return be16toh(util::ReadAccess<u16>(pifRam, paddr - 0x1FC007C0));
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case 0x00800000 ... 0x03FFFFFF: case 0x04200000 ... 0x042FFFFF:
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case 0x04900000 ... 0x0FFFFFFF: case 0x1FC00800 ... 0xFFFFFFFF: return 0;
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default: util::panic("Unimplemented 16-bit read at address {:08X} (PC = {:016X})\n", paddr, (u64)regs.pc);
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if(pointer) {
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return util::ReadAccess<u16>((u8*)pointer, HALF_ADDRESS(offset));
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} else {
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u32 paddr = vaddr;
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if (!MapVAddr<tlb>(regs, LOAD, vaddr, paddr)) {
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HandleTLBException(regs, vaddr);
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FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, LOAD), 0, pc);
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}
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switch (paddr) {
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case 0x00000000 ... 0x007FFFFF:
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return util::ReadAccess<u16>(mmio.rdp.dram.data(), HALF_ADDRESS(paddr));
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case 0x04000000 ... 0x0403FFFF:
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if ((paddr >> 12) & 1)
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return util::ReadAccess<u16>(mmio.rsp.imem, HALF_ADDRESS(paddr) & IMEM_DSIZE);
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else
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return util::ReadAccess<u16>(mmio.rsp.dmem, HALF_ADDRESS(paddr) & DMEM_DSIZE);
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case 0x04040000 ... 0x040FFFFF:
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case 0x04100000 ... 0x041FFFFF:
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case 0x04300000 ... 0x044FFFFF:
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case 0x04500000 ... 0x048FFFFF:
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return mmio.Read(paddr);
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case 0x10000000 ... 0x1FBFFFFF:
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paddr = (paddr + 2) & ~3;
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return util::ReadAccess<u16>(cart.data(), HALF_ADDRESS(paddr) & romMask);
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case 0x1FC00000 ... 0x1FC007BF:
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return util::ReadAccess<u16>(pifBootrom, HALF_ADDRESS(paddr) - 0x1FC00000);
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case 0x1FC007C0 ... 0x1FC007FF:
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return be16toh(util::ReadAccess<u16>(pifRam, paddr - 0x1FC007C0));
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case 0x00800000 ... 0x03FFFFFF:
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case 0x04200000 ... 0x042FFFFF:
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case 0x04900000 ... 0x0FFFFFFF:
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case 0x1FC00800 ... 0xFFFFFFFF:
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return 0;
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default:
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util::panic("Unimplemented 16-bit read at address {:08X} (PC = {:016X})\n", paddr, (u64) regs.pc);
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}
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}
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}
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template <bool tlb>
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u32 Mem::Read32(n64::Registers ®s, u64 vaddr, s64 pc) {
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u32 paddr = vaddr;
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if(!MapVAddr<tlb>(regs, LOAD, vaddr, paddr)) {
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HandleTLBException(regs, vaddr);
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FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, LOAD), 0, pc);
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}
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const auto page = (vaddr & 0xFFFFFFFF) >> 12;
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const auto offset = vaddr & 0xFFF;
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const auto pointer = readPages[page];
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switch(paddr) {
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case 0x00000000 ... 0x007FFFFF:
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return util::ReadAccess<u32>(mmio.rdp.dram.data(), paddr);
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case 0x04000000 ... 0x0403FFFF:
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if((paddr >> 12) & 1)
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return util::ReadAccess<u32>(mmio.rsp.imem, paddr & IMEM_DSIZE);
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else
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return util::ReadAccess<u32>(mmio.rsp.dmem, paddr & DMEM_DSIZE);
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case 0x04040000 ... 0x040FFFFF: case 0x04100000 ... 0x041FFFFF:
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case 0x04300000 ... 0x044FFFFF: case 0x04500000 ... 0x048FFFFF:
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return mmio.Read(paddr);
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case 0x10000000 ... 0x1FBFFFFF:
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return util::ReadAccess<u32>(cart.data(), paddr & romMask);
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case 0x1FC00000 ... 0x1FC007BF:
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return util::ReadAccess<u32>(pifBootrom, paddr - 0x1FC00000);
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case 0x1FC007C0 ... 0x1FC007FF:
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return be32toh(util::ReadAccess<u32>(pifRam, paddr - 0x1FC007C0));
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case 0x00800000 ... 0x03FFFFFF: case 0x04200000 ... 0x042FFFFF:
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case 0x04900000 ... 0x0FFFFFFF: case 0x1FC00800 ... 0xFFFFFFFF: return 0;
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default:
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util::panic("Unimplemented 32-bit read at address {:08X} (PC = {:016X})\n", paddr, (u64) regs.pc);
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if(pointer) {
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return util::ReadAccess<u32>((u8*)pointer, offset);
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} else {
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u32 paddr = vaddr;
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if(!MapVAddr<tlb>(regs, LOAD, vaddr, paddr)) {
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HandleTLBException(regs, vaddr);
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FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, LOAD), 0, pc);
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}
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switch(paddr) {
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case 0x00000000 ... 0x007FFFFF:
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return util::ReadAccess<u32>(mmio.rdp.dram.data(), paddr);
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case 0x04000000 ... 0x0403FFFF:
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if((paddr >> 12) & 1)
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return util::ReadAccess<u32>(mmio.rsp.imem, paddr & IMEM_DSIZE);
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else
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return util::ReadAccess<u32>(mmio.rsp.dmem, paddr & DMEM_DSIZE);
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case 0x04040000 ... 0x040FFFFF: case 0x04100000 ... 0x041FFFFF:
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case 0x04300000 ... 0x044FFFFF: case 0x04500000 ... 0x048FFFFF:
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return mmio.Read(paddr);
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case 0x10000000 ... 0x1FBFFFFF:
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return util::ReadAccess<u32>(cart.data(), paddr & romMask);
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case 0x1FC00000 ... 0x1FC007BF:
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return util::ReadAccess<u32>(pifBootrom, paddr - 0x1FC00000);
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case 0x1FC007C0 ... 0x1FC007FF:
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return be32toh(util::ReadAccess<u32>(pifRam, paddr - 0x1FC007C0));
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case 0x00800000 ... 0x03FFFFFF: case 0x04200000 ... 0x042FFFFF:
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case 0x04900000 ... 0x0FFFFFFF: case 0x1FC00800 ... 0xFFFFFFFF: return 0;
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default:
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util::panic("Unimplemented 32-bit read at address {:08X} (PC = {:016X})\n", paddr, (u64) regs.pc);
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}
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}
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}
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template <bool tlb>
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u64 Mem::Read64(n64::Registers ®s, u64 vaddr, s64 pc) {
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u32 paddr = vaddr;
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if(!MapVAddr<tlb>(regs, LOAD, vaddr, paddr)) {
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HandleTLBException(regs, vaddr);
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FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, LOAD), 0, pc);
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}
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const auto page = (vaddr & 0xFFFFFFFF) >> 12;
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const auto offset = vaddr & 0xFFF;
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const auto pointer = readPages[page];
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switch(paddr) {
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case 0x00000000 ... 0x007FFFFF:
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return util::ReadAccess<u64>(mmio.rdp.dram.data(), paddr);
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case 0x04000000 ... 0x0403FFFF:
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if((paddr >> 12) & 1)
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return util::ReadAccess<u64>(mmio.rsp.imem, paddr & IMEM_DSIZE);
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else
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return util::ReadAccess<u64>(mmio.rsp.dmem, paddr & DMEM_DSIZE);
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case 0x04040000 ... 0x040FFFFF: case 0x04100000 ... 0x041FFFFF:
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case 0x04300000 ... 0x044FFFFF: case 0x04500000 ... 0x048FFFFF:
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return mmio.Read(paddr);
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case 0x10000000 ... 0x1FBFFFFF:
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return util::ReadAccess<u64>(cart.data(), paddr & romMask);
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case 0x1FC00000 ... 0x1FC007BF:
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return util::ReadAccess<u64>(pifBootrom, paddr - 0x1FC00000);
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case 0x1FC007C0 ... 0x1FC007FF:
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return be64toh(util::ReadAccess<u64>(pifRam, paddr - 0x1FC007C0));
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case 0x00800000 ... 0x03FFFFFF: case 0x04200000 ... 0x042FFFFF:
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case 0x04900000 ... 0x0FFFFFFF: case 0x1FC00800 ... 0xFFFFFFFF: return 0;
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default: util::panic("Unimplemented 32-bit read at address {:08X} (PC = {:016X})\n", paddr, (u64)regs.pc);
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if(pointer) {
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return util::ReadAccess<u64>((u8*)pointer, offset);
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} else {
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u32 paddr = vaddr;
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if (!MapVAddr<tlb>(regs, LOAD, vaddr, paddr)) {
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HandleTLBException(regs, vaddr);
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FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, LOAD), 0, pc);
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}
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switch (paddr) {
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case 0x00000000 ... 0x007FFFFF:
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return util::ReadAccess<u64>(mmio.rdp.dram.data(), paddr);
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case 0x04000000 ... 0x0403FFFF:
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if ((paddr >> 12) & 1)
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return util::ReadAccess<u64>(mmio.rsp.imem, paddr & IMEM_DSIZE);
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else
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return util::ReadAccess<u64>(mmio.rsp.dmem, paddr & DMEM_DSIZE);
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case 0x04040000 ... 0x040FFFFF:
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case 0x04100000 ... 0x041FFFFF:
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case 0x04300000 ... 0x044FFFFF:
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case 0x04500000 ... 0x048FFFFF:
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return mmio.Read(paddr);
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case 0x10000000 ... 0x1FBFFFFF:
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return util::ReadAccess<u64>(cart.data(), paddr & romMask);
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case 0x1FC00000 ... 0x1FC007BF:
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return util::ReadAccess<u64>(pifBootrom, paddr - 0x1FC00000);
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case 0x1FC007C0 ... 0x1FC007FF:
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return be64toh(util::ReadAccess<u64>(pifRam, paddr - 0x1FC007C0));
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case 0x00800000 ... 0x03FFFFFF:
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case 0x04200000 ... 0x042FFFFF:
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case 0x04900000 ... 0x0FFFFFFF:
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case 0x1FC00800 ... 0xFFFFFFFF:
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return 0;
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default:
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util::panic("Unimplemented 32-bit read at address {:08X} (PC = {:016X})\n", paddr, (u64) regs.pc);
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}
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}
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}
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@@ -213,150 +285,211 @@ template u64 Mem::Read64<true>(n64::Registers ®s, u64 vaddr, s64 pc);
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template <bool tlb>
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void Mem::Write8(Registers& regs, u64 vaddr, u32 val, s64 pc) {
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u32 paddr = vaddr;
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if(!MapVAddr<tlb>(regs, STORE, vaddr, paddr)) {
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HandleTLBException(regs, vaddr);
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FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, STORE), 0, pc);
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}
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const auto page = (vaddr & 0xFFFFFFFF) >> 12;
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const auto offset = vaddr & 0xFFF;
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const auto pointer = writePages[page];
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switch(paddr) {
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case 0x00000000 ... 0x007FFFFF:
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mmio.rdp.dram[BYTE_ADDRESS(paddr)] = val;
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break;
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case 0x04000000 ... 0x0403FFFF:
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val = val << (8 * (3 - (paddr & 3)));
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paddr = (paddr & DMEM_DSIZE) & ~3;
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if(paddr & 0x1000)
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util::WriteAccess<u32>(mmio.rsp.imem, paddr & IMEM_DSIZE, val);
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else
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util::WriteAccess<u32>(mmio.rsp.dmem, paddr & DMEM_DSIZE, val);
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break;
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case 0x04040000 ... 0x040FFFFF: case 0x04100000 ... 0x041FFFFF:
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case 0x04300000 ... 0x044FFFFF: case 0x04500000 ... 0x048FFFFF: util::panic("MMIO Write8!\n");
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case 0x10000000 ... 0x13FFFFFF: break;
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case 0x1FC007C0 ... 0x1FC007FF:
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val = val << (8 * (3 - (paddr & 3)));
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paddr = (paddr - 0x1FC007C0) & ~3;
|
||||
util::WriteAccess<u32>(pifRam, paddr, htobe32(val));
|
||||
ProcessPIFCommands(pifRam, mmio.si.controller, *this);
|
||||
break;
|
||||
case 0x00800000 ... 0x03FFFFFF: case 0x04200000 ... 0x042FFFFF:
|
||||
case 0x08000000 ... 0x0FFFFFFF: case 0x04900000 ... 0x07FFFFFF:
|
||||
case 0x1FC00800 ... 0x7FFFFFFF: case 0x80000000 ... 0xFFFFFFFF: break;
|
||||
default:
|
||||
util::panic("Unimplemented 8-bit write at address {:08X} with value {:0X} (PC = {:016X})\n", paddr, val, (u64)regs.pc);
|
||||
if(pointer) {
|
||||
((u8*)pointer)[BYTE_ADDRESS(offset)] = val;
|
||||
} else {
|
||||
u32 paddr = vaddr;
|
||||
if (!MapVAddr<tlb>(regs, STORE, vaddr, paddr)) {
|
||||
HandleTLBException(regs, vaddr);
|
||||
FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, STORE), 0, pc);
|
||||
}
|
||||
|
||||
switch (paddr) {
|
||||
case 0x00000000 ... 0x007FFFFF:
|
||||
mmio.rdp.dram[BYTE_ADDRESS(paddr)] = val;
|
||||
break;
|
||||
case 0x04000000 ... 0x0403FFFF:
|
||||
val = val << (8 * (3 - (paddr & 3)));
|
||||
paddr = (paddr & DMEM_DSIZE) & ~3;
|
||||
if (paddr & 0x1000)
|
||||
util::WriteAccess<u32>(mmio.rsp.imem, paddr & IMEM_DSIZE, val);
|
||||
else
|
||||
util::WriteAccess<u32>(mmio.rsp.dmem, paddr & DMEM_DSIZE, val);
|
||||
break;
|
||||
case 0x04040000 ... 0x040FFFFF:
|
||||
case 0x04100000 ... 0x041FFFFF:
|
||||
case 0x04300000 ... 0x044FFFFF:
|
||||
case 0x04500000 ... 0x048FFFFF:
|
||||
util::panic("MMIO Write8!\n");
|
||||
case 0x10000000 ... 0x13FFFFFF:
|
||||
break;
|
||||
case 0x1FC007C0 ... 0x1FC007FF:
|
||||
val = val << (8 * (3 - (paddr & 3)));
|
||||
paddr = (paddr - 0x1FC007C0) & ~3;
|
||||
util::WriteAccess<u32>(pifRam, paddr, htobe32(val));
|
||||
ProcessPIFCommands(pifRam, mmio.si.controller, *this);
|
||||
break;
|
||||
case 0x00800000 ... 0x03FFFFFF:
|
||||
case 0x04200000 ... 0x042FFFFF:
|
||||
case 0x08000000 ... 0x0FFFFFFF:
|
||||
case 0x04900000 ... 0x07FFFFFF:
|
||||
case 0x1FC00800 ... 0x7FFFFFFF:
|
||||
case 0x80000000 ... 0xFFFFFFFF:
|
||||
break;
|
||||
default:
|
||||
util::panic("Unimplemented 8-bit write at address {:08X} with value {:0X} (PC = {:016X})\n", paddr, val,
|
||||
(u64) regs.pc);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
template <bool tlb>
|
||||
void Mem::Write16(Registers& regs, u64 vaddr, u32 val, s64 pc) {
|
||||
u32 paddr = vaddr;
|
||||
if(!MapVAddr<tlb>(regs, STORE, vaddr, paddr)) {
|
||||
HandleTLBException(regs, vaddr);
|
||||
FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, STORE), 0, pc);
|
||||
}
|
||||
const auto page = (vaddr & 0xFFFFFFFF) >> 12;
|
||||
const auto offset = vaddr & 0xFFF;
|
||||
const auto pointer = writePages[page];
|
||||
|
||||
switch(paddr) {
|
||||
case 0x00000000 ... 0x007FFFFF:
|
||||
util::WriteAccess<u16>(mmio.rdp.dram.data(), HALF_ADDRESS(paddr), val);
|
||||
break;
|
||||
case 0x04000000 ... 0x0403FFFF:
|
||||
val = val << (16 * !(paddr & 2));
|
||||
paddr &= ~3;
|
||||
if(paddr & 0x1000)
|
||||
util::WriteAccess<u32>(mmio.rsp.imem, paddr & IMEM_DSIZE, val);
|
||||
else
|
||||
util::WriteAccess<u32>(mmio.rsp.dmem, paddr & DMEM_DSIZE, val);
|
||||
break;
|
||||
case 0x04040000 ... 0x040FFFFF: case 0x04100000 ... 0x041FFFFF:
|
||||
case 0x04300000 ... 0x044FFFFF: case 0x04500000 ... 0x048FFFFF: util::panic("MMIO Write16!\n");
|
||||
case 0x10000000 ... 0x13FFFFFF: break;
|
||||
case 0x1FC007C0 ... 0x1FC007FF:
|
||||
val = val << (16 * !(paddr & 2));
|
||||
paddr &= ~3;
|
||||
util::WriteAccess<u32>(pifRam, paddr - 0x1FC007C0, htobe32(val));
|
||||
ProcessPIFCommands(pifRam, mmio.si.controller, *this);
|
||||
break;
|
||||
case 0x00800000 ... 0x03FFFFFF: case 0x04200000 ... 0x042FFFFF:
|
||||
case 0x08000000 ... 0x0FFFFFFF: case 0x04900000 ... 0x07FFFFFF:
|
||||
case 0x1FC00800 ... 0x7FFFFFFF: case 0x80000000 ... 0xFFFFFFFF: break;
|
||||
default: util::panic("Unimplemented 16-bit write at address {:08X} with value {:0X} (PC = {:016X})\n", paddr, val, (u64)regs.pc);
|
||||
if(pointer) {
|
||||
util::WriteAccess<u16>((u8*)pointer, HALF_ADDRESS(offset), val);
|
||||
} else {
|
||||
u32 paddr = vaddr;
|
||||
if (!MapVAddr<tlb>(regs, STORE, vaddr, paddr)) {
|
||||
HandleTLBException(regs, vaddr);
|
||||
FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, STORE), 0, pc);
|
||||
}
|
||||
|
||||
switch (paddr) {
|
||||
case 0x00000000 ... 0x007FFFFF:
|
||||
util::WriteAccess<u16>(mmio.rdp.dram.data(), HALF_ADDRESS(paddr), val);
|
||||
break;
|
||||
case 0x04000000 ... 0x0403FFFF:
|
||||
val = val << (16 * !(paddr & 2));
|
||||
paddr &= ~3;
|
||||
if (paddr & 0x1000)
|
||||
util::WriteAccess<u32>(mmio.rsp.imem, paddr & IMEM_DSIZE, val);
|
||||
else
|
||||
util::WriteAccess<u32>(mmio.rsp.dmem, paddr & DMEM_DSIZE, val);
|
||||
break;
|
||||
case 0x04040000 ... 0x040FFFFF:
|
||||
case 0x04100000 ... 0x041FFFFF:
|
||||
case 0x04300000 ... 0x044FFFFF:
|
||||
case 0x04500000 ... 0x048FFFFF:
|
||||
util::panic("MMIO Write16!\n");
|
||||
case 0x10000000 ... 0x13FFFFFF:
|
||||
break;
|
||||
case 0x1FC007C0 ... 0x1FC007FF:
|
||||
val = val << (16 * !(paddr & 2));
|
||||
paddr &= ~3;
|
||||
util::WriteAccess<u32>(pifRam, paddr - 0x1FC007C0, htobe32(val));
|
||||
ProcessPIFCommands(pifRam, mmio.si.controller, *this);
|
||||
break;
|
||||
case 0x00800000 ... 0x03FFFFFF:
|
||||
case 0x04200000 ... 0x042FFFFF:
|
||||
case 0x08000000 ... 0x0FFFFFFF:
|
||||
case 0x04900000 ... 0x07FFFFFF:
|
||||
case 0x1FC00800 ... 0x7FFFFFFF:
|
||||
case 0x80000000 ... 0xFFFFFFFF:
|
||||
break;
|
||||
default:
|
||||
util::panic("Unimplemented 16-bit write at address {:08X} with value {:0X} (PC = {:016X})\n", paddr, val,
|
||||
(u64) regs.pc);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
template <bool tlb>
|
||||
void Mem::Write32(Registers& regs, u64 vaddr, u32 val, s64 pc) {
|
||||
u32 paddr = vaddr;
|
||||
if(!MapVAddr<tlb>(regs, STORE, vaddr, paddr)) {
|
||||
HandleTLBException(regs, vaddr);
|
||||
FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, STORE), 0, pc);
|
||||
}
|
||||
const auto page = (vaddr & 0xFFFFFFFF) >> 12;
|
||||
const auto offset = vaddr & 0xFFF;
|
||||
const auto pointer = writePages[page];
|
||||
|
||||
switch(paddr) {
|
||||
case 0x00000000 ... 0x007FFFFF:
|
||||
util::WriteAccess<u32>(mmio.rdp.dram.data(), paddr, val);
|
||||
break;
|
||||
case 0x04000000 ... 0x0403FFFF:
|
||||
if(paddr & 0x1000)
|
||||
util::WriteAccess<u32>(mmio.rsp.imem, paddr & IMEM_DSIZE, val);
|
||||
else
|
||||
util::WriteAccess<u32>(mmio.rsp.dmem, paddr & DMEM_DSIZE, val);
|
||||
break;
|
||||
case 0x04040000 ... 0x040FFFFF: case 0x04100000 ... 0x041FFFFF:
|
||||
case 0x04300000 ... 0x044FFFFF: case 0x04500000 ... 0x048FFFFF: mmio.Write(*this, regs, paddr, val); break;
|
||||
case 0x10000000 ... 0x13FF0013: break;
|
||||
case 0x13FF0014: {
|
||||
if(val < ISVIEWER_SIZE) {
|
||||
char* message = (char*)calloc(val + 1, 1);
|
||||
memcpy(message, isviewer, val);
|
||||
fmt::print("{}", message);
|
||||
free(message);
|
||||
}
|
||||
} break;
|
||||
case 0x13FF0020 ... 0x13FFFFFF:
|
||||
util::WriteAccess<u32>(isviewer, paddr - 0x13FF0020, htobe32(val));
|
||||
break;
|
||||
case 0x1FC007C0 ... 0x1FC007FF:
|
||||
util::WriteAccess<u32>(pifRam, paddr - 0x1FC007C0, htobe32(val));
|
||||
ProcessPIFCommands(pifRam, mmio.si.controller, *this);
|
||||
break;
|
||||
case 0x00800000 ... 0x03FFFFFF: case 0x04200000 ... 0x042FFFFF:
|
||||
case 0x08000000 ... 0x0FFFFFFF: case 0x04900000 ... 0x07FFFFFF:
|
||||
case 0x1FC00800 ... 0x7FFFFFFF: case 0x80000000 ... 0xFFFFFFFF: break;
|
||||
default: util::panic("Unimplemented 32-bit write at address {:08X} with value {:0X} (PC = {:016X})\n", paddr, val, (u64)regs.pc);
|
||||
if(pointer) {
|
||||
util::WriteAccess<u32>((u8*)pointer, offset, val);
|
||||
} else {
|
||||
u32 paddr = vaddr;
|
||||
if(!MapVAddr<tlb>(regs, STORE, vaddr, paddr)) {
|
||||
HandleTLBException(regs, vaddr);
|
||||
FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, STORE), 0, pc);
|
||||
}
|
||||
|
||||
switch(paddr) {
|
||||
case 0x00000000 ... 0x007FFFFF:
|
||||
util::WriteAccess<u32>(mmio.rdp.dram.data(), paddr, val);
|
||||
break;
|
||||
case 0x04000000 ... 0x0403FFFF:
|
||||
if(paddr & 0x1000)
|
||||
util::WriteAccess<u32>(mmio.rsp.imem, paddr & IMEM_DSIZE, val);
|
||||
else
|
||||
util::WriteAccess<u32>(mmio.rsp.dmem, paddr & DMEM_DSIZE, val);
|
||||
break;
|
||||
case 0x04040000 ... 0x040FFFFF: case 0x04100000 ... 0x041FFFFF:
|
||||
case 0x04300000 ... 0x044FFFFF: case 0x04500000 ... 0x048FFFFF: mmio.Write(*this, regs, paddr, val); break;
|
||||
case 0x10000000 ... 0x13FF0013: break;
|
||||
case 0x13FF0014: {
|
||||
if(val < ISVIEWER_SIZE) {
|
||||
char* message = (char*)calloc(val + 1, 1);
|
||||
memcpy(message, isviewer, val);
|
||||
fmt::print("{}", message);
|
||||
free(message);
|
||||
}
|
||||
} break;
|
||||
case 0x13FF0020 ... 0x13FFFFFF:
|
||||
util::WriteAccess<u32>(isviewer, paddr - 0x13FF0020, htobe32(val));
|
||||
break;
|
||||
case 0x1FC007C0 ... 0x1FC007FF:
|
||||
util::WriteAccess<u32>(pifRam, paddr - 0x1FC007C0, htobe32(val));
|
||||
ProcessPIFCommands(pifRam, mmio.si.controller, *this);
|
||||
break;
|
||||
case 0x00800000 ... 0x03FFFFFF: case 0x04200000 ... 0x042FFFFF:
|
||||
case 0x08000000 ... 0x0FFFFFFF: case 0x04900000 ... 0x07FFFFFF:
|
||||
case 0x1FC00800 ... 0x7FFFFFFF: case 0x80000000 ... 0xFFFFFFFF: break;
|
||||
default: util::panic("Unimplemented 32-bit write at address {:08X} with value {:0X} (PC = {:016X})\n", paddr, val, (u64)regs.pc);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
template <bool tlb>
|
||||
void Mem::Write64(Registers& regs, u64 vaddr, u64 val, s64 pc) {
|
||||
u32 paddr = vaddr;
|
||||
if(!MapVAddr<tlb>(regs, STORE, vaddr, paddr)) {
|
||||
HandleTLBException(regs, vaddr);
|
||||
FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, STORE), 0, pc);
|
||||
}
|
||||
const auto page = (vaddr & 0xFFFFFFFF) >> 12;
|
||||
const auto offset = vaddr & 0xFFF;
|
||||
const auto pointer = writePages[page];
|
||||
|
||||
switch(paddr) {
|
||||
case 0x00000000 ... 0x007FFFFF:
|
||||
util::WriteAccess<u64>(mmio.rdp.dram.data(), paddr, val);
|
||||
break;
|
||||
case 0x04000000 ... 0x0403FFFF:
|
||||
val >>= 32;
|
||||
if(paddr & 0x1000)
|
||||
util::WriteAccess<u32>(mmio.rsp.imem, paddr & IMEM_DSIZE, val);
|
||||
else
|
||||
util::WriteAccess<u32>(mmio.rsp.dmem, paddr & DMEM_DSIZE, val);
|
||||
break;
|
||||
case 0x04040000 ... 0x040FFFFF: case 0x04100000 ... 0x041FFFFF:
|
||||
case 0x04300000 ... 0x044FFFFF: case 0x04500000 ... 0x048FFFFF: util::panic("MMIO Write64!\n");
|
||||
case 0x10000000 ... 0x13FFFFFF: break;
|
||||
case 0x1FC007C0 ... 0x1FC007FF:
|
||||
util::WriteAccess<u64>(pifRam, paddr - 0x1FC007C0, htobe64(val));
|
||||
ProcessPIFCommands(pifRam, mmio.si.controller, *this);
|
||||
break;
|
||||
case 0x00800000 ... 0x03FFFFFF: case 0x04200000 ... 0x042FFFFF:
|
||||
case 0x08000000 ... 0x0FFFFFFF: case 0x04900000 ... 0x07FFFFFF:
|
||||
case 0x1FC00800 ... 0x7FFFFFFF: case 0x80000000 ... 0xFFFFFFFF: break;
|
||||
default: util::panic("Unimplemented 64-bit write at address {:08X} with value {:0X} (PC = {:016X})\n", paddr, val, (u64)regs.pc);
|
||||
if(pointer) {
|
||||
util::WriteAccess<u64>((u8*)pointer, offset, val);
|
||||
} else {
|
||||
u32 paddr = vaddr;
|
||||
if (!MapVAddr<tlb>(regs, STORE, vaddr, paddr)) {
|
||||
HandleTLBException(regs, vaddr);
|
||||
FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, STORE), 0, pc);
|
||||
}
|
||||
|
||||
switch (paddr) {
|
||||
case 0x00000000 ... 0x007FFFFF:
|
||||
util::WriteAccess<u64>(mmio.rdp.dram.data(), paddr, val);
|
||||
break;
|
||||
case 0x04000000 ... 0x0403FFFF:
|
||||
val >>= 32;
|
||||
if (paddr & 0x1000)
|
||||
util::WriteAccess<u32>(mmio.rsp.imem, paddr & IMEM_DSIZE, val);
|
||||
else
|
||||
util::WriteAccess<u32>(mmio.rsp.dmem, paddr & DMEM_DSIZE, val);
|
||||
break;
|
||||
case 0x04040000 ... 0x040FFFFF:
|
||||
case 0x04100000 ... 0x041FFFFF:
|
||||
case 0x04300000 ... 0x044FFFFF:
|
||||
case 0x04500000 ... 0x048FFFFF:
|
||||
util::panic("MMIO Write64!\n");
|
||||
case 0x10000000 ... 0x13FFFFFF:
|
||||
break;
|
||||
case 0x1FC007C0 ... 0x1FC007FF:
|
||||
util::WriteAccess<u64>(pifRam, paddr - 0x1FC007C0, htobe64(val));
|
||||
ProcessPIFCommands(pifRam, mmio.si.controller, *this);
|
||||
break;
|
||||
case 0x00800000 ... 0x03FFFFFF:
|
||||
case 0x04200000 ... 0x042FFFFF:
|
||||
case 0x08000000 ... 0x0FFFFFFF:
|
||||
case 0x04900000 ... 0x07FFFFFF:
|
||||
case 0x1FC00800 ... 0x7FFFFFFF:
|
||||
case 0x80000000 ... 0xFFFFFFFF:
|
||||
break;
|
||||
default:
|
||||
util::panic("Unimplemented 64-bit write at address {:08X} with value {:0X} (PC = {:016X})\n", paddr, val,
|
||||
(u64) regs.pc);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@@ -82,6 +82,7 @@ private:
|
||||
std::vector<u8> cart, sram;
|
||||
u8 pifBootrom[PIF_BOOTROM_SIZE]{};
|
||||
u8 isviewer[ISVIEWER_SIZE]{};
|
||||
std::vector<uintptr_t> writePages, readPages;
|
||||
size_t romMask;
|
||||
|
||||
void SetCICType(u32& cicType, u32 checksum) {
|
||||
|
||||
@@ -29,4 +29,20 @@
|
||||
#define SRAM_REGION 0x08000000 ... 0x0FFFFFFF
|
||||
#define CART_REGION 0x10000000 ... 0x1FBFFFFF
|
||||
#define PIF_ROM_REGION 0x1FC00000 ... 0x1FC007BF
|
||||
#define PIF_RAM_REGION 0x1FC007C0 ... 0x1FC007FF
|
||||
#define PIF_RAM_REGION 0x1FC007C0 ... 0x1FC007FF
|
||||
|
||||
constexpr size_t operator""_kb(unsigned long long int x) {
|
||||
return 1024ULL * x;
|
||||
}
|
||||
|
||||
constexpr size_t operator""_mb(unsigned long long int x) {
|
||||
return 1024_kb * x;
|
||||
}
|
||||
|
||||
constexpr size_t operator""_gb(unsigned long long int x) {
|
||||
return 1024_mb * x;
|
||||
}
|
||||
|
||||
#define ADDRESS_RANGE_SIZE 4_gb
|
||||
#define PAGE_SIZE 4_kb
|
||||
#define PAGE_COUNT ((ADDRESS_RANGE_SIZE) / (PAGE_SIZE))
|
||||
Reference in New Issue
Block a user