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Merge commit '16a2cf3873e00fa08e587d1b05c9132d98c24f50' into back-to-imgui

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irisz64
2025-06-26 22:15:44 +02:00
parent 2ec3abbe14 16a2cf3873
commit e13270e41e
876 changed files with 168071 additions and 411897 deletions
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2
external/capstone/.clang-format vendored
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@@ -1,4 +1,4 @@
# SPDX-License-Identifier: GPL-2.0
# SPDX-License-Identifier: BSD-3-Clause
#
# clang-format configuration file. Intended for clang-format >= 11.
#

7
external/capstone/.github/labeler.yml vendored
View File

@@ -48,6 +48,13 @@ Alpha:
- tests/MC/Alpha/**
- tests/details/alpha.yaml
ARC:
- arch/ARC/*
- cstool/cstool_arc.c
- include/capstone/arc.h
- suite/MC/ARC/*
- tests/test_arc.c
BPF:
- arch/BPF/**
- cstool/cstool_bpf.c

39
external/capstone/.github/workflows/CITest.yml vendored
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@@ -50,7 +50,28 @@ jobs:
arch: x64,
build-system: 'cmake',
diet-build: 'OFF',
enable-asan: 'OFF'
enable-asan: 'OFF',
build_type: 'Debug'
}
- {
name: 'ubuntu-22.04 x64 release - assert warn',
os: ubuntu-22.04,
arch: x64,
build-system: 'cmake',
diet-build: 'OFF',
enable-asan: 'OFF',
build_type: 'Release',
build_options: '-DCAPSTONE_ASSERTION_WARNINGS=ON'
}
- {
name: 'ubuntu-22.04 x64 release - no asserts',
os: ubuntu-22.04,
arch: x64,
build-system: 'cmake',
diet-build: 'OFF',
enable-asan: 'OFF',
build_type: 'Release',
build_options: '-DCAPSTONE_ASSERTION_WARNINGS=OFF'
}
- {
name: 'ubuntu-24.04 x64 ASAN',
@@ -58,7 +79,8 @@ jobs:
arch: x64,
build-system: 'cmake',
diet-build: 'OFF',
enable-asan: 'ON'
enable-asan: 'ON',
build_type: 'Debug'
}
steps:
@@ -85,14 +107,16 @@ jobs:
if: startsWith(matrix.config.build-system, 'cmake')
env:
asan: ${{ matrix.config.enable-asan }}
build_option: ${{ matrix.config.build_option }}
build_type: ${{ matrix.config.build_type }}
run: |
mkdir build && cd build
# build static library
cmake -DCAPSTONE_INSTALL=1 -DCMAKE_INSTALL_PREFIX=/usr -DENABLE_ASAN=${asan} -DCAPSTONE_BUILD_DIET=${diet_build} ..
cmake --build . --config Debug
cmake -DCAPSTONE_INSTALL=1 -DCMAKE_INSTALL_PREFIX=/usr -DENABLE_ASAN=${asan} -DCAPSTONE_BUILD_DIET=${diet_build} ${build_option} ..
cmake --build . --config ${build_type}
# build shared library
cmake -DCAPSTONE_INSTALL=1 -DCAPSTONE_BUILD_SHARED_LIBS=1 -DCMAKE_INSTALL_PREFIX=/usr -DCAPSTONE_BUILD_CSTEST=ON -DENABLE_ASAN=${asan} ..
sudo cmake --build . --config Debug --target install
cmake -DCAPSTONE_INSTALL=1 -DCAPSTONE_BUILD_SHARED_LIBS=1 -DCMAKE_INSTALL_PREFIX=/usr -DCAPSTONE_BUILD_CSTEST=ON -DENABLE_ASAN=${asan} ${build_option} ..
sudo cmake --build . --config ${build_type} --target install
- name: Lower number of KASL randomized address bits
run: |
@@ -141,7 +165,8 @@ jobs:
- name: Valgrind cstest
if: startsWith(matrix.config.build-system, 'cmake') && startsWith(matrix.config.enable-asan, 'OFF')
run: |
sudo apt-get install valgrind
sudo apt-get -y update
sudo apt-get -y install valgrind
valgrind cstest tests
- name: Comaptibility header generation

4
external/capstone/.github/workflows/auto-sync.yml vendored
View File

@@ -55,7 +55,7 @@ jobs:
cd vendor/llvm_root
mkdir build
cd build
cmake -G Ninja -DCMAKE_BUILD_TYPE=Debug ../llvm
cmake -G Ninja -DCMAKE_BUILD_TYPE=Debug -DLLVM_EXPERIMENTAL_TARGETS_TO_BUILD=ARC ../llvm
cmake --build . --target llvm-tblgen --config Debug
cd ../../../
@@ -74,6 +74,7 @@ jobs:
run: |
./src/autosync/ASUpdater.py -d -a AArch64 -s IncGen
./src/autosync/ASUpdater.py -d -a Alpha -s IncGen
./src/autosync/ASUpdater.py -d -a ARC -s IncGen
./src/autosync/ASUpdater.py -d -a ARM -s IncGen
./src/autosync/ASUpdater.py -d -a PPC -s IncGen
./src/autosync/ASUpdater.py -d -a LoongArch -s IncGen
@@ -93,6 +94,7 @@ jobs:
- name: CppTranslator - Test translation
run: |
./src/autosync/ASUpdater.py --ci -d -a AArch64 -s Translate
./src/autosync/ASUpdater.py --ci -d -a ARC -s Translate
./src/autosync/ASUpdater.py --ci -d -a ARM -s Translate
./src/autosync/ASUpdater.py --ci -d -a PPC -s Translate
./src/autosync/ASUpdater.py --ci -d -a LoongArch -s Translate

148
external/capstone/.github/workflows/build-wheels-publish.yml vendored
View File

@@ -34,8 +34,7 @@ env:
CAPSTONE_DEBUG: ${{ inputs.debugMode != '' && inputs.debugMode || startsWith(github.ref, 'refs/tags') && '0' || '1' }}
jobs:
# job to be executed for every push - testing purpose
build_wheels_always:
build_and_test_wheels:
name: Building on ${{ matrix.os }} - ${{ matrix.arch }} - ${{ matrix.cibw_build }}
runs-on: ${{ matrix.os }}
strategy:
@@ -44,28 +43,27 @@ jobs:
include:
# NOTE: Making this to parallelize and speed up workflow
# i686 - manylinux
# - { os: ubuntu-latest, arch: i686, cibw_build: 'cp38-manylinux* cp313-manylinux*', cibw_skip: '' }
# - { os: ubuntu-latest, arch: i686, cibw_build: 'cp*-manylinux*', cibw_skip: '*36* *37*' }
# i686 - musllinux
# - { os: ubuntu-latest, arch: i686, cibw_build: 'cp38-musllinux* cp313-musllinux*', cibw_skip: '' }
# - { os: ubuntu-latest, arch: i686, cibw_build: 'cp*-musllinux*', cibw_skip: '*36* *37*' }
# x86_64 - manylinux
- { os: ubuntu-latest, arch: x86_64, cibw_build: 'cp38-manylinux* cp313-manylinux*', cibw_skip: '' }
- { os: ubuntu-latest, arch: x86_64, cibw_build: 'cp*-manylinux*', cibw_skip: '*36* *37*' }
# x86_64 - musllinux
- { os: ubuntu-latest, arch: x86_64, cibw_build: 'cp38-musllinux* cp313-musllinux*', cibw_skip: '' }
- { os: ubuntu-latest, arch: x86_64, cibw_build: 'cp*-musllinux*', cibw_skip: '*36* *37*' }
# aarch64 - manylinux
- { os: ubuntu-latest, arch: aarch64, cibw_build: 'cp38-manylinux* cp313-manylinux*', cibw_skip: '' }
- { os: ubuntu-24.04-arm, arch: aarch64, cibw_build: 'cp*-manylinux*', cibw_skip: '*36* *37*' }
# aarch64 - musllinux
- { os: ubuntu-latest, arch: aarch64, cibw_build: 'cp38-musllinux* cp313-musllinux*', cibw_skip: '' }
- { os: ubuntu-24.04-arm, arch: aarch64, cibw_build: 'cp*-musllinux*', cibw_skip: '*36* *37*' }
# macos - x86_64
- { os: macos-13, arch: x86_64, cibw_build: 'cp38* cp313*', cibw_skip: '' }
- { os: macos-13, arch: x86_64, cibw_build: 'cp*', cibw_skip: '*36* *37*' }
# macos - arm64
- { os: macos-latest, arch: arm64, cibw_build: 'cp38* cp313*', cibw_skip: '' }
- { os: macos-latest, arch: universal2, cibw_build: 'cp38* cp313*', cibw_skip: '' }
# windows - x86_64
- { os: windows-latest, arch: AMD64, cibw_build: 'cp38* cp313*', cibw_skip: '' }
- { os: macos-latest, arch: arm64, cibw_build: 'cp*', cibw_skip: '*36* *37*' }
# windows - amd64
# - { os: windows-latest, arch: x86, cibw_build: 'cp38* cp313*', cibw_skip: '' }
- { os: windows-latest, arch: AMD64, cibw_build: 'cp*', cibw_skip: '*36* *37*' }
# windows - x86
# - { os: windows-latest, arch: x86, cibw_build: 'cp*', cibw_skip: '*36* *37*' }
# windows - arm64
- { os: windows-latest, arch: ARM64, cibw_build: 'cp39* cp313*', cibw_skip: '' }
- { os: windows-latest, arch: ARM64, cibw_build: 'cp*', cibw_skip: '*36* *37* *38*' }
steps:
- uses: actions/checkout@v4
@@ -104,11 +102,11 @@ jobs:
arch: amd64_arm64
- name: '🛠️ Set up QEMU'
if: runner.os == 'Linux' && matrix.arch != 'x86_64'
if: runner.os == 'Linux' && matrix.arch == 'i686'
uses: docker/setup-qemu-action@v3
- name: '🚧 cibuildwheel run'
uses: pypa/cibuildwheel@v2.22.0
uses: pypa/cibuildwheel@v2.23.3
env:
CIBW_BUILD_FRONTEND: build
CIBW_BUILD: ${{ matrix.cibw_build }}
@@ -131,115 +129,6 @@ jobs:
name: ${{ env.ARTIFACT_NAME }}
path: ./wheelhouse/*.whl
# To be executed only in case of a tag release
build_wheels_all:
name: Building on ${{ matrix.os }} - ${{ matrix.arch }} - ${{ matrix.cibw_build }}
runs-on: ${{ matrix.os }}
if: startsWith(github.ref, 'refs/tags')
strategy:
fail-fast: false
matrix:
include:
# NOTE: Making this to parallelize and speed up workflow
# i686 - manylinux
# - { os: ubuntu-latest, arch: i686, cibw_build: 'cp39-manylinux*', cibw_skip: '' }
# - { os: ubuntu-latest, arch: i686, cibw_build: 'cp310-manylinux*', cibw_skip: '' }
# - { os: ubuntu-latest, arch: i686, cibw_build: 'cp311-manylinux*', cibw_skip: '' }
# - { os: ubuntu-latest, arch: i686, cibw_build: 'cp312-manylinux*', cibw_skip: '' }
# i686 - musllinux
# - { os: ubuntu-latest, arch: i686, cibw_build: 'cp39-musllinux*', cibw_skip: '' }
# - { os: ubuntu-latest, arch: i686, cibw_build: 'cp310-musllinux*', cibw_skip: '' }
# - { os: ubuntu-latest, arch: i686, cibw_build: 'cp311-musllinux*', cibw_skip: '' }
# - { os: ubuntu-latest, arch: i686, cibw_build: 'cp312-musllinux*', cibw_skip: '' }
# x86_64 - manylinux
- { os: ubuntu-latest, arch: x86_64, cibw_build: 'cp39-manylinux*', cibw_skip: '' }
- { os: ubuntu-latest, arch: x86_64, cibw_build: 'cp310-manylinux*', cibw_skip: '' }
- { os: ubuntu-latest, arch: x86_64, cibw_build: 'cp311-manylinux*', cibw_skip: '' }
- { os: ubuntu-latest, arch: x86_64, cibw_build: 'cp312-manylinux*', cibw_skip: '' }
# x86_64 - musllinux
- { os: ubuntu-latest, arch: x86_64, cibw_build: 'cp39-musllinux*', cibw_skip: '' }
- { os: ubuntu-latest, arch: x86_64, cibw_build: 'cp310-musllinux*', cibw_skip: '' }
- { os: ubuntu-latest, arch: x86_64, cibw_build: 'cp311-musllinux*', cibw_skip: '' }
- { os: ubuntu-latest, arch: x86_64, cibw_build: 'cp312-musllinux*', cibw_skip: '' }
# aarch64 - manylinux
- { os: ubuntu-latest, arch: aarch64, cibw_build: 'cp39-manylinux*', cibw_skip: '' }
- { os: ubuntu-latest, arch: aarch64, cibw_build: 'cp310-manylinux*', cibw_skip: '' }
- { os: ubuntu-latest, arch: aarch64, cibw_build: 'cp311-manylinux*', cibw_skip: '' }
- { os: ubuntu-latest, arch: aarch64, cibw_build: 'cp312-manylinux*', cibw_skip: '' }
# aarch64 - musllinux
- { os: ubuntu-latest, arch: aarch64, cibw_build: 'cp39-musllinux*', cibw_skip: '' }
- { os: ubuntu-latest, arch: aarch64, cibw_build: 'cp310-musllinux*', cibw_skip: '' }
- { os: ubuntu-latest, arch: aarch64, cibw_build: 'cp311-musllinux*', cibw_skip: '' }
- { os: ubuntu-latest, arch: aarch64, cibw_build: 'cp312-musllinux*', cibw_skip: '' }
# macos - x86_64
- { os: macos-13, arch: x86_64, cibw_build: 'cp*', cibw_skip: '*36* *37* *38* *313*' }
# macos - arm64
- { os: macos-latest, arch: arm64, cibw_build: 'cp*', cibw_skip: '*36* *37* *38* *313*' }
- { os: macos-latest, arch: universal2, cibw_build: 'cp*', cibw_skip: '*36* *37* *38* *39* *313*' }
# windows - amd64
- { os: windows-latest, arch: AMD64, cibw_build: 'cp*', cibw_skip: '*36* *37* *38* *313*' }
# windows - x86
# - { os: windows-latest, arch: x86, cibw_build: 'cp*', cibw_skip: '*36* *37* *38* *313*' }
# windows - arm64
- { os: windows-latest, arch: ARM64, cibw_build: 'cp*', cibw_skip: '*36* *37* *38* *39* *313*' }
steps:
- uses: actions/checkout@v4
# https://github.com/actions/upload-artifact/issues/22
- name: Prepare a unique name for Artifacts
shell: bash
run: |
# replace not-allowed chars with dash
name="cibw-wheels-${{ matrix.os }}-${{ matrix.arch }}-${{ matrix.cibw_build }}"
name=$(echo -n "$name" | sed -e 's/[ \t:\/\\"<>|*?]/-/g' -e 's/--*/-/g' | sed -e 's/\-$//')
echo "ARTIFACT_NAME=$name" >> $GITHUB_ENV
- name: '🛠️ Win MSVC 32 dev cmd setup'
if: runner.os == 'Windows' && matrix.arch == 'x86'
uses: ilammy/msvc-dev-cmd@v1
with:
arch: x86
- name: '🛠️ Win MSVC 64 dev cmd setup'
if: runner.os == 'Windows' && matrix.arch == 'AMD64'
uses: ilammy/msvc-dev-cmd@v1
with:
arch: x64
- name: '🛠️ Win MSVC ARM64 dev cmd setup'
if: runner.os == 'Windows' && matrix.arch == 'ARM64'
uses: ilammy/msvc-dev-cmd@v1
with:
arch: amd64_arm64
- name: '🛠️ Set up QEMU'
if: runner.os == 'Linux' && matrix.arch != 'x86_64'
uses: docker/setup-qemu-action@v3
- name: '🚧 cibuildwheel run'
uses: pypa/cibuildwheel@v2.22.0
env:
CIBW_BUILD_FRONTEND: build
CIBW_BUILD: ${{ matrix.cibw_build }}
CIBW_SKIP: ${{ matrix.cibw_skip }}
CIBW_ARCHS: ${{ matrix.arch }}
CIBW_ENVIRONMENT: DEBUG=${{ env.CAPSTONE_DEBUG }}
CIBW_ENVIRONMENT_PASS_LINUX: DEBUG
# https://cibuildwheel.pypa.io/en/stable/faq/#windows-arm64
CIBW_TEST_SKIP: "*-win_arm64"
CIBW_TEST_COMMAND: >
python -m pip install {package}/cstest_py &&
python {project}/suite/run_tests.py
with:
package-dir: bindings/python
output-dir: wheelhouse
- uses: actions/upload-artifact@v4
with:
name: ${{ env.ARTIFACT_NAME }}
path: ./wheelhouse/*.whl
make_sdist:
name: Make SDist
runs-on: ubuntu-latest
@@ -251,9 +140,10 @@ jobs:
- name: Build SDist
run: |
cd bindings/python
python3 -m pip install -U pip build
python3 -m build --sdist
python3 -m build --sdist bindings/python
python3 -m pip install bindings/python/dist/*.tar.gz
python3 -c 'import capstone; print(f"Capstone version installed from sdist: {capstone.__version__}")'
- uses: actions/upload-artifact@v4
with:
@@ -261,7 +151,7 @@ jobs:
path: bindings/python/dist/*.tar.gz
publish:
needs: [ build_wheels_always, build_wheels_all, make_sdist ]
needs: [ build_and_test_wheels, make_sdist ]
environment: pypi
permissions:
id-token: write

91
external/capstone/.github/workflows/build_release.yml vendored
View File

@@ -15,29 +15,6 @@ jobs:
with:
submodules: true
- name: Make setup.sh and check_capstone.sh are executable
run: |
chmod +x ./packages/deb/setup.sh
chmod +x ./packages/deb/check_capstone.sh
- name: Build Debian Package
working-directory: ./packages/deb
run: ./setup.sh ${{ github.event.release.tag_name }}
- name: Run sanity checks on the Debian package
working-directory: ./packages/deb
run: |
./check_capstone.sh ./libcapstone-dev_${{ github.event.release.tag_name }}_amd64.deb
- name: Upload debian package to release
uses: softprops/action-gh-release@v2
env:
GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
with:
tag_name: ${{ github.event.release.tag_name }}
files: |
./packages/deb/*.deb
- name: Create archive
id: archive
run: |
@@ -45,10 +22,9 @@ jobs:
PKGNAME="capstone-$VERSION"
SHASUM=$PKGNAME.tar.xz.sha256
mkdir -p /tmp/$PKGNAME
mv * /tmp/$PKGNAME
mv /tmp/$PKGNAME .
rsync -a --exclude=build --exclude='.*' ./ /tmp/$PKGNAME/
TARBALL=$PKGNAME.tar.xz
tar cJf $TARBALL $PKGNAME
tar -C /tmp -cJf $TARBALL $PKGNAME
sha256sum $TARBALL > $SHASUM
echo "tarball=$TARBALL" >> $GITHUB_OUTPUT
echo "shasum=$SHASUM" >> $GITHUB_OUTPUT
@@ -62,3 +38,66 @@ jobs:
files: |
${{ steps.archive.outputs.tarball }}
${{ steps.archive.outputs.shasum }}
- name: Configure CMake and build the project
run: |
cmake -B build \
-DPROJECT_VERSION=${{ github.event.release.tag_name }} \
-DCMAKE_BUILD_TYPE=Release \
-DCAPSTONE_BUILD_SHARED_LIBS=1 \
-DCMAKE_INSTALL_PREFIX=/usr
cmake --build build
- name: Package DEB and RPM package
run: |
cd build
cpack -G DEB
cpack -G RPM
- name: Upload debian package to release
uses: softprops/action-gh-release@v2
env:
GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
with:
tag_name: ${{ github.event.release.tag_name }}
files: |
./build/*.deb
./build/*.rpm
build_windows:
name: build_windows
runs-on: windows-latest
steps:
- uses: actions/checkout@v4
with:
submodules: true
- name: Win MSVC 64 dev cmd setup
uses: ilammy/msvc-dev-cmd@v1
with:
arch: x64
- name: Configure CMake and build the project
run: |
cmake -B build `
-T "ClangCL,host=x64" `
-A x64 `
-DPROJECT_VERSION="${{ github.event.release.tag_name }}" `
-DCMAKE_BUILD_TYPE=Release `
-DCAPSTONE_BUILD_SHARED_LIBS=1
cmake --build build --config Release
cmake --install build --config Release
- name: Package NSIS installer
run: |
cd build
cpack -G NSIS
- name: Upload NSIS installer to release
uses: softprops/action-gh-release@v2
env:
GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
with:
tag_name: ${{ github.event.release.tag_name }}
files: |
./build/*.exe

2
external/capstone/.github/workflows/labeler.yml vendored
View File

@@ -14,7 +14,7 @@ jobs:
pull-requests: write
runs-on: ubuntu-22.04
steps:
- uses: actions/labeler@v5
- uses: actions/labeler@v4
with:
repo-token: "${{ secrets.GITHUB_TOKEN }}"

1
external/capstone/.gitignore vendored
View File

@@ -79,6 +79,7 @@ tests/test_riscv
tests/test_sh
tests/test_alpha
tests/test_hppa
tests/test_arc
# regress binaries
suite/regress/invalid_read_in_print_operand

66
external/capstone/.travis.yml vendored
View File

@@ -1,66 +0,0 @@
language: cpp
sudo: false
before_install:
- export LD_LIBRARY_PATH=`pwd`/tests/:$LD_LIBRARY_PATH
before_script:
- wget https://github.com/groundx/capstonefuzz/raw/master/corpus/corpus-libFuzzer-capstone_fuzz_disasmnext-latest.zip
- unzip -q corpus-libFuzzer-capstone_fuzz_disasmnext-latest.zip -d suite/fuzz
# TODO remove built in cmocka compile and use system cmocka (including brewfile) once xenial is default
- git clone https://git.cryptomilk.org/projects/cmocka.git suite/cstest/cmocka
- chmod +x suite/cstest/build_cstest.sh
- if [[ ${TRAVIS_OS_NAME} = linux ]]; then export PATH="/usr/lib/llvm-9/bin:${PATH}"; fi
script:
- ./make.sh
- make check
- sudo make install
- if [[ "$TRAVIS_OS_NAME" == "linux" ]]; then cp libcapstone.so.* bindings/python/libcapstone.so; fi
- if [[ "$TRAVIS_OS_NAME" == "osx" ]]; then cp libcapstone.*.dylib bindings/python/libcapstone.dylib; fi
- if [[ "$NOPYTEST" != "true" ]]; then cd bindings/python && make check; cd ../..; fi
- if [[ "$NOPYTEST" != "true" ]]; then cd suite/cstest && ./build_cstest.sh; fi
- if [[ "$NOPYTEST" != "true" ]]; then python cstest_report.py -D -t build/cstest -d ../MC; fi
- if [[ "$NOPYTEST" != "true" ]]; then python cstest_report.py -D -t build/cstest -f issues.cs; fi
- if [ -n "$QA_FUZZIT" ]; then suite/fuzz/fuzzit.sh; fi
compiler:
- clang
- gcc
os:
- linux
- osx
matrix:
include:
- name: xenial gcc
os: linux
dist: xenial
compiler: gcc
addons:
apt:
packages:
- libcmocka-dev
- name: xenial clang
os: linux
dist: xenial
compiler: clang
addons:
apt:
packages:
- libcmocka-dev
- name: fuzza
env: ASAN_OPTIONS=detect_leaks=0 CXXFLAGS="-DFUZZING_BUILD_MODE_UNSAFE_FOR_PRODUCTION -fsanitize=address -fsanitize=fuzzer-no-link" CFLAGS="-DFUZZING_BUILD_MODE_UNSAFE_FOR_PRODUCTION -fsanitize=address -fsanitize=fuzzer-no-link" LDFLAGS="-fsanitize=address" NOPYTEST=true QA_FUZZIT=asan
compiler: clang
os: linux
- name: fuzzm
env: CXXFLAGS="-DFUZZING_BUILD_MODE_UNSAFE_FOR_PRODUCTION -fsanitize=memory -fsanitize=fuzzer-no-link" CFLAGS="-DFUZZING_BUILD_MODE_UNSAFE_FOR_PRODUCTION -fsanitize=memory -fsanitize=fuzzer-no-link" LDFLAGS="-fsanitize=memory" NOPYTEST=true QA_FUZZIT=msan
compiler: clang
os: linux
- name: fuzzu
env: CXXFLAGS="-DFUZZING_BUILD_MODE_UNSAFE_FOR_PRODUCTION -fsanitize=undefined -fsanitize=fuzzer-no-link" CFLAGS="-DFUZZING_BUILD_MODE_UNSAFE_FOR_PRODUCTION -fsanitize=undefined -fno-sanitize-recover=undefined,integer -fsanitize=fuzzer-no-link" LDFLAGS="-fsanitize=undefined" NOPYTEST=true QA_FUZZIT=ubsan
compiler: clang
os: linux
addons:
apt:
sources:
- llvm-toolchain-trusty
- ubuntu-toolchain-r-test
packages:
- clang-9

11
external/capstone/BUILDING.md vendored
View File

@@ -12,6 +12,16 @@ cmake --build build
cmake --install build --prefix "<install-prefix>"
```
To create rpm, debian and OSX packages, run the following
```bash
cmake -B build -DCMAKE_BUILD_TYPE=Release -DCAPSTONE_BUILD_SHARED_LIBS=1 -DCMAKE_INSTALL_PREFIX=/usr
cmake --build build
cd build
cpack -G DEB
cpack -G RPM
cpack -G DragNDrop
```
**Windows**
```bash
@@ -34,6 +44,7 @@ By default all are enabled.
- `CAPSTONE_ARM_SUPPORT`: Support ARM.
- `CAPSTONE_AARCH64_SUPPORT`: Support AARCH64.
- `CAPSTONE_ALPHA_SUPPORT`: Support Alpha.
- `CAPSTONE_ARC_SUPPORT`: Support ARC.
- `CAPSTONE_HPPA_SUPPORT`: Support HPPA.
- `CAPSTONE_LOONGARCH_SUPPORT`: Support LoongArch.
- `CAPSTONE_M680X_SUPPORT`: Support M680X.

78
external/capstone/CMakeLists.txt vendored
View File

@@ -20,15 +20,21 @@ endif()
cmake_policy(SET CMP0042 NEW)
# Check if VERSION is provided externally, otherwise default to 6.0.0
if(NOT DEFINED PROJECT_VERSION)
if(NOT DEFINED PROJECT_VERSION OR PROJECT_VERSION STREQUAL "")
set(PROJECT_VERSION "6.0.0")
endif()
# Extract the major, minor, and patch versions
string(REGEX MATCH "^[0-9]+\\.[0-9]+\\.[0-9]+" PROJECT_VERSION_BASE ${PROJECT_VERSION})
# Remove the 'v' prefix if it exists and extract the major, minor, and patch versions
string(REGEX MATCH "^[vV]?([0-9]+\\.[0-9]+\\.[0-9]+)" _ ${PROJECT_VERSION})
set(PROJECT_VERSION_BASE ${CMAKE_MATCH_1})
# Use PROJECT_VERSION directly for CPack
set(CPACK_PACKAGE_VERSION ${PROJECT_VERSION})
# Set the project version without the pre-release identifier
project(capstone VERSION ${PROJECT_VERSION_BASE})
# Print the values of PROJECT_VERSION and PROJECT_VERSION_BASE
message(STATUS "PROJECT_VERSION: ${CPACK_PACKAGE_VERSION} CAPSTONE_VERSION: ${PROJECT_VERSION_BASE}")
set(UNIX_COMPILER_OPTIONS -Werror -Warray-bounds -Wshift-negative-value -Wreturn-type -Wformat -Wmissing-braces -Warray-bounds -Wunused-variable -Wparentheses -Wint-in-bool-context -Wmisleading-indentation)
@@ -73,6 +79,7 @@ option(CAPSTONE_USE_DEFAULT_ALLOC "Use default memory allocation functions" ON)
option(CAPSTONE_USE_ARCH_REGISTRATION "Use explicit architecture registration" OFF)
option(CAPSTONE_ARCHITECTURE_DEFAULT "Whether architectures are enabled by default" ON)
option(CAPSTONE_DEBUG "Whether to enable extra debug assertions (enabled with CMAKE_BUILD_TYPE=Debug)" OFF)
option(CAPSTONE_ASSERTION_WARNINGS "Warns about hit assertions in release builds." OFF)
option(CAPSTONE_INSTALL "Generate install target" ${PROJECT_IS_TOP_LEVEL})
option(ENABLE_ASAN "Enable address sanitizer" OFF)
option(ENABLE_COVERAGE "Enable test coverage" OFF)
@@ -99,8 +106,8 @@ if(APPLE AND NOT CAPSTONE_BUILD_MACOS_THIN)
set(CMAKE_OSX_ARCHITECTURES "x86_64;arm64")
endif()
set(SUPPORTED_ARCHITECTURES ARM AARCH64 M68K MIPS PPC SPARC SYSTEMZ XCORE X86 TMS320C64X M680X EVM MOS65XX WASM BPF RISCV SH TRICORE ALPHA HPPA LOONGARCH XTENSA)
set(SUPPORTED_ARCHITECTURE_LABELS ARM AARCH64 M68K MIPS PowerPC Sparc SystemZ XCore x86 TMS320C64x M680x EVM MOS65XX WASM BPF RISCV SH TriCore Alpha HPPA LoongArch Xtensa)
set(SUPPORTED_ARCHITECTURES ARM AARCH64 M68K MIPS PPC SPARC SYSTEMZ XCORE X86 TMS320C64X M680X EVM MOS65XX WASM BPF RISCV SH TRICORE ALPHA HPPA LOONGARCH XTENSA ARC)
set(SUPPORTED_ARCHITECTURE_LABELS ARM AARCH64 M68K MIPS PowerPC Sparc SystemZ XCore x86 TMS320C64x M680x EVM MOS65XX WASM BPF RISCV SH TriCore Alpha HPPA LoongArch Xtensa ARC)
# If building for OSX it's best to allow CMake to handle building both architectures
if(APPLE AND NOT CAPSTONE_BUILD_MACOS_THIN)
@@ -226,6 +233,7 @@ set(HEADERS_COMMON
include/capstone/hppa.h
include/capstone/loongarch.h
include/capstone/xtensa.h
include/capstone/arc.h
)
## architecture support
@@ -280,7 +288,6 @@ if(CAPSTONE_AARCH64_SUPPORT)
arch/AArch64/AArch64GenDisassemblerTables.inc
arch/AArch64/AArch64GenInstrInfo.inc
arch/AArch64/AArch64GenRegisterInfo.inc
arch/AArch64/AArch64GenRegisterName.inc
arch/AArch64/AArch64GenSubtargetInfo.inc
arch/AArch64/AArch64GenSystemOperands.inc
arch/AArch64/AArch64GenCSMappingInsn.inc
@@ -405,21 +412,30 @@ if(CAPSTONE_SPARC_SUPPORT)
add_definitions(-DCAPSTONE_HAS_SPARC)
set(SOURCES_SPARC
arch/Sparc/SparcDisassembler.c
arch/Sparc/SparcDisassemblerExtension.c
arch/Sparc/SparcInstPrinter.c
arch/Sparc/SparcMapping.c
arch/Sparc/SparcModule.c
)
set(HEADERS_SPARC
arch/Sparc/Sparc.h
arch/Sparc/SparcDisassembler.h
arch/Sparc/SparcDisassemblerExtension.h
arch/Sparc/SparcInstPrinter.h
arch/Sparc/SparcLinkage.h
arch/Sparc/SparcMCTargetDesc.h
arch/Sparc/SparcMapping.h
arch/Sparc/SparcModule.h
arch/Sparc/SparcGenAsmWriter.inc
arch/Sparc/SparcGenCSAliasMnemMap.inc
arch/Sparc/SparcGenCSFeatureName.inc
arch/Sparc/SparcGenCSMappingInsn.inc
arch/Sparc/SparcGenCSMappingInsnName.inc
arch/Sparc/SparcGenCSMappingInsnOp.inc
arch/Sparc/SparcGenCSOpGroup.inc
arch/Sparc/SparcGenDisassemblerTables.inc
arch/Sparc/SparcGenInstrInfo.inc
arch/Sparc/SparcGenRegisterInfo.inc
arch/Sparc/SparcGenSubtargetInfo.inc
arch/Sparc/SparcInstPrinter.h
arch/Sparc/SparcMapping.h
arch/Sparc/SparcMappingInsn.inc
arch/Sparc/SparcGenSystemOperands.inc
)
endif()
@@ -710,6 +726,22 @@ if(CAPSTONE_XTENSA_SUPPORT)
)
endif()
if (CAPSTONE_ARC_SUPPORT)
add_definitions(-DCAPSTONE_HAS_ARC)
set(SOURCES_ARC
arch/ARC/ARCDisassembler.c
arch/ARC/ARCInstPrinter.c
arch/ARC/ARCMapping.c
arch/ARC/ARCModule.c
)
set(HEADERS_ARC
arch/ARC/ARCInstPrinter.h
arch/ARC/ARCMapping.h
arch/ARC/ARCModule.h
arch/ARC/ARCLinkage.h
)
endif ()
if (CAPSTONE_OSXKERNEL_SUPPORT)
add_definitions(-DCAPSTONE_HAS_OSXKERNEL)
endif()
@@ -738,6 +770,7 @@ set(ALL_SOURCES
${SOURCES_HPPA}
${SOURCES_LOONGARCH}
${SOURCES_XTENSA}
${SOURCES_ARC}
)
set(ALL_HEADERS
@@ -765,6 +798,7 @@ set(ALL_HEADERS
${HEADERS_HPPA}
${HEADERS_LOONGARCH}
${HEADERS_XTENSA}
${HEADERS_ARC}
)
## properties
@@ -800,6 +834,12 @@ if(CAPSTONE_BUILD_SHARED_LIBS)
$<BUILD_INTERFACE:${PROJECT_SOURCE_DIR}/include>
)
target_compile_definitions(capstone PUBLIC CAPSTONE_SHARED)
# Build pdb file for dll on Windows
if(MSVC)
message("Enabling PDB for Windows")
set(CMAKE_CXX_FLAGS_RELEASE "${CMAKE_CXX_FLAGS_RELEASE} /Zi")
set(CMAKE_SHARED_LINKER_FLAGS_RELEASE "${CMAKE_SHARED_LINKER_FLAGS_RELEASE} /DEBUG")
endif()
endif()
# Fuzzer if this is moved to it's own CMakeLists.txt (as it should be)
@@ -833,6 +873,7 @@ source_group("Source\\Alpha" FILES ${SOURCES_ALPHA})
source_group("Source\\HPPA" FILES ${SOURCES_HPPA})
source_group("Source\\LoongArch" FILES ${SOURCES_LOONGARCH})
source_group("Source\\Xtensa" FILES ${SOURCES_XTENSA})
source_group("Source\\ARC" FILES ${SOURCES_ARC})
source_group("Include\\Common" FILES ${HEADERS_COMMON})
source_group("Include\\Engine" FILES ${HEADERS_ENGINE})
@@ -858,6 +899,7 @@ source_group("Include\\Alpha" FILES ${HEADERS_ALPHA})
source_group("Include\\HPPA" FILES ${HEADERS_HPPA})
source_group("Include\\LoongArch" FILES ${HEADERS_LOONGARCH})
source_group("Include\\Xtensa" FILES ${HEADERS_XTENSA})
source_group("Include\\ARC" FILES ${HEADERS_ARC})
## installation
if(CAPSTONE_INSTALL)
@@ -924,6 +966,14 @@ if(CAPSTONE_INSTALL)
DESTINATION ${CAPSTONE_CMAKE_CONFIG_INSTALL_DIR}
)
if (MSVC AND CAPSTONE_BUILD_SHARED_LIBS)
install(FILES
$<TARGET_PDB_FILE:capstone_shared>
DESTINATION ${CMAKE_INSTALL_BINDIR}
OPTIONAL
)
endif()
# uninstall target
if(NOT TARGET UNINSTALL)
configure_file(
@@ -959,3 +1009,9 @@ if(CAPSTONE_BUILD_CSTEST)
set(TESTS_UNIT_DIR ${PROJECT_SOURCE_DIR}/tests/unit)
add_subdirectory(${TESTS_UNIT_DIR})
endif()
# Include CPack
if(PROJECT_IS_TOP_LEVEL)
set(CPACK_PROJECT_CONFIG_FILE "${PROJECT_SOURCE_DIR}/CPackConfig.cmake")
include(CPackConfig.txt)
endif()

1
external/capstone/COMPILE_MAKE.TXT vendored
View File

@@ -94,6 +94,7 @@ Capstone requires no prerequisite packages, so it is easy to compile & install.
/usr/include/capstone/arm.h
/usr/include/capstone/arm64.h
/usr/include/capstone/alpha.h
/usr/include/capstone/arc.h
/usr/include/capstone/bpf.h
/usr/include/capstone/capstone.h
/usr/include/capstone/evm.h

2
external/capstone/CONTRIBUTING.md vendored
View File

@@ -109,6 +109,6 @@ Adding an Architecture
If your architecture is supported in LLVM or one of its forks, you can use `Auto-Sync` to
add the new module.
Checkout [suite/auto-sync/README.md](suite/auto-sync/README.md).
Checkout [suite/auto-sync/RefactorGuide.md](suite/auto-sync/RefactorGuide.md).
Otherwise, you need to implement the disassembler on your own and make it work with the Capstone API.

15
external/capstone/CPackConfig.cmake vendored Normal file
View File

@@ -0,0 +1,15 @@
# Used to dynamically set the package file name based on the generator
foreach(generator ${CPACK_GENERATOR})
if("${generator}" STREQUAL "DEB")
set(CPACK_PACKAGE_FILE_NAME ${CPACK_DEBIAN_PACKAGE_FILE_NAME})
elseif("${generator}" STREQUAL "RPM")
set(CPACK_PACKAGE_FILE_NAME ${CPACK_RPM_PACKAGE_FILE_NAME})
elseif("${generator}" STREQUAL "NSIS")
set(CPACK_PACKAGE_FILE_NAME ${CPACK_NSIS_PACKAGE_FILE_NAME})
elseif("${generator}" STREQUAL "DragNDrop")
set(CPACK_PACKAGE_FILE_NAME ${CPACK_DMG_PACKAGE_FILE_NAME})
else()
set(CPACK_PACKAGE_FILE_NAME "${CPACK_PACKAGE_NAME}-${CPACK_PACKAGE_VERSION}-unknown")
endif()
message(STATUS "Generating package for ${generator} with file name ${CPACK_PACKAGE_FILE_NAME}")
endforeach()

68
external/capstone/CPackConfig.txt vendored Normal file
View File

@@ -0,0 +1,68 @@
# Copyright © 2024 Andrew Quijano <andrewquijano92@gmail.com>
# SPDX-License-Identifier: MIT
# Set general CPack values
set(CPACK_PACKAGE_NAME "capstone")
set(CPACK_PACKAGE_VENDOR "Rot127")
set(CPACK_PACKAGE_CONTACT "Rot127 <unisono@quyllur.org>")
set(CPACK_PACKAGE_DESCRIPTION "Capstone is a lightweight multi-platform, multi-architecture disassembly framework. These are the development headers and libraries.\n Features:\n - Support hardware architectures: AArch64, ARM, Alpha, BPF, EVM, HPPA, LongArch, M680X, M68K, MOS65XX, Mips, PowerPC, RISCV, SH, Sparc, SystemZ, TMS320C64x, TriCore, WASM, x86, XCore, Xtensa.\n - Clean/simple/lightweight/intuitive architecture-neutral API.\n - Provide details on disassembled instructions (called \\\"decomposer\\\" by some others).\n - Provide some semantics of the disassembled instruction, such as list of implicit registers read & written.\n - Thread-safe by design.\n - Special support for embedding into firmware or OS kernel.\n - Distributed under the open source BSD license.")
set(CPACK_PACKAGE_DESCRIPTION_SUMMARY "Lightweight multi-architecture disassembly framework - devel files")
set(CPACK_PACKAGE_HOMEPAGE_URL "https://www.capstone-engine.org/")
set(CPACK_STRIP_FILES false)
set(CPACK_RESOURCE_FILE_LICENSE "${PROJECT_SOURCE_DIR}/LICENSES/LICENSE.TXT")
# Set Debian-specific package variables
set(CPACK_DEBIAN_PACKAGE_NAME "libcapstone-dev")
set(CPACK_DEBIAN_PACKAGE_SOURCE "capstone")
set(CPACK_DEBIAN_PACKAGE_VERSION "${PROJECT_VERSION}")
set(CPACK_DEBIAN_PACKAGE_ORIGINAL_MAINTAINER "Debian Security Tools <team+pkg-security@tracker.debian.org>")
set(CPACK_DEBIAN_PACKAGE_DEPENDS "libc6 (>= 2.2.5)")
set(CPACK_DEBIAN_PACKAGE_SECTION "libdevel")
set(CPACK_DEBIAN_PACKAGE_PRIORITY "optional")
set(CPACK_DEBIAN_PACKAGE_MULTIARCH "same")
# Determine architecture for Debian package
if(${CMAKE_SYSTEM_PROCESSOR} STREQUAL "x86_64")
set(CPACK_DEBIAN_PACKAGE_ARCHITECTURE "amd64")
elseif(${CMAKE_SYSTEM_PROCESSOR} STREQUAL "i386" OR ${CMAKE_SYSTEM_PROCESSOR} STREQUAL "i686")
set(CPACK_DEBIAN_PACKAGE_ARCHITECTURE "i386")
elseif(${CMAKE_SYSTEM_PROCESSOR} STREQUAL "arm")
if(CMAKE_SIZE_OF_VOID_P EQUAL 4)
set(CPACK_DEBIAN_PACKAGE_ARCHITECTURE "armhf")
else()
set(CPACK_DEBIAN_PACKAGE_ARCHITECTURE "arm64")
endif()
else()
set(CPACK_DEBIAN_PACKAGE_ARCHITECTURE ${CMAKE_SYSTEM_PROCESSOR})
endif()
# Include additional file to run 'ldconfig' after install
set(CPACK_DEBIAN_PACKAGE_CONTROL_EXTRA "${PROJECT_SOURCE_DIR}/packages/deb/triggers")
# RPM package settings
set(CPACK_RPM_PACKAGE_NAME "capstone-devel")
set(CPACK_RPM_PACKAGE_VERSION "${PROJECT_VERSION}")
set(CPACK_RPM_PACKAGE_ARCHITECTURE ${CMAKE_SYSTEM_PROCESSOR})
set(CPACK_RPM_PACKAGE_GROUP "Development/Libraries")
set(CPACK_RPM_PACKAGE_REQUIRES "glibc >= 2.2.5")
set(CPACK_RPM_POST_INSTALL_SCRIPT_FILE "${PROJECT_SOURCE_DIR}/packages/rpm/postinstall.sh")
set(CPACK_RPM_POST_UNINSTALL_SCRIPT_FILE "${PROJECT_SOURCE_DIR}/packages/rpm/postinstall.sh")
set(CPACK_RPM_CHANGELOG_FILE "${PROJECT_SOURCE_DIR}/ChangeLog")
set(CPACK_RPM_PACKAGE_LICENSE "BSD3, LLVM")
set(CPACK_RPM_PACKAGE_DESCRIPTION "${CPACK_PACKAGE_DESCRIPTION}")
# Windows package settings
if(WIN32)
set(CPACK_PACKAGE_INSTALL_DIRECTORY "capstone")
set(CPACK_SYSTEM_NAME "Windows-x64")
set(CPACK_NSIS_MODIFY_PATH ON)
set(CPACK_NSIS_PACKAGE_NAME "${CPACK_PACKAGE_NAME} ${CPACK_PACKAGE_VERSION}")
endif()
# Set package file name based on the generator
set(CPACK_DEBIAN_PACKAGE_FILE_NAME "${CPACK_DEBIAN_PACKAGE_NAME}_${CPACK_PACKAGE_VERSION}_${CPACK_DEBIAN_PACKAGE_ARCHITECTURE}")
set(CPACK_RPM_PACKAGE_FILE_NAME "${CPACK_RPM_PACKAGE_NAME}-${CPACK_PACKAGE_VERSION}.${CMAKE_SYSTEM_PROCESSOR}")
set(CPACK_DMG_PACKAGE_FILE_NAME "${CPACK_PACKAGE_NAME}-${CPACK_PACKAGE_VERSION}")
set(CPACK_NSIS_PACKAGE_FILE_NAME "${CPACK_PACKAGE_NAME}-${CPACK_PACKAGE_VERSION}-${CPACK_SYSTEM_NAME}")
include(CPack)

2
external/capstone/CREDITS.TXT vendored
View File

@@ -88,6 +88,6 @@ fanfuqiang & citypw & porto703 : RISCV architecture.
Josh "blacktop" Maine: Arm64 architecture improvements.
Finn Wilkinson: AArch64 update to Armv9.2-a (SME + SVE2 support)
Billow & Sidneyp: TriCore architecture.
Dmitry Sibirtsev: Alpha & HPPA architecture.
Dmitry Sibirtsev: Alpha, HPPA, ARC architecture.
Jiajie Chen & Yanglin Xun: LoongArch architecture.
Billow: Xtensa architecture.

77
external/capstone/ChangeLog vendored
View File

@@ -1,5 +1,82 @@
This file details the changelog of Capstone.
-----------------------------
Version 6.0.0-Alpha4: April 11th, 2025
## What's Changed
* Fix wrong version requirement of tricore instructions by @Changqing-JING in https://github.com/capstone-engine/capstone/pull/2620
* Python bindings: Switch to ubuntu-24.04-arm runner image by @Antelox in https://github.com/capstone-engine/capstone/pull/2625
* Build Tarball before DEB/RPM package. by @Rot127 in https://github.com/capstone-engine/capstone/pull/2627
* Add aliases mapping for MIPS & test for id, alias_id by @wargio in https://github.com/capstone-engine/capstone/pull/2635
* Add checks for MIPS details on cstest_py by @wargio in https://github.com/capstone-engine/capstone/pull/2640
* Give the user some guidance where to add missing enumeration values. by @Rot127 in https://github.com/capstone-engine/capstone/pull/2639
* Python bindings: sdist creation fix + relative test by @Antelox in https://github.com/capstone-engine/capstone/pull/2624
* cmake: Fix building capstone as sub-project by @imphil in https://github.com/capstone-engine/capstone/pull/2629
* Update operand type enums of all arch modules to the one in `capstone.h` by @Rot127 in https://github.com/capstone-engine/capstone/pull/2633
* Enhance shift value and types of shift instructions. by @Rot127 in https://github.com/capstone-engine/capstone/pull/2638
* Fix #2643 by @Rot127 in https://github.com/capstone-engine/capstone/pull/2645
* Tms32c64x Little Endian by @Rot127 in https://github.com/capstone-engine/capstone/pull/2648
* Add call group to svc, smc and hvc. by @Rot127 in https://github.com/capstone-engine/capstone/pull/2651
* Decode BH field in print_insn_detail_ppc by @hainest in https://github.com/capstone-engine/capstone/pull/2662
* Remove undefined constants in riscv_const.py (#2660) by @Asphaltt in https://github.com/capstone-engine/capstone/pull/2661
* Stringify BH fields when printing ppc details by @hainest in https://github.com/capstone-engine/capstone/pull/2663
* MIPS: Fix MIPS16 decoding, wrong flags and ghost registers by @wargio in https://github.com/capstone-engine/capstone/pull/2665
* Add a script to compare the inc file content with the lastest generated ones. by @Rot127 in https://github.com/capstone-engine/capstone/pull/2667
* Mips32r6_64r632 is for both mips32r6 and mips64r6 by @wargio in https://github.com/capstone-engine/capstone/pull/2673
* Fix nanoMIPS decoding of jalrc by @wargio in https://github.com/capstone-engine/capstone/pull/2672
* Revert "Add a script to compare the inc file content with the lastest generated ones." by @Rot127 in https://github.com/capstone-engine/capstone/pull/2678
* Add workflow for building on Windows by @stevenjoezhang in https://github.com/capstone-engine/capstone/pull/2675
* Update read/written registers for x87 comparison instructions by @hainest in https://github.com/capstone-engine/capstone/pull/2680
## New Contributors
* @imphil made their first contribution in https://github.com/capstone-engine/capstone/pull/2629
* @Asphaltt made their first contribution in https://github.com/capstone-engine/capstone/pull/2661
* @stevenjoezhang made their first contribution in https://github.com/capstone-engine/capstone/pull/2675
**Full Changelog**: https://github.com/capstone-engine/capstone/compare/6.0.0-Alpha3...6.0.0-Alpha4
-----------------------------
Version 6.0.0-Alpha3: January 29th, 2025
## What's Changed
* Update Changelog Version to 6.0.0-Alpha2 by @kabeor in https://github.com/capstone-engine/capstone/pull/2553
* PPC LLVM 18 by @Rot127 in https://github.com/capstone-engine/capstone/pull/2540
* Arm regressions by @Rot127 in https://github.com/capstone-engine/capstone/pull/2556
* Python bindings: Enable more archs + bump cibuildwheel action to the v2.22.0 by @Antelox in https://github.com/capstone-engine/capstone/pull/2558
* Add arm64 and sysz compatibility layer to Python bindings by @peace-maker in https://github.com/capstone-engine/capstone/pull/2559
* Make thumb, v8 and m-class positional cstool arguments. by @Rot127 in https://github.com/capstone-engine/capstone/pull/2557
* Small arm64 compat header fixes by @satk0 in https://github.com/capstone-engine/capstone/pull/2563
* PPC regressions by @Rot127 in https://github.com/capstone-engine/capstone/pull/2575
* Fix 2572 by @Rot127 in https://github.com/capstone-engine/capstone/pull/2574
* Clean up the cstest documentation and build instructions. by @Rot127 in https://github.com/capstone-engine/capstone/pull/2580
* Update BPF arch by @Roeegg2 in https://github.com/capstone-engine/capstone/pull/2568
* x86: update read/write registers for transfer instructions by @hainest in https://github.com/capstone-engine/capstone/pull/2578
* cstest: use DOWNLOAD_EXTRACT_TIMESTAMP conditionally by @hainest in https://github.com/capstone-engine/capstone/pull/2581
* Capstone v6 now supports Debian Packaging by @AndrewQuijano in https://github.com/capstone-engine/capstone/pull/2579
* Fix complex atomic instructions handling by @Roeegg2 in https://github.com/capstone-engine/capstone/pull/2584
* Fix linking issue on Windows. by @Rot127 in https://github.com/capstone-engine/capstone/pull/2587
* Clarify between machine used vs. Capstone module affected. by @Rot127 in https://github.com/capstone-engine/capstone/pull/2586
* Fix LoongArch aliases and CS_OPT_SYNTAX_NO_DOLLAR support by @wargio in https://github.com/capstone-engine/capstone/pull/2594
* Update Actions by @AndrewQuijano in https://github.com/capstone-engine/capstone/pull/2593
* Downgrade labeler to v4 again due to failing CI. by @Rot127 in https://github.com/capstone-engine/capstone/pull/2598
* Delete Travis by @AndrewQuijano in https://github.com/capstone-engine/capstone/pull/2600
* Implement CPack for Debian/RPM by @AndrewQuijano in https://github.com/capstone-engine/capstone/pull/2590
* Add tricore tc1.8 instructions by @Changqing-JING in https://github.com/capstone-engine/capstone/pull/2595
* Apply new EVM opcode updates by @andelf in https://github.com/capstone-engine/capstone/pull/2602
* Fix SystemZ macro in Makefile by @Changqing-JING in https://github.com/capstone-engine/capstone/pull/2603
* Rebased #2570 by @Rot127 in https://github.com/capstone-engine/capstone/pull/2614
## New Contributors
* @satk0 made their first contribution in https://github.com/capstone-engine/capstone/pull/2563
* @Roeegg2 made their first contribution in https://github.com/capstone-engine/capstone/pull/2568
* @hainest made their first contribution in https://github.com/capstone-engine/capstone/pull/2578
* @Changqing-JING made their first contribution in https://github.com/capstone-engine/capstone/pull/2595
* @andelf made their first contribution in https://github.com/capstone-engine/capstone/pull/2602
**Full Changelog**: https://github.com/capstone-engine/capstone/compare/6.0.0-Alpha2...6.0.0-RC1
-----------------------------
Version 6.0.0-Alpha2: November 24th, 2024

11
external/capstone/LICENSES/LICENSE_DEB_PACKAGE.txt vendored
View File

@@ -1,11 +0,0 @@
MIT License
The scope of this license is the `packages/deb` directory
Copyright (c) 2024 Andrew Quijano
Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

10
external/capstone/MCInst.c vendored
View File

@@ -319,3 +319,13 @@ void MCInst_updateWithTmpMI(MCInst *MI, MCInst *TmpMI) {
assert(MI->size < MAX_MC_OPS);
memcpy(MI->Operands, TmpMI->Operands, sizeof(MI->Operands[0]) * MI->size);
}
/// @brief Sets the softfail/illegal flag in the cs_insn.
/// Setting it indicates the instruction can be decoded, but is invalid
/// due to not allowed operands or an illegal context.
///
/// @param MI The MCInst holding the cs_insn currently decoded.
void MCInst_setSoftFail(MCInst *MI) {
assert(MI && MI->flat_insn);
MI->flat_insn->illegal = true;
}

2
external/capstone/MCInst.h vendored
View File

@@ -179,4 +179,6 @@ static inline bool MCInst_isAlias(const MCInst *MI) {
void MCInst_updateWithTmpMI(MCInst *MI, MCInst *TmpMI);
void MCInst_setSoftFail(MCInst *MI);
#endif

5
external/capstone/MCInstPrinter.c vendored
View File

@@ -10,6 +10,7 @@ extern bool PPC_getFeatureBits(unsigned int mode, unsigned int feature);
extern bool Mips_getFeatureBits(unsigned int mode, unsigned int feature);
extern bool AArch64_getFeatureBits(unsigned int mode, unsigned int feature);
extern bool TriCore_getFeatureBits(unsigned int mode, unsigned int feature);
extern bool Sparc_getFeatureBits(unsigned int mode, unsigned int feature);
static bool testFeatureBits(const MCInst *MI, uint32_t Value)
{
@@ -37,6 +38,10 @@ static bool testFeatureBits(const MCInst *MI, uint32_t Value)
#ifdef CAPSTONE_HAS_TRICORE
case CS_ARCH_TRICORE:
return TriCore_getFeatureBits(MI->csh->mode, Value);
#endif
#ifdef CAPSTONE_HAS_SPARC
case CS_ARCH_SPARC:
return Sparc_getFeatureBits(MI->csh->mode, Value);
#endif
}
}

15
external/capstone/Makefile vendored
View File

@@ -195,7 +195,7 @@ DEP_SYSZ += $(wildcard arch/SystemZ/SystemZ*.inc)
LIBOBJ_SYSZ =
ifneq (,$(findstring systemz,$(CAPSTONE_ARCHS)))
CFLAGS += -DCAPSTONE_HAS_SYSZ
CFLAGS += -DCAPSTONE_HAS_SYSTEMZ
LIBSRC_SYSZ += $(wildcard arch/SystemZ/SystemZ*.c)
LIBOBJ_SYSZ += $(LIBSRC_SYSZ:%.c=$(OBJDIR)/%.o)
endif
@@ -365,11 +365,21 @@ ifneq (,$(findstring xtensa,$(CAPSTONE_ARCHS)))
LIBOBJ_XTENSA += $(LIBSRC_XTENSA:%.c=$(OBJDIR)/%.o)
endif
DEP_ARC =
DEP_ARC += $(wildcard arch/ARC/ARC*.inc)
LIBOBJ_ARC =
ifneq (,$(findstring arc,$(CAPSTONE_ARCHS)))
CFLAGS += -DCAPSTONE_HAS_ARC
LIBSRC_ARC += $(wildcard arch/ARC/ARC*.c)
LIBOBJ_ARC += $(LIBSRC_ARC:%.c=$(OBJDIR)/%.o)
endif
LIBOBJ =
LIBOBJ += $(OBJDIR)/cs.o $(OBJDIR)/utils.o $(OBJDIR)/SStream.o $(OBJDIR)/MCInstrDesc.o $(OBJDIR)/MCRegisterInfo.o $(OBJDIR)/MCInst.o $(OBJDIR)/MCInstPrinter.o $(OBJDIR)/Mapping.o
LIBOBJ += $(LIBOBJ_ARM) $(LIBOBJ_AARCH64) $(LIBOBJ_M68K) $(LIBOBJ_MIPS) $(LIBOBJ_PPC) $(LIBOBJ_RISCV) $(LIBOBJ_SPARC) $(LIBOBJ_SYSZ) $(LIBOBJ_SH)
LIBOBJ += $(LIBOBJ_X86) $(LIBOBJ_XCORE) $(LIBOBJ_TMS320C64X) $(LIBOBJ_M680X) $(LIBOBJ_EVM) $(LIBOBJ_MOS65XX) $(LIBOBJ_WASM) $(LIBOBJ_BPF)
LIBOBJ += $(LIBOBJ_TRICORE) $(LIBOBJ_ALPHA) $(LIBOBJ_HPPA) $(LIBOBJ_LOONGARCH) $(LIBOBJ_XTENSA)
LIBOBJ += $(LIBOBJ_TRICORE) $(LIBOBJ_ALPHA) $(LIBOBJ_HPPA) $(LIBOBJ_LOONGARCH) $(LIBOBJ_XTENSA) $(LIBOBJ_ARC)
ifeq ($(PKG_EXTRA),)
@@ -503,6 +513,7 @@ $(LIBOBJ_ALPHA): $(DEP_ALPHA)
$(LIBOBJ_HPPA): $(DEP_HPPA)
$(LIBOBJ_LOONGARCH): $(DEP_LOONGARCH)
$(LIBOBJ_XTENSA): $(DEP_XTENSA)
$(LIBOBJ_ARC): $(DEP_ARC)
ifeq ($(CAPSTONE_STATIC),yes)
$(ARCHIVE): $(LIBOBJ)

4
external/capstone/Mapping.c vendored
View File

@@ -354,6 +354,8 @@ DEFINE_get_detail_op(riscv, RISCV);
DEFINE_get_detail_op(systemz, SystemZ);
DEFINE_get_detail_op(xtensa, Xtensa);
DEFINE_get_detail_op(bpf, BPF);
DEFINE_get_detail_op(arc, ARC);
DEFINE_get_detail_op(sparc, Sparc);
/// Returns true if for this architecture the
/// alias operands should be filled.
@@ -390,6 +392,8 @@ static inline bool char_ends_mnem(const char c, cs_arch arch) {
return (!c || c == ' ' || c == '\t' || c == '.');
case CS_ARCH_PPC:
return (!c || c == ' ' || c == '\t');
case CS_ARCH_SPARC:
return (!c || c == ' ' || c == '\t' || c == ',');
}
}

11
external/capstone/Mapping.h vendored
View File

@@ -35,6 +35,7 @@ typedef struct insn_map {
systemz_suppl_info systemz;
arm_suppl_info arm;
xtensa_suppl_info xtensa;
sparc_suppl_info sparc;
} suppl_info; // Supplementary information for each instruction.
#endif
} insn_map;
@@ -146,6 +147,8 @@ DECL_get_detail_op(riscv, RISCV);
DECL_get_detail_op(systemz, SystemZ);
DECL_get_detail_op(xtensa, Xtensa);
DECL_get_detail_op(bpf, BPF);
DECL_get_detail_op(arc, ARC);
DECL_get_detail_op(sparc, Sparc);
/// Increments the detail->arch.op_count by one.
#define DEFINE_inc_detail_op_count(arch, ARCH) \
@@ -185,6 +188,10 @@ DEFINE_inc_detail_op_count(xtensa, Xtensa);
DEFINE_dec_detail_op_count(xtensa, Xtensa);
DEFINE_inc_detail_op_count(bpf, BPF);
DEFINE_dec_detail_op_count(bpf, BPF);
DEFINE_inc_detail_op_count(arc, ARC);
DEFINE_dec_detail_op_count(arc, ARC);
DEFINE_inc_detail_op_count(sparc, Sparc);
DEFINE_dec_detail_op_count(sparc, Sparc);
/// Returns true if a memory operand is currently edited.
static inline bool doing_mem(const MCInst *MI)
@@ -215,9 +222,11 @@ DEFINE_get_arch_detail(hppa, HPPA);
DEFINE_get_arch_detail(loongarch, LoongArch);
DEFINE_get_arch_detail(mips, Mips);
DEFINE_get_arch_detail(riscv, RISCV);
DEFINE_get_arch_detail(arc, ARC);
DEFINE_get_arch_detail(systemz, SystemZ);
DEFINE_get_arch_detail(xtensa, Xtensa);
DEFINE_get_arch_detail(bpf, BPF);
DEFINE_get_arch_detail(sparc, Sparc);
#define DEFINE_check_safe_inc(Arch, ARCH) \
static inline void Arch##_check_safe_inc(const MCInst *MI) { \
@@ -235,6 +244,8 @@ DEFINE_check_safe_inc(RISCV, RISCV);
DEFINE_check_safe_inc(SystemZ, SYSTEMZ);
DEFINE_check_safe_inc(Mips, MIPS);
DEFINE_check_safe_inc(BPF, BPF);
DEFINE_check_safe_inc(ARC, ARC);
DEFINE_check_safe_inc(Sparc, SPARC);
static inline bool detail_is_set(const MCInst *MI)
{

16
external/capstone/MathExtras.h vendored
View File

@@ -482,15 +482,31 @@ static inline unsigned int countLeadingZeros(int x)
}
/// \brief Get specified field from 32-bit instruction. Returns bits from the segment [from, to]
/// The right most bit of insn is bit 31.
static inline uint32_t get_insn_field(uint32_t insn, uint8_t from, uint8_t to)
{
return insn >> (31 - to) & ((1 << (to - from + 1)) - 1);
}
/// \brief Get specified field from 32-bit instruction. Returns bits from the segment [from, to]
/// The right most bit of insn is bit 0.
static inline uint32_t get_insn_field_r(uint32_t insn, uint8_t from, uint8_t to)
{
return insn >> from & ((1 << (to - from + 1)) - 1);
}
/// \brief Get specified bit from 32-bit instruction
static inline uint32_t get_insn_bit(uint32_t insn, uint8_t bit)
{
return get_insn_field(insn, bit, bit);
}
/// \brief Create a bitmask with the N right-most bits set to 1, and all other
/// bits set to 0. Only unsigned types are allowed.
static inline uint32_t maskTrailingOnes32(uint32_t N)
{
const unsigned Bits = CHAR_BIT * sizeof(uint32_t);
return N == 0 ? 0 : (((uint32_t) -1) >> (Bits - N));
}
#endif

2
external/capstone/README.md vendored
View File

@@ -16,7 +16,7 @@ disasm engine for binary analysis and reversing in the security community.
Created by Nguyen Anh Quynh, then developed and maintained by a small community,
Capstone offers some unparalleled features:
- Support multiple hardware architectures: ARM, AArch64, Alpha, BPF, Ethereum VM,
- Support multiple hardware architectures: ARM, AArch64, Alpha, ARC, BPF, Ethereum VM,
LoongArch, HP PA-RISC (HPPA), M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH,
Sparc, SystemZ, TMS320C64X, TriCore, Webassembly, XCore and X86 (16, 32, 64), Xtensa.

57
external/capstone/SStream.c vendored
View File

@@ -26,6 +26,13 @@ void SStream_Init(SStream *ss)
ss->is_closed = false;
ss->markup_stream = false;
ss->prefixed_by_markup = false;
ss->unsigned_num = false;
}
void SStream_opt_unum(SStream *ss, bool print_unsigned_numbers)
{
assert(ss);
ss->unsigned_num = print_unsigned_numbers;
}
/// Returns the a pointer to the internal string buffer of the stream.
@@ -224,6 +231,10 @@ void SStream_concat(SStream *ss, const char *fmt, ...)
void printInt64Bang(SStream *ss, int64_t val)
{
assert(ss);
if (ss->unsigned_num) {
printUInt64Bang(ss, val);
return;
}
SSTREAM_RETURN_IF_CLOSED(ss);
SStream_concat1(ss, '#');
printInt64(ss, val);
@@ -241,6 +252,10 @@ void printUInt64Bang(SStream *ss, uint64_t val)
void printInt64(SStream *ss, int64_t val)
{
assert(ss);
if (ss->unsigned_num) {
printUInt64(ss, val);
return;
}
SSTREAM_RETURN_IF_CLOSED(ss);
if (val >= 0) {
if (val > HEX_THRESHOLD)
@@ -286,14 +301,40 @@ void printInt32BangDec(SStream *ss, int32_t val)
void printInt32Bang(SStream *ss, int32_t val)
{
assert(ss);
if (ss->unsigned_num) {
printUInt32Bang(ss, val);
return;
}
SSTREAM_RETURN_IF_CLOSED(ss);
SStream_concat1(ss, '#');
printInt32(ss, val);
}
void printUInt8(SStream *ss, uint8_t val)
{
assert(ss);
if (val > HEX_THRESHOLD)
SStream_concat(ss, "0x%"PRIx8, val);
else
SStream_concat(ss, "%"PRIu8, val);
}
void printUInt16(SStream *ss, uint16_t val)
{
assert(ss);
if (val > HEX_THRESHOLD)
SStream_concat(ss, "0x%"PRIx16, val);
else
SStream_concat(ss, "%"PRIu16, val);
}
void printInt8(SStream *ss, int8_t val)
{
assert(ss);
if (ss->unsigned_num) {
printUInt8(ss, val);
return;
}
SSTREAM_RETURN_IF_CLOSED(ss);
if (val >= 0) {
if (val > HEX_THRESHOLD)
@@ -314,6 +355,10 @@ void printInt8(SStream *ss, int8_t val)
void printInt16(SStream *ss, int16_t val)
{
assert(ss);
if (ss->unsigned_num) {
printUInt16(ss, val);
return;
}
SSTREAM_RETURN_IF_CLOSED(ss);
if (val >= 0) {
if (val > HEX_THRESHOLD)
@@ -334,6 +379,10 @@ void printInt16(SStream *ss, int16_t val)
void printInt16HexOffset(SStream *ss, int16_t val)
{
assert(ss);
if (ss->unsigned_num) {
printUInt16(ss, val);
return;
}
SSTREAM_RETURN_IF_CLOSED(ss);
if (val >= 0) {
SStream_concat(ss, "+0x%" PRIx16, val);
@@ -350,6 +399,10 @@ void printInt16HexOffset(SStream *ss, int16_t val)
void printInt32(SStream *ss, int32_t val)
{
assert(ss);
if (ss->unsigned_num) {
printUInt32(ss, val);
return;
}
SSTREAM_RETURN_IF_CLOSED(ss);
if (val >= 0) {
if (val > HEX_THRESHOLD)
@@ -371,6 +424,10 @@ void printInt32(SStream *ss, int32_t val)
void printInt32HexOffset(SStream *ss, int32_t val)
{
assert(ss);
if (ss->unsigned_num) {
printUInt32(ss, val);
return;
}
SSTREAM_RETURN_IF_CLOSED(ss);
if (val >= 0) {
SStream_concat(ss, "+0x%" PRIx32, val);

4
external/capstone/SStream.h vendored
View File

@@ -22,6 +22,7 @@ typedef struct SStream {
bool is_closed;
bool markup_stream; ///< If true, markups to the stream are allowed.
bool prefixed_by_markup; ///< Set after the stream wrote a markup for an operand.
bool unsigned_num; ///< Print all numbers as unsigned. Set with CS_OPT_UNSIGNED.
} SStream;
#define SSTREAM_OVERFLOW_CHECK(OS, len) \
@@ -39,6 +40,7 @@ do { \
} while(0)
void SStream_Init(SStream *ss);
void SStream_opt_unum(SStream *ss, bool print_unsigned_numbers);
const char *SStream_replc(const SStream *ss, char elem, char repl);
@@ -81,6 +83,8 @@ void printInt32HexOffset(SStream *ss, int32_t val);
void printUInt32Bang(SStream *O, uint32_t val);
void printUInt8(SStream *ss, uint8_t val);
void printUInt16(SStream *ss, uint16_t val);
void printUInt32(SStream *O, uint32_t val);
// print number in decimal mode

4
external/capstone/arch/AArch64/AArch64DisassemblerExtension.c vendored
View File

@@ -7,6 +7,10 @@
bool AArch64_getFeatureBits(unsigned int mode, unsigned int feature)
{
if (feature == AArch64_FeatureAMX || feature == AArch64_FeatureMUL53 ||
feature == AArch64_FeatureAppleSys) {
return mode & CS_MODE_APPLE_PROPRIETARY;
}
// we support everything
return true;
}

16046
external/capstone/arch/AArch64/AArch64GenAsmWriter.inc vendored
View File

File diff suppressed because it is too large Load Diff

3
external/capstone/arch/AArch64/AArch64GenCSFeatureName.inc vendored
View File

@@ -129,6 +129,9 @@
{ AARCH64_FEATURE_HASGCS, "HasGCS" },
{ AARCH64_FEATURE_HASCPA, "HasCPA" },
{ AARCH64_FEATURE_USENEGATIVEIMMEDIATES, "UseNegativeImmediates" },
{ AARCH64_FEATURE_HASAMX, "HasAMX" },
{ AARCH64_FEATURE_HASMUL53, "HasMUL53" },
{ AARCH64_FEATURE_HASAPPLESYS, "HasAppleSys" },
{ AARCH64_FEATURE_HASCCPP, "HasCCPP" },
{ AARCH64_FEATURE_HASPAN, "HasPAN" },
{ AARCH64_FEATURE_HASPSUAO, "HasPsUAO" },

13426
external/capstone/arch/AArch64/AArch64GenCSMappingInsn.inc vendored
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File diff suppressed because it is too large Load Diff

32
external/capstone/arch/AArch64/AArch64GenCSMappingInsnName.inc vendored
View File

@@ -47,6 +47,7 @@
"asrd", // AARCH64_INS_ASRD
"asrr", // AARCH64_INS_ASRR
"asr", // AARCH64_INS_ASR
"at_as1elx", // AARCH64_INS_AT_AS1ELX
"autda", // AARCH64_INS_AUTDA
"autdb", // AARCH64_INS_AUTDB
"autdza", // AARCH64_INS_AUTDZA
@@ -158,6 +159,7 @@
"cfinv", // AARCH64_INS_CFINV
"clasta", // AARCH64_INS_CLASTA
"clastb", // AARCH64_INS_CLASTB
"clr", // AARCH64_INS_CLR
"clrex", // AARCH64_INS_CLREX
"cls", // AARCH64_INS_CLS
"clz", // AARCH64_INS_CLZ
@@ -329,6 +331,8 @@
"extq", // AARCH64_INS_EXTQ
"mova", // AARCH64_INS_MOVA
"extr", // AARCH64_INS_EXTR
"extrx", // AARCH64_INS_EXTRX
"extry", // AARCH64_INS_EXTRY
"ext", // AARCH64_INS_EXT
"f1cvtl2", // AARCH64_INS_F1CVTL2
"f1cvtlt", // AARCH64_INS_F1CVTLT
@@ -394,6 +398,9 @@
"fexpa", // AARCH64_INS_FEXPA
"fjcvtzs", // AARCH64_INS_FJCVTZS
"flogb", // AARCH64_INS_FLOGB
"fma16", // AARCH64_INS_FMA16
"fma32", // AARCH64_INS_FMA32
"fma64", // AARCH64_INS_FMA64
"fmadd", // AARCH64_INS_FMADD
"fmad", // AARCH64_INS_FMAD
"fmax", // AARCH64_INS_FMAX
@@ -431,6 +438,9 @@
"fmopa", // AARCH64_INS_FMOPA
"fmops", // AARCH64_INS_FMOPS
"fmov", // AARCH64_INS_FMOV
"fms16", // AARCH64_INS_FMS16
"fms32", // AARCH64_INS_FMS32
"fms64", // AARCH64_INS_FMS64
"fmsb", // AARCH64_INS_FMSB
"fmsub", // AARCH64_INS_FMSUB
"fmul", // AARCH64_INS_FMUL
@@ -478,6 +488,9 @@
"gcsss2", // AARCH64_INS_GCSSS2
"gcsstr", // AARCH64_INS_GCSSTR
"gcssttr", // AARCH64_INS_GCSSTTR
"genlut", // AARCH64_INS_GENLUT
"genter", // AARCH64_INS_GENTER
"gexit", // AARCH64_INS_GEXIT
"ld1b", // AARCH64_INS_LD1B
"ld1d", // AARCH64_INS_LD1D
"ld1h", // AARCH64_INS_LD1H
@@ -713,21 +726,28 @@
"ldursb", // AARCH64_INS_LDURSB
"ldursh", // AARCH64_INS_LDURSH
"ldursw", // AARCH64_INS_LDURSW
"ldx", // AARCH64_INS_LDX
"ldxp", // AARCH64_INS_LDXP
"ldxrb", // AARCH64_INS_LDXRB
"ldxrh", // AARCH64_INS_LDXRH
"ldxr", // AARCH64_INS_LDXR
"ldy", // AARCH64_INS_LDY
"ldz", // AARCH64_INS_LDZ
"ldzi", // AARCH64_INS_LDZI
"lslr", // AARCH64_INS_LSLR
"lsl", // AARCH64_INS_LSL
"lsrr", // AARCH64_INS_LSRR
"lsr", // AARCH64_INS_LSR
"luti2", // AARCH64_INS_LUTI2
"luti4", // AARCH64_INS_LUTI4
"mac16", // AARCH64_INS_MAC16
"maddpt", // AARCH64_INS_MADDPT
"madd", // AARCH64_INS_MADD
"madpt", // AARCH64_INS_MADPT
"mad", // AARCH64_INS_MAD
"match", // AARCH64_INS_MATCH
"matfp", // AARCH64_INS_MATFP
"matint", // AARCH64_INS_MATINT
"mlapt", // AARCH64_INS_MLAPT
"mla", // AARCH64_INS_MLA
"mls", // AARCH64_INS_MLS
@@ -749,6 +769,8 @@
"msrr", // AARCH64_INS_MSRR
"msubpt", // AARCH64_INS_MSUBPT
"msub", // AARCH64_INS_MSUB
"mul53hi", // AARCH64_INS_MUL53HI
"mul53lo", // AARCH64_INS_MUL53LO
"mul", // AARCH64_INS_MUL
"mvni", // AARCH64_INS_MVNI
"nands", // AARCH64_INS_NANDS
@@ -934,7 +956,9 @@
"sdivr", // AARCH64_INS_SDIVR
"sdiv", // AARCH64_INS_SDIV
"sdot", // AARCH64_INS_SDOT
"sdsb", // AARCH64_INS_SDSB
"sel", // AARCH64_INS_SEL
"set", // AARCH64_INS_SET
"sete", // AARCH64_INS_SETE
"seten", // AARCH64_INS_SETEN
"setet", // AARCH64_INS_SETET
@@ -1177,13 +1201,17 @@
"sturb", // AARCH64_INS_STURB
"stur", // AARCH64_INS_STUR
"sturh", // AARCH64_INS_STURH
"stx", // AARCH64_INS_STX
"stxp", // AARCH64_INS_STXP
"stxrb", // AARCH64_INS_STXRB
"stxrh", // AARCH64_INS_STXRH
"stxr", // AARCH64_INS_STXR
"sty", // AARCH64_INS_STY
"stz", // AARCH64_INS_STZ
"stz2g", // AARCH64_INS_STZ2G
"stzgm", // AARCH64_INS_STZGM
"stzg", // AARCH64_INS_STZG
"stzi", // AARCH64_INS_STZI
"subg", // AARCH64_INS_SUBG
"subhnb", // AARCH64_INS_SUBHNB
"subhnt", // AARCH64_INS_SUBHNT
@@ -1376,6 +1404,8 @@
"uzpq1", // AARCH64_INS_UZPQ1
"uzpq2", // AARCH64_INS_UZPQ2
"uzp", // AARCH64_INS_UZP
"vecfp", // AARCH64_INS_VECFP
"vecint", // AARCH64_INS_VECINT
"wfet", // AARCH64_INS_WFET
"wfit", // AARCH64_INS_WFIT
"whilege", // AARCH64_INS_WHILEGE
@@ -1388,6 +1418,8 @@
"whilelt", // AARCH64_INS_WHILELT
"whilerw", // AARCH64_INS_WHILERW
"whilewr", // AARCH64_INS_WHILEWR
"wkdmc", // AARCH64_INS_WKDMC
"wkdmd", // AARCH64_INS_WKDMD
"wrffr", // AARCH64_INS_WRFFR
"xaflag", // AARCH64_INS_XAFLAG
"xar", // AARCH64_INS_XAR

13482
external/capstone/arch/AArch64/AArch64GenCSMappingInsnOp.inc vendored
View File

File diff suppressed because it is too large Load Diff

9
external/capstone/arch/AArch64/AArch64GenCSOpGroup.inc vendored
View File

@@ -174,7 +174,8 @@
AArch64_OP_GROUP_RegWithShiftExtend_0_64_w_s = 160,
AArch64_OP_GROUP_PrefetchOp_0 = 161,
AArch64_OP_GROUP_RPRFMOperand = 162,
AArch64_OP_GROUP_GPR64as32 = 163,
AArch64_OP_GROUP_SysCROperand = 164,
AArch64_OP_GROUP_SyspXzrPair = 165,
AArch64_OP_GROUP_MatrixTileList = 166,
AArch64_OP_GROUP_AppleSysBarrierOption = 163,
AArch64_OP_GROUP_GPR64as32 = 164,
AArch64_OP_GROUP_SysCROperand = 165,
AArch64_OP_GROUP_SyspXzrPair = 166,
AArch64_OP_GROUP_MatrixTileList = 167,

62526
external/capstone/arch/AArch64/AArch64GenDisassemblerTables.inc vendored
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File diff suppressed because it is too large Load Diff

26418
external/capstone/arch/AArch64/AArch64GenInstrInfo.inc vendored
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File diff suppressed because it is too large Load Diff

3435
external/capstone/arch/AArch64/AArch64GenRegisterInfo.inc vendored
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File diff suppressed because it is too large Load Diff

714
external/capstone/arch/AArch64/AArch64GenRegisterName.inc vendored
View File

@@ -1,714 +0,0 @@
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
/// getRegisterName - This method is automatically generated by tblgen
/// from the register set description. This returns the assembler name
/// for the specified register.
static const char *getRegisterName(unsigned RegNo, unsigned AltIdx)
{
#ifdef __GNUC__
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Woverlength-strings"
#endif
#ifndef CAPSTONE_DIET
static const char AsmStrsNoRegAltName[] = {
/* 0 */ "D7_D8_D9_D10\0"
/* 13 */ "Q7_Q8_Q9_Q10\0"
/* 26 */ "Z7_Z8_Z9_Z10\0"
/* 39 */ "b10\0"
/* 43 */ "d10\0"
/* 47 */ "h10\0"
/* 51 */ "p10\0"
/* 55 */ "q10\0"
/* 59 */ "s10\0"
/* 63 */ "w10\0"
/* 67 */ "x10\0"
/* 71 */ "z10\0"
/* 75 */ "D17_D18_D19_D20\0"
/* 91 */ "Q17_Q18_Q19_Q20\0"
/* 107 */ "Z17_Z18_Z19_Z20\0"
/* 123 */ "b20\0"
/* 127 */ "d20\0"
/* 131 */ "h20\0"
/* 135 */ "q20\0"
/* 139 */ "s20\0"
/* 143 */ "w20\0"
/* 147 */ "x20\0"
/* 151 */ "z20\0"
/* 155 */ "D27_D28_D29_D30\0"
/* 171 */ "Q27_Q28_Q29_Q30\0"
/* 187 */ "Z27_Z28_Z29_Z30\0"
/* 203 */ "b30\0"
/* 207 */ "d30\0"
/* 211 */ "h30\0"
/* 215 */ "q30\0"
/* 219 */ "s30\0"
/* 223 */ "w30\0"
/* 227 */ "x30\0"
/* 231 */ "z30\0"
/* 235 */ "D29_D30_D31_D0\0"
/* 250 */ "Q29_Q30_Q31_Q0\0"
/* 265 */ "Z29_Z30_Z31_Z0\0"
/* 280 */ "b0\0"
/* 283 */ "d0\0"
/* 286 */ "h0\0"
/* 289 */ "p0\0"
/* 292 */ "q0\0"
/* 295 */ "s0\0"
/* 298 */ "w0\0"
/* 301 */ "x0\0"
/* 304 */ "z0\0"
/* 307 */ "D8_D9_D10_D11\0"
/* 321 */ "Q8_Q9_Q10_Q11\0"
/* 335 */ "W10_W11\0"
/* 343 */ "X4_X5_X6_X7_X8_X9_X10_X11\0"
/* 369 */ "Z8_Z9_Z10_Z11\0"
/* 383 */ "b11\0"
/* 387 */ "d11\0"
/* 391 */ "h11\0"
/* 395 */ "p11\0"
/* 399 */ "q11\0"
/* 403 */ "s11\0"
/* 407 */ "w11\0"
/* 411 */ "x11\0"
/* 415 */ "z11\0"
/* 419 */ "D18_D19_D20_D21\0"
/* 435 */ "Q18_Q19_Q20_Q21\0"
/* 451 */ "W20_W21\0"
/* 459 */ "X14_X15_X16_X17_X18_X19_X20_X21\0"
/* 491 */ "Z18_Z19_Z20_Z21\0"
/* 507 */ "b21\0"
/* 511 */ "d21\0"
/* 515 */ "h21\0"
/* 519 */ "q21\0"
/* 523 */ "s21\0"
/* 527 */ "w21\0"
/* 531 */ "x21\0"
/* 535 */ "z21\0"
/* 539 */ "D28_D29_D30_D31\0"
/* 555 */ "Q28_Q29_Q30_Q31\0"
/* 571 */ "Z28_Z29_Z30_Z31\0"
/* 587 */ "b31\0"
/* 591 */ "d31\0"
/* 595 */ "h31\0"
/* 599 */ "q31\0"
/* 603 */ "s31\0"
/* 607 */ "z31\0"
/* 611 */ "D30_D31_D0_D1\0"
/* 625 */ "Q30_Q31_Q0_Q1\0"
/* 639 */ "W0_W1\0"
/* 645 */ "X0_X1\0"
/* 651 */ "Z30_Z31_Z0_Z1\0"
/* 665 */ "b1\0"
/* 668 */ "d1\0"
/* 671 */ "h1\0"
/* 674 */ "p1\0"
/* 677 */ "q1\0"
/* 680 */ "s1\0"
/* 683 */ "w1\0"
/* 686 */ "x1\0"
/* 689 */ "z1\0"
/* 692 */ "D9_D10_D11_D12\0"
/* 707 */ "Q9_Q10_Q11_Q12\0"
/* 722 */ "Z9_Z10_Z11_Z12\0"
/* 737 */ "b12\0"
/* 741 */ "d12\0"
/* 745 */ "h12\0"
/* 749 */ "p12\0"
/* 753 */ "q12\0"
/* 757 */ "s12\0"
/* 761 */ "w12\0"
/* 765 */ "x12\0"
/* 769 */ "z12\0"
/* 773 */ "D19_D20_D21_D22\0"
/* 789 */ "Q19_Q20_Q21_Q22\0"
/* 805 */ "Z19_Z20_Z21_Z22\0"
/* 821 */ "b22\0"
/* 825 */ "d22\0"
/* 829 */ "h22\0"
/* 833 */ "q22\0"
/* 837 */ "s22\0"
/* 841 */ "w22\0"
/* 845 */ "x22\0"
/* 849 */ "z22\0"
/* 853 */ "D31_D0_D1_D2\0"
/* 866 */ "Q31_Q0_Q1_Q2\0"
/* 879 */ "Z31_Z0_Z1_Z2\0"
/* 892 */ "b2\0"
/* 895 */ "d2\0"
/* 898 */ "h2\0"
/* 901 */ "p2\0"
/* 904 */ "q2\0"
/* 907 */ "s2\0"
/* 910 */ "w2\0"
/* 913 */ "x2\0"
/* 916 */ "z2\0"
/* 919 */ "D10_D11_D12_D13\0"
/* 935 */ "Q10_Q11_Q12_Q13\0"
/* 951 */ "W12_W13\0"
/* 959 */ "X6_X7_X8_X9_X10_X11_X12_X13\0"
/* 987 */ "Z10_Z11_Z12_Z13\0"
/* 1003 */ "b13\0"
/* 1007 */ "d13\0"
/* 1011 */ "h13\0"
/* 1015 */ "p13\0"
/* 1019 */ "q13\0"
/* 1023 */ "s13\0"
/* 1027 */ "w13\0"
/* 1031 */ "x13\0"
/* 1035 */ "z13\0"
/* 1039 */ "D20_D21_D22_D23\0"
/* 1055 */ "Q20_Q21_Q22_Q23\0"
/* 1071 */ "W22_W23\0"
/* 1079 */ "X16_X17_X18_X19_X20_X21_X22_X23\0"
/* 1111 */ "Z20_Z21_Z22_Z23\0"
/* 1127 */ "b23\0"
/* 1131 */ "d23\0"
/* 1135 */ "h23\0"
/* 1139 */ "q23\0"
/* 1143 */ "s23\0"
/* 1147 */ "w23\0"
/* 1151 */ "x23\0"
/* 1155 */ "z23\0"
/* 1159 */ "D0_D1_D2_D3\0"
/* 1171 */ "Q0_Q1_Q2_Q3\0"
/* 1183 */ "W2_W3\0"
/* 1189 */ "X2_X3\0"
/* 1195 */ "Z0_Z1_Z2_Z3\0"
/* 1207 */ "b3\0"
/* 1210 */ "d3\0"
/* 1213 */ "h3\0"
/* 1216 */ "p3\0"
/* 1219 */ "q3\0"
/* 1222 */ "s3\0"
/* 1225 */ "w3\0"
/* 1228 */ "x3\0"
/* 1231 */ "z3\0"
/* 1234 */ "D11_D12_D13_D14\0"
/* 1250 */ "Q11_Q12_Q13_Q14\0"
/* 1266 */ "Z11_Z12_Z13_Z14\0"
/* 1282 */ "b14\0"
/* 1286 */ "d14\0"
/* 1290 */ "h14\0"
/* 1294 */ "p14\0"
/* 1298 */ "q14\0"
/* 1302 */ "s14\0"
/* 1306 */ "w14\0"
/* 1310 */ "x14\0"
/* 1314 */ "z14\0"
/* 1318 */ "D21_D22_D23_D24\0"
/* 1334 */ "Q21_Q22_Q23_Q24\0"
/* 1350 */ "Z21_Z22_Z23_Z24\0"
/* 1366 */ "b24\0"
/* 1370 */ "d24\0"
/* 1374 */ "h24\0"
/* 1378 */ "q24\0"
/* 1382 */ "s24\0"
/* 1386 */ "w24\0"
/* 1390 */ "x24\0"
/* 1394 */ "z24\0"
/* 1398 */ "D1_D2_D3_D4\0"
/* 1410 */ "Q1_Q2_Q3_Q4\0"
/* 1422 */ "Z1_Z2_Z3_Z4\0"
/* 1434 */ "b4\0"
/* 1437 */ "d4\0"
/* 1440 */ "h4\0"
/* 1443 */ "p4\0"
/* 1446 */ "q4\0"
/* 1449 */ "s4\0"
/* 1452 */ "w4\0"
/* 1455 */ "x4\0"
/* 1458 */ "z4\0"
/* 1461 */ "D12_D13_D14_D15\0"
/* 1477 */ "Q12_Q13_Q14_Q15\0"
/* 1493 */ "W14_W15\0"
/* 1501 */ "X8_X9_X10_X11_X12_X13_X14_X15\0"
/* 1531 */ "Z12_Z13_Z14_Z15\0"
/* 1547 */ "b15\0"
/* 1551 */ "d15\0"
/* 1555 */ "h15\0"
/* 1559 */ "p15\0"
/* 1563 */ "q15\0"
/* 1567 */ "s15\0"
/* 1571 */ "w15\0"
/* 1575 */ "x15\0"
/* 1579 */ "z15\0"
/* 1583 */ "D22_D23_D24_D25\0"
/* 1599 */ "Q22_Q23_Q24_Q25\0"
/* 1615 */ "W24_W25\0"
/* 1623 */ "X18_X19_X20_X21_X22_X23_X24_X25\0"
/* 1655 */ "Z22_Z23_Z24_Z25\0"
/* 1671 */ "b25\0"
/* 1675 */ "d25\0"
/* 1679 */ "h25\0"
/* 1683 */ "q25\0"
/* 1687 */ "s25\0"
/* 1691 */ "w25\0"
/* 1695 */ "x25\0"
/* 1699 */ "z25\0"
/* 1703 */ "D2_D3_D4_D5\0"
/* 1715 */ "Q2_Q3_Q4_Q5\0"
/* 1727 */ "W4_W5\0"
/* 1733 */ "X4_X5\0"
/* 1739 */ "Z2_Z3_Z4_Z5\0"
/* 1751 */ "b5\0"
/* 1754 */ "d5\0"
/* 1757 */ "h5\0"
/* 1760 */ "p5\0"
/* 1763 */ "q5\0"
/* 1766 */ "s5\0"
/* 1769 */ "w5\0"
/* 1772 */ "x5\0"
/* 1775 */ "z5\0"
/* 1778 */ "D13_D14_D15_D16\0"
/* 1794 */ "Q13_Q14_Q15_Q16\0"
/* 1810 */ "Z13_Z14_Z15_Z16\0"
/* 1826 */ "b16\0"
/* 1830 */ "d16\0"
/* 1834 */ "h16\0"
/* 1838 */ "q16\0"
/* 1842 */ "s16\0"
/* 1846 */ "w16\0"
/* 1850 */ "x16\0"
/* 1854 */ "z16\0"
/* 1858 */ "D23_D24_D25_D26\0"
/* 1874 */ "Q23_Q24_Q25_Q26\0"
/* 1890 */ "Z23_Z24_Z25_Z26\0"
/* 1906 */ "b26\0"
/* 1910 */ "d26\0"
/* 1914 */ "h26\0"
/* 1918 */ "q26\0"
/* 1922 */ "s26\0"
/* 1926 */ "w26\0"
/* 1930 */ "x26\0"
/* 1934 */ "z26\0"
/* 1938 */ "D3_D4_D5_D6\0"
/* 1950 */ "Q3_Q4_Q5_Q6\0"
/* 1962 */ "Z3_Z4_Z5_Z6\0"
/* 1974 */ "b6\0"
/* 1977 */ "d6\0"
/* 1980 */ "h6\0"
/* 1983 */ "p6\0"
/* 1986 */ "q6\0"
/* 1989 */ "s6\0"
/* 1992 */ "w6\0"
/* 1995 */ "x6\0"
/* 1998 */ "z6\0"
/* 2001 */ "D14_D15_D16_D17\0"
/* 2017 */ "Q14_Q15_Q16_Q17\0"
/* 2033 */ "W16_W17\0"
/* 2041 */ "X10_X11_X12_X13_X14_X15_X16_X17\0"
/* 2073 */ "Z14_Z15_Z16_Z17\0"
/* 2089 */ "b17\0"
/* 2093 */ "d17\0"
/* 2097 */ "h17\0"
/* 2101 */ "q17\0"
/* 2105 */ "s17\0"
/* 2109 */ "w17\0"
/* 2113 */ "x17\0"
/* 2117 */ "z17\0"
/* 2121 */ "D24_D25_D26_D27\0"
/* 2137 */ "Q24_Q25_Q26_Q27\0"
/* 2153 */ "W26_W27\0"
/* 2161 */ "X20_X21_X22_X23_X24_X25_X26_X27\0"
/* 2193 */ "Z24_Z25_Z26_Z27\0"
/* 2209 */ "b27\0"
/* 2213 */ "d27\0"
/* 2217 */ "h27\0"
/* 2221 */ "q27\0"
/* 2225 */ "s27\0"
/* 2229 */ "w27\0"
/* 2233 */ "x27\0"
/* 2237 */ "z27\0"
/* 2241 */ "D4_D5_D6_D7\0"
/* 2253 */ "Q4_Q5_Q6_Q7\0"
/* 2265 */ "W6_W7\0"
/* 2271 */ "X0_X1_X2_X3_X4_X5_X6_X7\0"
/* 2295 */ "Z4_Z5_Z6_Z7\0"
/* 2307 */ "b7\0"
/* 2310 */ "d7\0"
/* 2313 */ "h7\0"
/* 2316 */ "p7\0"
/* 2319 */ "q7\0"
/* 2322 */ "s7\0"
/* 2325 */ "w7\0"
/* 2328 */ "x7\0"
/* 2331 */ "z7\0"
/* 2334 */ "D15_D16_D17_D18\0"
/* 2350 */ "Q15_Q16_Q17_Q18\0"
/* 2366 */ "Z15_Z16_Z17_Z18\0"
/* 2382 */ "b18\0"
/* 2386 */ "d18\0"
/* 2390 */ "h18\0"
/* 2394 */ "q18\0"
/* 2398 */ "s18\0"
/* 2402 */ "w18\0"
/* 2406 */ "x18\0"
/* 2410 */ "z18\0"
/* 2414 */ "D25_D26_D27_D28\0"
/* 2430 */ "Q25_Q26_Q27_Q28\0"
/* 2446 */ "Z25_Z26_Z27_Z28\0"
/* 2462 */ "b28\0"
/* 2466 */ "d28\0"
/* 2470 */ "h28\0"
/* 2474 */ "q28\0"
/* 2478 */ "s28\0"
/* 2482 */ "w28\0"
/* 2486 */ "x28\0"
/* 2490 */ "z28\0"
/* 2494 */ "D5_D6_D7_D8\0"
/* 2506 */ "Q5_Q6_Q7_Q8\0"
/* 2518 */ "Z5_Z6_Z7_Z8\0"
/* 2530 */ "b8\0"
/* 2533 */ "d8\0"
/* 2536 */ "h8\0"
/* 2539 */ "p8\0"
/* 2542 */ "q8\0"
/* 2545 */ "s8\0"
/* 2548 */ "w8\0"
/* 2551 */ "x8\0"
/* 2554 */ "z8\0"
/* 2557 */ "D16_D17_D18_D19\0"
/* 2573 */ "Q16_Q17_Q18_Q19\0"
/* 2589 */ "W18_W19\0"
/* 2597 */ "X12_X13_X14_X15_X16_X17_X18_X19\0"
/* 2629 */ "Z16_Z17_Z18_Z19\0"
/* 2645 */ "b19\0"
/* 2649 */ "d19\0"
/* 2653 */ "h19\0"
/* 2657 */ "q19\0"
/* 2661 */ "s19\0"
/* 2665 */ "w19\0"
/* 2669 */ "x19\0"
/* 2673 */ "z19\0"
/* 2677 */ "D26_D27_D28_D29\0"
/* 2693 */ "Q26_Q27_Q28_Q29\0"
/* 2709 */ "W28_W29\0"
/* 2717 */ "Z26_Z27_Z28_Z29\0"
/* 2733 */ "b29\0"
/* 2737 */ "d29\0"
/* 2741 */ "h29\0"
/* 2745 */ "q29\0"
/* 2749 */ "s29\0"
/* 2753 */ "w29\0"
/* 2757 */ "x29\0"
/* 2761 */ "z29\0"
/* 2765 */ "D6_D7_D8_D9\0"
/* 2777 */ "Q6_Q7_Q8_Q9\0"
/* 2789 */ "W8_W9\0"
/* 2795 */ "X2_X3_X4_X5_X6_X7_X8_X9\0"
/* 2819 */ "Z6_Z7_Z8_Z9\0"
/* 2831 */ "b9\0"
/* 2834 */ "d9\0"
/* 2837 */ "h9\0"
/* 2840 */ "p9\0"
/* 2843 */ "q9\0"
/* 2846 */ "s9\0"
/* 2849 */ "w9\0"
/* 2852 */ "x9\0"
/* 2855 */ "z9\0"
/* 2858 */ "X22_X23_X24_X25_X26_X27_X28_FP\0"
/* 2889 */ "W30_WZR\0"
/* 2897 */ "LR_XZR\0"
/* 2904 */ "za\0"
/* 2907 */ "za0.b\0"
/* 2913 */ "za0.d\0"
/* 2919 */ "za1.d\0"
/* 2925 */ "za2.d\0"
/* 2931 */ "za3.d\0"
/* 2937 */ "za4.d\0"
/* 2943 */ "za5.d\0"
/* 2949 */ "za6.d\0"
/* 2955 */ "za7.d\0"
/* 2961 */ "vg\0"
/* 2964 */ "za0.h\0"
/* 2970 */ "za1.h\0"
/* 2976 */ "z10_hi\0"
/* 2983 */ "z20_hi\0"
/* 2990 */ "z30_hi\0"
/* 2997 */ "z0_hi\0"
/* 3003 */ "z11_hi\0"
/* 3010 */ "z21_hi\0"
/* 3017 */ "z31_hi\0"
/* 3024 */ "z1_hi\0"
/* 3030 */ "z12_hi\0"
/* 3037 */ "z22_hi\0"
/* 3044 */ "z2_hi\0"
/* 3050 */ "z13_hi\0"
/* 3057 */ "z23_hi\0"
/* 3064 */ "z3_hi\0"
/* 3070 */ "z14_hi\0"
/* 3077 */ "z24_hi\0"
/* 3084 */ "z4_hi\0"
/* 3090 */ "z15_hi\0"
/* 3097 */ "z25_hi\0"
/* 3104 */ "z5_hi\0"
/* 3110 */ "z16_hi\0"
/* 3117 */ "z26_hi\0"
/* 3124 */ "z6_hi\0"
/* 3130 */ "z17_hi\0"
/* 3137 */ "z27_hi\0"
/* 3144 */ "z7_hi\0"
/* 3150 */ "z18_hi\0"
/* 3157 */ "z28_hi\0"
/* 3164 */ "z8_hi\0"
/* 3170 */ "z19_hi\0"
/* 3177 */ "z29_hi\0"
/* 3184 */ "z9_hi\0"
/* 3190 */ "wsp\0"
/* 3194 */ "za10.q\0"
/* 3201 */ "za0.q\0"
/* 3207 */ "za11.q\0"
/* 3214 */ "za1.q\0"
/* 3220 */ "za12.q\0"
/* 3227 */ "za2.q\0"
/* 3233 */ "za13.q\0"
/* 3240 */ "za3.q\0"
/* 3246 */ "za14.q\0"
/* 3253 */ "za4.q\0"
/* 3259 */ "za15.q\0"
/* 3266 */ "za5.q\0"
/* 3272 */ "za6.q\0"
/* 3278 */ "za7.q\0"
/* 3284 */ "za8.q\0"
/* 3290 */ "za9.q\0"
/* 3296 */ "ffr\0"
/* 3300 */ "wzr\0"
/* 3304 */ "xzr\0"
/* 3308 */ "za0.s\0"
/* 3314 */ "za1.s\0"
/* 3320 */ "za2.s\0"
/* 3326 */ "za3.s\0"
/* 3332 */ "nzcv\0"
};
#ifdef __GNUC__
#pragma GCC diagnostic pop
#endif
static const uint16_t RegAsmOffsetNoRegAltName[] = {
3296, 2757, 227, 3332, 3191, 2961, 3190, 3300, 3304, 2904, 280, 665, 892, 1207,
1434, 1751, 1974, 2307, 2530, 2831, 39, 383, 737, 1003, 1282, 1547, 1826, 2089,
2382, 2645, 123, 507, 821, 1127, 1366, 1671, 1906, 2209, 2462, 2733, 203, 587,
283, 668, 895, 1210, 1437, 1754, 1977, 2310, 2533, 2834, 43, 387, 741, 1007,
1286, 1551, 1830, 2093, 2386, 2649, 127, 511, 825, 1131, 1370, 1675, 1910, 2213,
2466, 2737, 207, 591, 286, 671, 898, 1213, 1440, 1757, 1980, 2313, 2536, 2837,
47, 391, 745, 1011, 1290, 1555, 1834, 2097, 2390, 2653, 131, 515, 829, 1135,
1374, 1679, 1914, 2217, 2470, 2741, 211, 595, 289, 674, 901, 1216, 1443, 1760,
1983, 2316, 2539, 2840, 51, 395, 749, 1015, 1294, 1559, 292, 677, 904, 1219,
1446, 1763, 1986, 2319, 2542, 2843, 55, 399, 753, 1019, 1298, 1563, 1838, 2101,
2394, 2657, 135, 519, 833, 1139, 1378, 1683, 1918, 2221, 2474, 2745, 215, 599,
295, 680, 907, 1222, 1449, 1766, 1989, 2322, 2545, 2846, 59, 403, 757, 1023,
1302, 1567, 1842, 2105, 2398, 2661, 139, 523, 837, 1143, 1382, 1687, 1922, 2225,
2478, 2749, 219, 603, 298, 683, 910, 1225, 1452, 1769, 1992, 2325, 2548, 2849,
63, 407, 761, 1027, 1306, 1571, 1846, 2109, 2402, 2665, 143, 527, 841, 1147,
1386, 1691, 1926, 2229, 2482, 2753, 223, 301, 686, 913, 1228, 1455, 1772, 1995,
2328, 2551, 2852, 67, 411, 765, 1031, 1310, 1575, 1850, 2113, 2406, 2669, 147,
531, 845, 1151, 1390, 1695, 1930, 2233, 2486, 304, 689, 916, 1231, 1458, 1775,
1998, 2331, 2554, 2855, 71, 415, 769, 1035, 1314, 1579, 1854, 2117, 2410, 2673,
151, 535, 849, 1155, 1394, 1699, 1934, 2237, 2490, 2761, 231, 607, 2907, 2913,
2919, 2925, 2931, 2937, 2943, 2949, 2955, 2964, 2970, 3201, 3214, 3227, 3240, 3253,
3266, 3272, 3278, 3284, 3290, 3194, 3207, 3220, 3233, 3246, 3259, 3308, 3314, 3320,
3326, 2997, 3024, 3044, 3064, 3084, 3104, 3124, 3144, 3164, 3184, 2976, 3003, 3030,
3050, 3070, 3090, 3110, 3130, 3150, 3170, 2983, 3010, 3037, 3057, 3077, 3097, 3117,
3137, 3157, 3177, 2990, 3017, 619, 860, 1165, 1404, 1709, 1944, 2247, 2500, 2771,
6, 313, 699, 927, 1242, 1469, 1786, 2009, 2342, 2565, 83, 427, 781, 1047,
1326, 1591, 1866, 2129, 2422, 2685, 163, 547, 243, 1159, 1398, 1703, 1938, 2241,
2494, 2765, 0, 307, 692, 919, 1234, 1461, 1778, 2001, 2334, 2557, 75, 419,
773, 1039, 1318, 1583, 1858, 2121, 2414, 2677, 155, 539, 235, 611, 853, 857,
1162, 1401, 1706, 1941, 2244, 2497, 2768, 3, 310, 695, 923, 1238, 1465, 1782,
2005, 2338, 2561, 79, 423, 777, 1043, 1322, 1587, 1862, 2125, 2418, 2681, 159,
543, 239, 615, 633, 873, 1177, 1416, 1721, 1956, 2259, 2512, 2783, 19, 327,
714, 943, 1258, 1485, 1802, 2025, 2358, 2581, 99, 443, 797, 1063, 1342, 1607,
1882, 2145, 2438, 2701, 179, 563, 258, 1171, 1410, 1715, 1950, 2253, 2506, 2777,
13, 321, 707, 935, 1250, 1477, 1794, 2017, 2350, 2573, 91, 435, 789, 1055,
1334, 1599, 1874, 2137, 2430, 2693, 171, 555, 250, 625, 866, 870, 1174, 1413,
1718, 1953, 2256, 2509, 2780, 16, 324, 710, 939, 1254, 1481, 1798, 2021, 2354,
2577, 95, 439, 793, 1059, 1338, 1603, 1878, 2141, 2434, 2697, 175, 559, 254,
629, 2858, 2271, 2795, 343, 959, 1501, 2041, 2597, 459, 1079, 1623, 2161, 2889,
639, 1183, 1727, 2265, 2789, 335, 951, 1493, 2033, 2589, 451, 1071, 1615, 2153,
2709, 2897, 2882, 645, 1189, 1733, 2289, 2813, 361, 979, 1523, 2065, 2621, 483,
1103, 1647, 2185, 659, 886, 1201, 1428, 1745, 1968, 2301, 2524, 2825, 32, 375,
729, 995, 1274, 1539, 1818, 2081, 2374, 2637, 115, 499, 813, 1119, 1358, 1663,
1898, 2201, 2454, 2725, 195, 579, 273, 1195, 1422, 1739, 1962, 2295, 2518, 2819,
26, 369, 722, 987, 1266, 1531, 1810, 2073, 2366, 2629, 107, 491, 805, 1111,
1350, 1655, 1890, 2193, 2446, 2717, 187, 571, 265, 651, 879, 883, 1198, 1425,
1742, 1965, 2298, 2521, 2822, 29, 372, 725, 991, 1270, 1535, 1814, 2077, 2370,
2633, 111, 495, 809, 1115, 1354, 1659, 1894, 2197, 2450, 2721, 191, 575, 269,
655,
};
#ifdef __GNUC__
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Woverlength-strings"
#endif
static const char AsmStrsvlist1[] = {
/* 0 */ "\0"
};
#ifdef __GNUC__
#pragma GCC diagnostic pop
#endif
static const uint8_t RegAsmOffsetvlist1[] = {
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0,
};
#ifdef __GNUC__
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Woverlength-strings"
#endif
static const char AsmStrsvreg[] = {
/* 0 */ "v10\0"
/* 4 */ "v20\0"
/* 8 */ "v30\0"
/* 12 */ "v0\0"
/* 15 */ "v11\0"
/* 19 */ "v21\0"
/* 23 */ "v31\0"
/* 27 */ "v1\0"
/* 30 */ "v12\0"
/* 34 */ "v22\0"
/* 38 */ "v2\0"
/* 41 */ "v13\0"
/* 45 */ "v23\0"
/* 49 */ "v3\0"
/* 52 */ "v14\0"
/* 56 */ "v24\0"
/* 60 */ "v4\0"
/* 63 */ "v15\0"
/* 67 */ "v25\0"
/* 71 */ "v5\0"
/* 74 */ "v16\0"
/* 78 */ "v26\0"
/* 82 */ "v6\0"
/* 85 */ "v17\0"
/* 89 */ "v27\0"
/* 93 */ "v7\0"
/* 96 */ "v18\0"
/* 100 */ "v28\0"
/* 104 */ "v8\0"
/* 107 */ "v19\0"
/* 111 */ "v29\0"
/* 115 */ "v9\0"
};
#ifdef __GNUC__
#pragma GCC diagnostic pop
#endif
static const uint8_t RegAsmOffsetvreg[] = {
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
12, 27, 38, 49, 60, 71, 82, 93, 104, 115, 0, 15, 30, 41,
52, 63, 74, 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, 89,
100, 111, 8, 23, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 12, 27, 38, 49,
60, 71, 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, 74, 85,
96, 107, 4, 19, 34, 45, 56, 67, 78, 89, 100, 111, 8, 23,
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
3, 3, 3, 3, 3, 12, 27, 38, 49, 60, 71, 82, 93, 104,
115, 0, 15, 30, 41, 52, 63, 74, 85, 96, 107, 4, 19, 34,
45, 56, 67, 78, 89, 100, 111, 8, 23, 12, 27, 38, 49, 60,
71, 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, 74, 85, 96,
107, 4, 19, 34, 45, 56, 67, 78, 89, 100, 111, 8, 23, 12,
27, 38, 49, 60, 71, 82, 93, 104, 115, 0, 15, 30, 41, 52,
63, 74, 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, 89, 100,
111, 8, 23, 12, 27, 38, 49, 60, 71, 82, 93, 104, 115, 0,
15, 30, 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, 45, 56,
67, 78, 89, 100, 111, 8, 23, 12, 27, 38, 49, 60, 71, 82,
93, 104, 115, 0, 15, 30, 41, 52, 63, 74, 85, 96, 107, 4,
19, 34, 45, 56, 67, 78, 89, 100, 111, 8, 23, 12, 27, 38,
49, 60, 71, 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, 74,
85, 96, 107, 4, 19, 34, 45, 56, 67, 78, 89, 100, 111, 8,
23, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
3,
};
switch(AltIdx) {
default:
return (const char *)(sizeof(RegAsmOffsetvreg)/sizeof(RegAsmOffsetvreg[0]));
case AArch64_NoRegAltName:
return AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1];
case AArch64_vlist1:
return AsmStrsvlist1+RegAsmOffsetvlist1[RegNo-1];
case AArch64_vreg:
return AsmStrsvreg+RegAsmOffsetvreg[RegNo-1];
}
#else
return NULL;
#endif
}

547
external/capstone/arch/AArch64/AArch64GenSubtargetInfo.inc vendored
View File

@@ -19,278 +19,281 @@ enum {
AArch64_FeatureALULSLFast = 1,
AArch64_FeatureAM = 2,
AArch64_FeatureAMVS = 3,
AArch64_FeatureAddrLSLFast = 4,
AArch64_FeatureAggressiveFMA = 5,
AArch64_FeatureAll = 6,
AArch64_FeatureAltFPCmp = 7,
AArch64_FeatureAlternateSExtLoadCVTF32Pattern = 8,
AArch64_FeatureAppleA7SysReg = 9,
AArch64_FeatureArithmeticBccFusion = 10,
AArch64_FeatureArithmeticCbzFusion = 11,
AArch64_FeatureAscendStoreAddress = 12,
AArch64_FeatureB16B16 = 13,
AArch64_FeatureBF16 = 14,
AArch64_FeatureBRBE = 15,
AArch64_FeatureBalanceFPOps = 16,
AArch64_FeatureBranchTargetId = 17,
AArch64_FeatureCCIDX = 18,
AArch64_FeatureCCPP = 19,
AArch64_FeatureCHK = 20,
AArch64_FeatureCLRBHB = 21,
AArch64_FeatureCONTEXTIDREL2 = 22,
AArch64_FeatureCPA = 23,
AArch64_FeatureCRC = 24,
AArch64_FeatureCSSC = 25,
AArch64_FeatureCacheDeepPersist = 26,
AArch64_FeatureCallSavedX8 = 27,
AArch64_FeatureCallSavedX9 = 28,
AArch64_FeatureCallSavedX10 = 29,
AArch64_FeatureCallSavedX11 = 30,
AArch64_FeatureCallSavedX12 = 31,
AArch64_FeatureCallSavedX13 = 32,
AArch64_FeatureCallSavedX14 = 33,
AArch64_FeatureCallSavedX15 = 34,
AArch64_FeatureCallSavedX18 = 35,
AArch64_FeatureCmpBccFusion = 36,
AArch64_FeatureComplxNum = 37,
AArch64_FeatureCrypto = 38,
AArch64_FeatureD128 = 39,
AArch64_FeatureDIT = 40,
AArch64_FeatureDisableLatencySchedHeuristic = 41,
AArch64_FeatureDisableLdp = 42,
AArch64_FeatureDisableStp = 43,
AArch64_FeatureDotProd = 44,
AArch64_FeatureEL2VMSA = 45,
AArch64_FeatureEL3 = 46,
AArch64_FeatureETE = 47,
AArch64_FeatureEnableSelectOptimize = 48,
AArch64_FeatureEnhancedCounterVirtualization = 49,
AArch64_FeatureExperimentalZeroingPseudos = 50,
AArch64_FeatureExynosCheapAsMoveHandling = 51,
AArch64_FeatureFAMINMAX = 52,
AArch64_FeatureFMV = 53,
AArch64_FeatureFP8 = 54,
AArch64_FeatureFP8DOT2 = 55,
AArch64_FeatureFP8DOT4 = 56,
AArch64_FeatureFP8FMA = 57,
AArch64_FeatureFP16FML = 58,
AArch64_FeatureFPARMv8 = 59,
AArch64_FeatureFPMR = 60,
AArch64_FeatureFRInt3264 = 61,
AArch64_FeatureFineGrainedTraps = 62,
AArch64_FeatureFixCortexA53_835769 = 63,
AArch64_FeatureFlagM = 64,
AArch64_FeatureForce32BitJumpTables = 65,
AArch64_FeatureFullFP16 = 66,
AArch64_FeatureFuseAES = 67,
AArch64_FeatureFuseAddSub2RegAndConstOne = 68,
AArch64_FeatureFuseAddress = 69,
AArch64_FeatureFuseAdrpAdd = 70,
AArch64_FeatureFuseArithmeticLogic = 71,
AArch64_FeatureFuseCCSelect = 72,
AArch64_FeatureFuseCryptoEOR = 73,
AArch64_FeatureFuseLiterals = 74,
AArch64_FeatureGCS = 75,
AArch64_FeatureHBC = 76,
AArch64_FeatureHCX = 77,
AArch64_FeatureHardenSlsBlr = 78,
AArch64_FeatureHardenSlsNoComdat = 79,
AArch64_FeatureHardenSlsRetBr = 80,
AArch64_FeatureITE = 81,
AArch64_FeatureJS = 82,
AArch64_FeatureLOR = 83,
AArch64_FeatureLS64 = 84,
AArch64_FeatureLSE = 85,
AArch64_FeatureLSE2 = 86,
AArch64_FeatureLSE128 = 87,
AArch64_FeatureLUT = 88,
AArch64_FeatureLdpAlignedOnly = 89,
AArch64_FeatureMEC = 90,
AArch64_FeatureMOPS = 91,
AArch64_FeatureMPAM = 92,
AArch64_FeatureMTE = 93,
AArch64_FeatureMatMulFP32 = 94,
AArch64_FeatureMatMulFP64 = 95,
AArch64_FeatureMatMulInt8 = 96,
AArch64_FeatureNEON = 97,
AArch64_FeatureNMI = 98,
AArch64_FeatureNV = 99,
AArch64_FeatureNoBTIAtReturnTwice = 100,
AArch64_FeatureNoNegativeImmediates = 101,
AArch64_FeatureNoSVEFPLD1R = 102,
AArch64_FeatureNoZCZeroingFP = 103,
AArch64_FeatureOutlineAtomics = 104,
AArch64_FeaturePAN = 105,
AArch64_FeaturePAN_RWV = 106,
AArch64_FeaturePAuth = 107,
AArch64_FeaturePAuthLR = 108,
AArch64_FeaturePRFM_SLC = 109,
AArch64_FeaturePerfMon = 110,
AArch64_FeaturePostRAScheduler = 111,
AArch64_FeaturePredRes = 112,
AArch64_FeaturePredictableSelectIsExpensive = 113,
AArch64_FeaturePsUAO = 114,
AArch64_FeatureRAS = 115,
AArch64_FeatureRASv2 = 116,
AArch64_FeatureRCPC = 117,
AArch64_FeatureRCPC3 = 118,
AArch64_FeatureRCPC_IMMO = 119,
AArch64_FeatureRDM = 120,
AArch64_FeatureRME = 121,
AArch64_FeatureRandGen = 122,
AArch64_FeatureReserveX1 = 123,
AArch64_FeatureReserveX2 = 124,
AArch64_FeatureReserveX3 = 125,
AArch64_FeatureReserveX4 = 126,
AArch64_FeatureReserveX5 = 127,
AArch64_FeatureReserveX6 = 128,
AArch64_FeatureReserveX7 = 129,
AArch64_FeatureReserveX9 = 130,
AArch64_FeatureReserveX10 = 131,
AArch64_FeatureReserveX11 = 132,
AArch64_FeatureReserveX12 = 133,
AArch64_FeatureReserveX13 = 134,
AArch64_FeatureReserveX14 = 135,
AArch64_FeatureReserveX15 = 136,
AArch64_FeatureReserveX18 = 137,
AArch64_FeatureReserveX20 = 138,
AArch64_FeatureReserveX21 = 139,
AArch64_FeatureReserveX22 = 140,
AArch64_FeatureReserveX23 = 141,
AArch64_FeatureReserveX24 = 142,
AArch64_FeatureReserveX25 = 143,
AArch64_FeatureReserveX26 = 144,
AArch64_FeatureReserveX27 = 145,
AArch64_FeatureReserveX28 = 146,
AArch64_FeatureReserveX30 = 147,
AArch64_FeatureSB = 148,
AArch64_FeatureSEL2 = 149,
AArch64_FeatureSHA2 = 150,
AArch64_FeatureSHA3 = 151,
AArch64_FeatureSM4 = 152,
AArch64_FeatureSME = 153,
AArch64_FeatureSME2 = 154,
AArch64_FeatureSME2p1 = 155,
AArch64_FeatureSMEF8F16 = 156,
AArch64_FeatureSMEF8F32 = 157,
AArch64_FeatureSMEF16F16 = 158,
AArch64_FeatureSMEF64F64 = 159,
AArch64_FeatureSMEFA64 = 160,
AArch64_FeatureSMEI16I64 = 161,
AArch64_FeatureSME_LUTv2 = 162,
AArch64_FeatureSPE = 163,
AArch64_FeatureSPECRES2 = 164,
AArch64_FeatureSPE_EEF = 165,
AArch64_FeatureSSBS = 166,
AArch64_FeatureSSVE_FP8DOT2 = 167,
AArch64_FeatureSSVE_FP8DOT4 = 168,
AArch64_FeatureSSVE_FP8FMA = 169,
AArch64_FeatureSVE = 170,
AArch64_FeatureSVE2 = 171,
AArch64_FeatureSVE2AES = 172,
AArch64_FeatureSVE2BitPerm = 173,
AArch64_FeatureSVE2SHA3 = 174,
AArch64_FeatureSVE2SM4 = 175,
AArch64_FeatureSVE2p1 = 176,
AArch64_FeatureSlowMisaligned128Store = 177,
AArch64_FeatureSlowPaired128 = 178,
AArch64_FeatureSlowSTRQro = 179,
AArch64_FeatureSpecRestrict = 180,
AArch64_FeatureStorePairSuppress = 181,
AArch64_FeatureStpAlignedOnly = 182,
AArch64_FeatureStrictAlign = 183,
AArch64_FeatureTHE = 184,
AArch64_FeatureTLBIW = 185,
AArch64_FeatureTLB_RMI = 186,
AArch64_FeatureTME = 187,
AArch64_FeatureTRACEV8_4 = 188,
AArch64_FeatureTRBE = 189,
AArch64_FeatureTaggedGlobals = 190,
AArch64_FeatureUseEL1ForTP = 191,
AArch64_FeatureUseEL2ForTP = 192,
AArch64_FeatureUseEL3ForTP = 193,
AArch64_FeatureUseROEL0ForTP = 194,
AArch64_FeatureUseRSqrt = 195,
AArch64_FeatureUseScalarIncVL = 196,
AArch64_FeatureVH = 197,
AArch64_FeatureWFxT = 198,
AArch64_FeatureXS = 199,
AArch64_FeatureZCRegMove = 200,
AArch64_FeatureZCZeroing = 201,
AArch64_FeatureZCZeroingFPWorkaround = 202,
AArch64_FeatureZCZeroingGP = 203,
AArch64_HasV8_0aOps = 204,
AArch64_HasV8_0rOps = 205,
AArch64_HasV8_1aOps = 206,
AArch64_HasV8_2aOps = 207,
AArch64_HasV8_3aOps = 208,
AArch64_HasV8_4aOps = 209,
AArch64_HasV8_5aOps = 210,
AArch64_HasV8_6aOps = 211,
AArch64_HasV8_7aOps = 212,
AArch64_HasV8_8aOps = 213,
AArch64_HasV8_9aOps = 214,
AArch64_HasV9_0aOps = 215,
AArch64_HasV9_1aOps = 216,
AArch64_HasV9_2aOps = 217,
AArch64_HasV9_3aOps = 218,
AArch64_HasV9_4aOps = 219,
AArch64_HasV9_5aOps = 220,
AArch64_TuneA35 = 221,
AArch64_TuneA53 = 222,
AArch64_TuneA55 = 223,
AArch64_TuneA57 = 224,
AArch64_TuneA64FX = 225,
AArch64_TuneA65 = 226,
AArch64_TuneA72 = 227,
AArch64_TuneA73 = 228,
AArch64_TuneA75 = 229,
AArch64_TuneA76 = 230,
AArch64_TuneA77 = 231,
AArch64_TuneA78 = 232,
AArch64_TuneA78C = 233,
AArch64_TuneA510 = 234,
AArch64_TuneA520 = 235,
AArch64_TuneA710 = 236,
AArch64_TuneA715 = 237,
AArch64_TuneA720 = 238,
AArch64_TuneAmpere1 = 239,
AArch64_TuneAmpere1A = 240,
AArch64_TuneAmpere1B = 241,
AArch64_TuneAppleA7 = 242,
AArch64_TuneAppleA10 = 243,
AArch64_TuneAppleA11 = 244,
AArch64_TuneAppleA12 = 245,
AArch64_TuneAppleA13 = 246,
AArch64_TuneAppleA14 = 247,
AArch64_TuneAppleA15 = 248,
AArch64_TuneAppleA16 = 249,
AArch64_TuneAppleA17 = 250,
AArch64_TuneCarmel = 251,
AArch64_TuneExynosM3 = 252,
AArch64_TuneExynosM4 = 253,
AArch64_TuneFalkor = 254,
AArch64_TuneKryo = 255,
AArch64_TuneNeoverse512TVB = 256,
AArch64_TuneNeoverseE1 = 257,
AArch64_TuneNeoverseN1 = 258,
AArch64_TuneNeoverseN2 = 259,
AArch64_TuneNeoverseV1 = 260,
AArch64_TuneNeoverseV2 = 261,
AArch64_TuneR82 = 262,
AArch64_TuneSaphira = 263,
AArch64_TuneTSV110 = 264,
AArch64_TuneThunderX = 265,
AArch64_TuneThunderX2T99 = 266,
AArch64_TuneThunderX3T110 = 267,
AArch64_TuneThunderXT81 = 268,
AArch64_TuneThunderXT83 = 269,
AArch64_TuneThunderXT88 = 270,
AArch64_TuneX1 = 271,
AArch64_TuneX2 = 272,
AArch64_TuneX3 = 273,
AArch64_TuneX4 = 274,
AArch64_NumSubtargetFeatures = 275
AArch64_FeatureAMX = 4,
AArch64_FeatureAddrLSLFast = 5,
AArch64_FeatureAggressiveFMA = 6,
AArch64_FeatureAll = 7,
AArch64_FeatureAltFPCmp = 8,
AArch64_FeatureAlternateSExtLoadCVTF32Pattern = 9,
AArch64_FeatureAppleA7SysReg = 10,
AArch64_FeatureAppleSys = 11,
AArch64_FeatureArithmeticBccFusion = 12,
AArch64_FeatureArithmeticCbzFusion = 13,
AArch64_FeatureAscendStoreAddress = 14,
AArch64_FeatureB16B16 = 15,
AArch64_FeatureBF16 = 16,
AArch64_FeatureBRBE = 17,
AArch64_FeatureBalanceFPOps = 18,
AArch64_FeatureBranchTargetId = 19,
AArch64_FeatureCCIDX = 20,
AArch64_FeatureCCPP = 21,
AArch64_FeatureCHK = 22,
AArch64_FeatureCLRBHB = 23,
AArch64_FeatureCONTEXTIDREL2 = 24,
AArch64_FeatureCPA = 25,
AArch64_FeatureCRC = 26,
AArch64_FeatureCSSC = 27,
AArch64_FeatureCacheDeepPersist = 28,
AArch64_FeatureCallSavedX8 = 29,
AArch64_FeatureCallSavedX9 = 30,
AArch64_FeatureCallSavedX10 = 31,
AArch64_FeatureCallSavedX11 = 32,
AArch64_FeatureCallSavedX12 = 33,
AArch64_FeatureCallSavedX13 = 34,
AArch64_FeatureCallSavedX14 = 35,
AArch64_FeatureCallSavedX15 = 36,
AArch64_FeatureCallSavedX18 = 37,
AArch64_FeatureCmpBccFusion = 38,
AArch64_FeatureComplxNum = 39,
AArch64_FeatureCrypto = 40,
AArch64_FeatureD128 = 41,
AArch64_FeatureDIT = 42,
AArch64_FeatureDisableLatencySchedHeuristic = 43,
AArch64_FeatureDisableLdp = 44,
AArch64_FeatureDisableStp = 45,
AArch64_FeatureDotProd = 46,
AArch64_FeatureEL2VMSA = 47,
AArch64_FeatureEL3 = 48,
AArch64_FeatureETE = 49,
AArch64_FeatureEnableSelectOptimize = 50,
AArch64_FeatureEnhancedCounterVirtualization = 51,
AArch64_FeatureExperimentalZeroingPseudos = 52,
AArch64_FeatureExynosCheapAsMoveHandling = 53,
AArch64_FeatureFAMINMAX = 54,
AArch64_FeatureFMV = 55,
AArch64_FeatureFP8 = 56,
AArch64_FeatureFP8DOT2 = 57,
AArch64_FeatureFP8DOT4 = 58,
AArch64_FeatureFP8FMA = 59,
AArch64_FeatureFP16FML = 60,
AArch64_FeatureFPARMv8 = 61,
AArch64_FeatureFPMR = 62,
AArch64_FeatureFRInt3264 = 63,
AArch64_FeatureFineGrainedTraps = 64,
AArch64_FeatureFixCortexA53_835769 = 65,
AArch64_FeatureFlagM = 66,
AArch64_FeatureForce32BitJumpTables = 67,
AArch64_FeatureFullFP16 = 68,
AArch64_FeatureFuseAES = 69,
AArch64_FeatureFuseAddSub2RegAndConstOne = 70,
AArch64_FeatureFuseAddress = 71,
AArch64_FeatureFuseAdrpAdd = 72,
AArch64_FeatureFuseArithmeticLogic = 73,
AArch64_FeatureFuseCCSelect = 74,
AArch64_FeatureFuseCryptoEOR = 75,
AArch64_FeatureFuseLiterals = 76,
AArch64_FeatureGCS = 77,
AArch64_FeatureHBC = 78,
AArch64_FeatureHCX = 79,
AArch64_FeatureHardenSlsBlr = 80,
AArch64_FeatureHardenSlsNoComdat = 81,
AArch64_FeatureHardenSlsRetBr = 82,
AArch64_FeatureITE = 83,
AArch64_FeatureJS = 84,
AArch64_FeatureLOR = 85,
AArch64_FeatureLS64 = 86,
AArch64_FeatureLSE = 87,
AArch64_FeatureLSE2 = 88,
AArch64_FeatureLSE128 = 89,
AArch64_FeatureLUT = 90,
AArch64_FeatureLdpAlignedOnly = 91,
AArch64_FeatureMEC = 92,
AArch64_FeatureMOPS = 93,
AArch64_FeatureMPAM = 94,
AArch64_FeatureMTE = 95,
AArch64_FeatureMUL53 = 96,
AArch64_FeatureMatMulFP32 = 97,
AArch64_FeatureMatMulFP64 = 98,
AArch64_FeatureMatMulInt8 = 99,
AArch64_FeatureNEON = 100,
AArch64_FeatureNMI = 101,
AArch64_FeatureNV = 102,
AArch64_FeatureNoBTIAtReturnTwice = 103,
AArch64_FeatureNoNegativeImmediates = 104,
AArch64_FeatureNoSVEFPLD1R = 105,
AArch64_FeatureNoZCZeroingFP = 106,
AArch64_FeatureOutlineAtomics = 107,
AArch64_FeaturePAN = 108,
AArch64_FeaturePAN_RWV = 109,
AArch64_FeaturePAuth = 110,
AArch64_FeaturePAuthLR = 111,
AArch64_FeaturePRFM_SLC = 112,
AArch64_FeaturePerfMon = 113,
AArch64_FeaturePostRAScheduler = 114,
AArch64_FeaturePredRes = 115,
AArch64_FeaturePredictableSelectIsExpensive = 116,
AArch64_FeaturePsUAO = 117,
AArch64_FeatureRAS = 118,
AArch64_FeatureRASv2 = 119,
AArch64_FeatureRCPC = 120,
AArch64_FeatureRCPC3 = 121,
AArch64_FeatureRCPC_IMMO = 122,
AArch64_FeatureRDM = 123,
AArch64_FeatureRME = 124,
AArch64_FeatureRandGen = 125,
AArch64_FeatureReserveX1 = 126,
AArch64_FeatureReserveX2 = 127,
AArch64_FeatureReserveX3 = 128,
AArch64_FeatureReserveX4 = 129,
AArch64_FeatureReserveX5 = 130,
AArch64_FeatureReserveX6 = 131,
AArch64_FeatureReserveX7 = 132,
AArch64_FeatureReserveX9 = 133,
AArch64_FeatureReserveX10 = 134,
AArch64_FeatureReserveX11 = 135,
AArch64_FeatureReserveX12 = 136,
AArch64_FeatureReserveX13 = 137,
AArch64_FeatureReserveX14 = 138,
AArch64_FeatureReserveX15 = 139,
AArch64_FeatureReserveX18 = 140,
AArch64_FeatureReserveX20 = 141,
AArch64_FeatureReserveX21 = 142,
AArch64_FeatureReserveX22 = 143,
AArch64_FeatureReserveX23 = 144,
AArch64_FeatureReserveX24 = 145,
AArch64_FeatureReserveX25 = 146,
AArch64_FeatureReserveX26 = 147,
AArch64_FeatureReserveX27 = 148,
AArch64_FeatureReserveX28 = 149,
AArch64_FeatureReserveX30 = 150,
AArch64_FeatureSB = 151,
AArch64_FeatureSEL2 = 152,
AArch64_FeatureSHA2 = 153,
AArch64_FeatureSHA3 = 154,
AArch64_FeatureSM4 = 155,
AArch64_FeatureSME = 156,
AArch64_FeatureSME2 = 157,
AArch64_FeatureSME2p1 = 158,
AArch64_FeatureSMEF8F16 = 159,
AArch64_FeatureSMEF8F32 = 160,
AArch64_FeatureSMEF16F16 = 161,
AArch64_FeatureSMEF64F64 = 162,
AArch64_FeatureSMEFA64 = 163,
AArch64_FeatureSMEI16I64 = 164,
AArch64_FeatureSME_LUTv2 = 165,
AArch64_FeatureSPE = 166,
AArch64_FeatureSPECRES2 = 167,
AArch64_FeatureSPE_EEF = 168,
AArch64_FeatureSSBS = 169,
AArch64_FeatureSSVE_FP8DOT2 = 170,
AArch64_FeatureSSVE_FP8DOT4 = 171,
AArch64_FeatureSSVE_FP8FMA = 172,
AArch64_FeatureSVE = 173,
AArch64_FeatureSVE2 = 174,
AArch64_FeatureSVE2AES = 175,
AArch64_FeatureSVE2BitPerm = 176,
AArch64_FeatureSVE2SHA3 = 177,
AArch64_FeatureSVE2SM4 = 178,
AArch64_FeatureSVE2p1 = 179,
AArch64_FeatureSlowMisaligned128Store = 180,
AArch64_FeatureSlowPaired128 = 181,
AArch64_FeatureSlowSTRQro = 182,
AArch64_FeatureSpecRestrict = 183,
AArch64_FeatureStorePairSuppress = 184,
AArch64_FeatureStpAlignedOnly = 185,
AArch64_FeatureStrictAlign = 186,
AArch64_FeatureTHE = 187,
AArch64_FeatureTLBIW = 188,
AArch64_FeatureTLB_RMI = 189,
AArch64_FeatureTME = 190,
AArch64_FeatureTRACEV8_4 = 191,
AArch64_FeatureTRBE = 192,
AArch64_FeatureTaggedGlobals = 193,
AArch64_FeatureUseEL1ForTP = 194,
AArch64_FeatureUseEL2ForTP = 195,
AArch64_FeatureUseEL3ForTP = 196,
AArch64_FeatureUseROEL0ForTP = 197,
AArch64_FeatureUseRSqrt = 198,
AArch64_FeatureUseScalarIncVL = 199,
AArch64_FeatureVH = 200,
AArch64_FeatureWFxT = 201,
AArch64_FeatureXS = 202,
AArch64_FeatureZCRegMove = 203,
AArch64_FeatureZCZeroing = 204,
AArch64_FeatureZCZeroingFPWorkaround = 205,
AArch64_FeatureZCZeroingGP = 206,
AArch64_HasV8_0aOps = 207,
AArch64_HasV8_0rOps = 208,
AArch64_HasV8_1aOps = 209,
AArch64_HasV8_2aOps = 210,
AArch64_HasV8_3aOps = 211,
AArch64_HasV8_4aOps = 212,
AArch64_HasV8_5aOps = 213,
AArch64_HasV8_6aOps = 214,
AArch64_HasV8_7aOps = 215,
AArch64_HasV8_8aOps = 216,
AArch64_HasV8_9aOps = 217,
AArch64_HasV9_0aOps = 218,
AArch64_HasV9_1aOps = 219,
AArch64_HasV9_2aOps = 220,
AArch64_HasV9_3aOps = 221,
AArch64_HasV9_4aOps = 222,
AArch64_HasV9_5aOps = 223,
AArch64_TuneA35 = 224,
AArch64_TuneA53 = 225,
AArch64_TuneA55 = 226,
AArch64_TuneA57 = 227,
AArch64_TuneA64FX = 228,
AArch64_TuneA65 = 229,
AArch64_TuneA72 = 230,
AArch64_TuneA73 = 231,
AArch64_TuneA75 = 232,
AArch64_TuneA76 = 233,
AArch64_TuneA77 = 234,
AArch64_TuneA78 = 235,
AArch64_TuneA78C = 236,
AArch64_TuneA510 = 237,
AArch64_TuneA520 = 238,
AArch64_TuneA710 = 239,
AArch64_TuneA715 = 240,
AArch64_TuneA720 = 241,
AArch64_TuneAmpere1 = 242,
AArch64_TuneAmpere1A = 243,
AArch64_TuneAmpere1B = 244,
AArch64_TuneAppleA7 = 245,
AArch64_TuneAppleA10 = 246,
AArch64_TuneAppleA11 = 247,
AArch64_TuneAppleA12 = 248,
AArch64_TuneAppleA13 = 249,
AArch64_TuneAppleA14 = 250,
AArch64_TuneAppleA15 = 251,
AArch64_TuneAppleA16 = 252,
AArch64_TuneAppleA17 = 253,
AArch64_TuneCarmel = 254,
AArch64_TuneExynosM3 = 255,
AArch64_TuneExynosM4 = 256,
AArch64_TuneFalkor = 257,
AArch64_TuneKryo = 258,
AArch64_TuneNeoverse512TVB = 259,
AArch64_TuneNeoverseE1 = 260,
AArch64_TuneNeoverseN1 = 261,
AArch64_TuneNeoverseN2 = 262,
AArch64_TuneNeoverseV1 = 263,
AArch64_TuneNeoverseV2 = 264,
AArch64_TuneR82 = 265,
AArch64_TuneSaphira = 266,
AArch64_TuneTSV110 = 267,
AArch64_TuneThunderX = 268,
AArch64_TuneThunderX2T99 = 269,
AArch64_TuneThunderX3T110 = 270,
AArch64_TuneThunderXT81 = 271,
AArch64_TuneThunderXT83 = 272,
AArch64_TuneThunderXT88 = 273,
AArch64_TuneX1 = 274,
AArch64_TuneX2 = 275,
AArch64_TuneX3 = 276,
AArch64_TuneX4 = 277,
AArch64_NumSubtargetFeatures = 278
};
#endif // GET_SUBTARGETINFO_ENUM

5379
external/capstone/arch/AArch64/AArch64GenSystemRegister.inc vendored Normal file
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File diff suppressed because it is too large Load Diff

26
external/capstone/arch/AArch64/AArch64InstPrinter.c vendored
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@@ -2110,6 +2110,32 @@ void printAdrAdrpLabel(MCInst *MI, uint64_t Address, unsigned OpNum, SStream *O)
printUInt64Bang(O, MCOperand_getImm(Op));
}
/// Not part of upstream LLVM.
/// Just prints the barrier options as documented in
/// https://github.com/AsahiLinux/docs/blob/main/docs/hw/cpu/apple-instructions.md
void printAppleSysBarrierOption(MCInst *MI, unsigned OpNo, SStream *O)
{
AArch64_add_cs_detail_0(MI, AArch64_OP_GROUP_AppleSysBarrierOption, OpNo);
unsigned Val = MCOperand_getImm(MCInst_getOperand(MI, (OpNo)));
switch (Val) {
default:
SStream_concat0(O, "<undefined>");
break;
case 0:
SStream_concat0(O, "osh");
break;
case 1:
SStream_concat0(O, "nsh");
break;
case 2:
SStream_concat0(O, "ish");
break;
case 3:
SStream_concat0(O, "sy");
break;
}
}
void printBarrierOption(MCInst *MI, unsigned OpNo, SStream *O)
{
AArch64_add_cs_detail_0(MI, AArch64_OP_GROUP_BarrierOption, OpNo);

1
external/capstone/arch/AArch64/AArch64InstPrinter.h vendored
View File

@@ -251,6 +251,7 @@ DECLARE_printVectorIndex(8);
void printAdrAdrpLabel(MCInst *MI, uint64_t Address, unsigned OpNum,
SStream *O);
void printAppleSysBarrierOption(MCInst *MI, unsigned OpNum, SStream *O);
void printBarrierOption(MCInst *MI, unsigned OpNum, SStream *O);
void printBarriernXSOption(MCInst *MI, unsigned OpNum, SStream *O);
void printMSRSystemRegister(MCInst *MI, unsigned OpNum, SStream *O);

94
external/capstone/arch/AArch64/AArch64Mapping.c vendored
View File

@@ -179,6 +179,12 @@ void AArch64_add_vas(MCInst *MI, const SStream *OS)
if (AArch64_get_detail(MI)->op_count == 0) {
return;
}
if (MCInst_getOpcode(MI) == AArch64_MUL53HI || MCInst_getOpcode(MI) == AArch64_MUL53LO) {
// Proprietary Apple instrucions.
AArch64_get_detail(MI)->operands[0].vas = AARCH64LAYOUT_VL_2D;
AArch64_get_detail(MI)->operands[1].vas = AARCH64LAYOUT_VL_2D;
return;
}
// Search for r".[0-9]{1,2}[bhsdq]\W"
// with poor mans regex
@@ -369,12 +375,52 @@ static void AArch64_check_updates_flags(MCInst *MI)
#endif // CAPSTONE_DIET
}
static aarch64_shifter id_to_shifter(unsigned Opcode) {
switch (Opcode) {
default:
return AARCH64_SFT_INVALID;
case AArch64_RORVXr:
case AArch64_RORVWr:
return AARCH64_SFT_ROR_REG;
case AArch64_LSRVXr:
case AArch64_LSRVWr:
return AARCH64_SFT_LSR_REG;
case AArch64_LSLVXr:
case AArch64_LSLVWr:
return AARCH64_SFT_LSL_REG;
case AArch64_ASRVXr:
case AArch64_ASRVWr:
return AARCH64_SFT_ASR_REG;
}
}
static void add_non_alias_details(MCInst *MI)
{
unsigned Opcode = MCInst_getOpcode(MI);
switch (Opcode) {
default:
break;
case AArch64_RORVXr:
case AArch64_RORVWr:
case AArch64_LSRVXr:
case AArch64_LSRVWr:
case AArch64_LSLVXr:
case AArch64_LSLVWr:
case AArch64_ASRVXr:
case AArch64_ASRVWr:
if (AArch64_get_detail(MI)->op_count != 3) {
return;
}
CS_ASSERT_RET(AArch64_get_detail_op(MI, -1)->type == AARCH64_OP_REG);
// The shift by register instructions don't set the shift value properly.
// Correct it here.
uint64_t shift = AArch64_get_detail_op(MI, -1)->reg;
cs_aarch64_op *op1 = AArch64_get_detail_op(MI, -2);
op1->shift.type = id_to_shifter(Opcode);
op1->shift.value = shift;
AArch64_dec_op_count(MI);
break;
case AArch64_FCMPDri:
case AArch64_FCMPEDri:
case AArch64_FCMPEHri:
@@ -573,6 +619,19 @@ static void AArch64_add_not_defined_ops(MCInst *MI, const SStream *OS)
switch (MI->flat_insn->alias_id) {
default:
return;
case AARCH64_INS_ALIAS_ROR:
if (AArch64_get_detail(MI)->op_count != 3) {
return;
}
// The ROR alias doesn't set the shift value properly.
// Correct it here.
bool reg_shift = AArch64_get_detail_op(MI, -1)->type == AARCH64_OP_REG;
uint64_t shift = reg_shift ? AArch64_get_detail_op(MI, -1)->reg : AArch64_get_detail_op(MI, -1)->imm;
cs_aarch64_op *op1 = AArch64_get_detail_op(MI, -2);
op1->shift.type = reg_shift ? AARCH64_SFT_ROR_REG : AARCH64_SFT_ROR;
op1->shift.value = shift;
AArch64_dec_op_count(MI);
break;
case AARCH64_INS_ALIAS_FMOV:
if (AArch64_get_detail_op(MI, -1)->type == AARCH64_OP_FP) {
break;
@@ -611,7 +670,7 @@ static void AArch64_add_not_defined_ops(MCInst *MI, const SStream *OS)
case AARCH64_INS_ALIAS_SMSTART:
case AARCH64_INS_ALIAS_SMSTOP: {
const char *disp_off = NULL;
disp_off = strstr(OS->buffer, " za");
disp_off = strstr(OS->buffer, "smstart\tza");
if (disp_off) {
aarch64_sysop sysop = { 0 };
sysop.alias.svcr = AARCH64_SVCR_SVCRZA;
@@ -620,7 +679,7 @@ static void AArch64_add_not_defined_ops(MCInst *MI, const SStream *OS)
AARCH64_OP_SYSALIAS);
return;
}
disp_off = strstr(OS->buffer, " sm");
disp_off = strstr(OS->buffer, "smstart\tsm");
if (disp_off) {
aarch64_sysop sysop = { 0 };
sysop.alias.svcr = AARCH64_SVCR_SVCRSM;
@@ -762,11 +821,14 @@ bool AArch64_getInstruction(csh handle, const uint8_t *code, size_t code_len,
void *info)
{
AArch64_init_cs_detail(MI);
bool Result = AArch64_LLVM_getInstruction(handle, code, code_len, MI,
DecodeStatus Result = AArch64_LLVM_getInstruction(handle, code, code_len, MI,
size, address,
info) != MCDisassembler_Fail;
info);
AArch64_set_instr_map_data(MI);
return Result;
if (Result == MCDisassembler_SoftFail) {
MCInst_setSoftFail(MI);
}
return Result != MCDisassembler_Fail;
}
/// Patches the register names with Capstone specific alias.
@@ -1042,6 +1104,21 @@ void AArch64_reg_access(const cs_insn *insn, cs_regs regs_read,
default:
break;
}
if (op->shift.type >= AARCH64_SFT_LSL_REG) {
if (!arr_exist(regs_read, read_count, op->shift.value)) {
regs_read[read_count] = (uint16_t)op->shift.value;
read_count++;
}
}
}
switch (insn->alias_id) {
default:
break;
case AARCH64_INS_ALIAS_RET:
regs_read[read_count] = AARCH64_REG_X30;
read_count++;
break;
}
*regs_read_count = read_count;
@@ -1429,6 +1506,13 @@ void AArch64_add_cs_detail_0(MCInst *MI, aarch64_op_group op_group,
AArch64_set_detail_op_sys(MI, OpNum, sysop, AARCH64_OP_SYSIMM);
break;
}
case AArch64_OP_GROUP_AppleSysBarrierOption: {
// Proprietary stuff. We just add the
// immediate here.
unsigned Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
AArch64_set_detail_op_imm(MI, OpNum, AARCH64_OP_IMM, Val);
break;
}
case AArch64_OP_GROUP_BarrierOption: {
unsigned Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
unsigned Opcode = MCInst_getOpcode(MI);

473
external/capstone/arch/ARC/ARCDisassembler.c vendored Normal file
View File

@@ -0,0 +1,473 @@
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2023 */
/* Automatically translated source file from LLVM. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Only small edits allowed. */
/* For multiple similar edits, please create a Patch for the translator. */
/* Capstone's C++ file translator: */
/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
//===- ARCDisassembler.cpp - Disassembler for ARC ---------------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
///
/// \file
/// This file is part of the ARC Disassembler.
///
//===----------------------------------------------------------------------===//
#ifdef CAPSTONE_HAS_ARC
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <capstone/platform.h>
#include "../../MCInst.h"
#include "../../SStream.h"
#include "../../MCDisassembler.h"
#include "../../MCFixedLenDisassembler.h"
#include "../../MathExtras.h"
#include "../../utils.h"
#define CONCAT(a, b) CONCAT_(a, b)
#define CONCAT_(a, b) a##_##b
#define DEBUG_TYPE "arc-disassembler"
/// A disassembler class for ARC.
static DecodeStatus getInstruction(MCInst *Instr, uint64_t *Size, const uint8_t *Bytes,
size_t BytesLen, uint64_t Address,
SStream *CStream);
// end anonymous namespace
static bool readInstruction32(const uint8_t *Bytes, size_t BytesLen,
uint64_t Address, uint64_t *Size, uint32_t *Insn)
{
*Size = 4;
// Read 2 16-bit values, but swap hi/lo parts.
*Insn = (Bytes[0] << 16) | (Bytes[1] << 24) | (Bytes[2] << 0) |
(Bytes[3] << 8);
return true;
}
static bool readInstruction64(const uint8_t *Bytes, size_t BytesLen,
uint64_t Address, uint64_t *Size, uint64_t *Insn)
{
*Size = 8;
*Insn = ((uint64_t)Bytes[0] << 16) | ((uint64_t)Bytes[1] << 24) |
((uint64_t)Bytes[2] << 0) | ((uint64_t)Bytes[3] << 8) |
((uint64_t)Bytes[4] << 48) | ((uint64_t)Bytes[5] << 56) |
((uint64_t)Bytes[6] << 32) | ((uint64_t)Bytes[7] << 40);
return true;
}
static bool readInstruction48(const uint8_t *Bytes, size_t BytesLen,
uint64_t Address, uint64_t *Size, uint64_t *Insn)
{
*Size = 6;
*Insn = ((uint64_t)Bytes[0] << 0) | ((uint64_t)Bytes[1] << 8) |
((uint64_t)Bytes[2] << 32) | ((uint64_t)Bytes[3] << 40) |
((uint64_t)Bytes[4] << 16) | ((uint64_t)Bytes[5] << 24);
return true;
}
static bool readInstruction16(const uint8_t *Bytes, size_t BytesLen,
uint64_t Address, uint64_t *Size, uint32_t *Insn)
{
*Size = 2;
*Insn = (Bytes[0] << 0) | (Bytes[1] << 8);
return true;
}
#define DECLARE_DecodeSignedOperand(B) \
static DecodeStatus CONCAT(DecodeSignedOperand, B)( \
MCInst * Inst, unsigned InsnS, uint64_t Address, \
const void *Decoder);
DECLARE_DecodeSignedOperand(11);
DECLARE_DecodeSignedOperand(9);
DECLARE_DecodeSignedOperand(10);
DECLARE_DecodeSignedOperand(12);
#define DECLARE_DecodeFromCyclicRange(B) \
static DecodeStatus CONCAT(DecodeFromCyclicRange, B)( \
MCInst * Inst, unsigned InsnS, uint64_t Address, \
const void *Decoder);
DECLARE_DecodeFromCyclicRange(3);
#define DECLARE_DecodeBranchTargetS(B) \
static DecodeStatus CONCAT(DecodeBranchTargetS, \
B)(MCInst * Inst, unsigned InsnS, \
uint64_t Address, const void *Decoder);
DECLARE_DecodeBranchTargetS(8);
DECLARE_DecodeBranchTargetS(10);
DECLARE_DecodeBranchTargetS(7);
DECLARE_DecodeBranchTargetS(13);
DECLARE_DecodeBranchTargetS(21);
DECLARE_DecodeBranchTargetS(25);
DECLARE_DecodeBranchTargetS(9);
static DecodeStatus DecodeMEMrs9(MCInst *, unsigned, uint64_t,
const void *);
static DecodeStatus DecodeLdLImmInstruction(MCInst *, uint64_t, uint64_t,
const void *);
static DecodeStatus DecodeStLImmInstruction(MCInst *, uint64_t, uint64_t,
const void *);
static DecodeStatus DecodeLdRLImmInstruction(MCInst *, uint64_t, uint64_t,
const void *);
static DecodeStatus DecodeSOPwithRS12(MCInst *, uint64_t, uint64_t,
const void *);
static DecodeStatus DecodeSOPwithRU6(MCInst *, uint64_t, uint64_t,
const void *);
static DecodeStatus DecodeCCRU6Instruction(MCInst *, uint64_t, uint64_t,
const void *);
static DecodeStatus DecodeMoveHRegInstruction(MCInst *Inst, uint64_t, uint64_t,
const void *);
#define GET_REGINFO_ENUM
#include "ARCGenRegisterInfo.inc"
static const uint16_t GPR32DecoderTable[] = {
ARC_R0, ARC_R1, ARC_R2, ARC_R3, ARC_R4, ARC_R5, ARC_R6,
ARC_R7, ARC_R8, ARC_R9, ARC_R10, ARC_R11, ARC_R12, ARC_R13,
ARC_R14, ARC_R15, ARC_R16, ARC_R17, ARC_R18, ARC_R19, ARC_R20,
ARC_R21, ARC_R22, ARC_R23, ARC_R24, ARC_R25, ARC_GP, ARC_FP,
ARC_SP, ARC_ILINK, ARC_R30, ARC_BLINK
};
static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address,
const void *Decoder)
{
if (RegNo >= 32) {
;
return MCDisassembler_Fail;
}
unsigned Reg = GPR32DecoderTable[RegNo];
MCOperand_CreateReg0(Inst, (Reg));
return MCDisassembler_Success;
}
static DecodeStatus DecodeGBR32ShortRegister(MCInst *Inst, unsigned RegNo,
uint64_t Address,
const void *Decoder)
{
// Enumerates registers from ranges [r0-r3],[r12-r15].
if (RegNo > 3)
RegNo += 8; // 4 for r12, etc...
return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
}
#include "ARCGenDisassemblerTables.inc"
static unsigned decodeCField(unsigned Insn)
{
return fieldFromInstruction_4(Insn, 6, 6);
}
static unsigned decodeBField(unsigned Insn)
{
return (fieldFromInstruction_4(Insn, 12, 3) << 3) |
fieldFromInstruction_4(Insn, 24, 3);
}
static unsigned decodeAField(unsigned Insn)
{
return fieldFromInstruction_4(Insn, 0, 6);
}
static DecodeStatus DecodeMEMrs9(MCInst *Inst, unsigned Insn, uint64_t Address,
const void *Decoder)
{
// We have the 9-bit immediate in the low bits, 6-bit register in high bits.
unsigned S9 = Insn & 0x1ff;
unsigned R = (Insn & (0x7fff & ~0x1ff)) >> 9;
if (DecodeGPR32RegisterClass(Inst, R, Address, Decoder) == MCDisassembler_Fail) {
return MCDisassembler_Fail;
}
MCOperand_CreateImm0(Inst, (SignExtend32((S9), 9)));
return MCDisassembler_Success;
}
static void DecodeSymbolicOperandOff(MCInst *Inst, uint64_t Address,
uint64_t Offset, const void *Decoder)
{
uint64_t NextAddress = Address + Offset;
MCOperand_CreateImm0(Inst, (NextAddress));
}
#define DEFINE_DecodeBranchTargetS(B) \
static DecodeStatus CONCAT(DecodeBranchTargetS, \
B)(MCInst * Inst, unsigned InsnS, \
uint64_t Address, const void *Decoder) \
{ \
CS_ASSERT(B > 0 && "field is empty"); \
DecodeSymbolicOperandOff(Inst, Address, \
SignExtend32((InsnS), B), Decoder); \
return MCDisassembler_Success; \
}
DEFINE_DecodeBranchTargetS(8);
DEFINE_DecodeBranchTargetS(10);
DEFINE_DecodeBranchTargetS(7);
DEFINE_DecodeBranchTargetS(13);
DEFINE_DecodeBranchTargetS(21);
DEFINE_DecodeBranchTargetS(25);
DEFINE_DecodeBranchTargetS(9);
#define DEFINE_DecodeSignedOperand(B) \
static DecodeStatus CONCAT(DecodeSignedOperand, B)( \
MCInst * Inst, unsigned InsnS, uint64_t Address, \
const void * Decoder) \
{ \
CS_ASSERT(B > 0 && "field is empty"); \
MCOperand_CreateImm0( \
Inst, SignExtend32(maskTrailingOnes32(B) & \
InsnS, B) \
); \
return MCDisassembler_Success; \
}
DEFINE_DecodeSignedOperand(11);
DEFINE_DecodeSignedOperand(9);
DEFINE_DecodeSignedOperand(10);
DEFINE_DecodeSignedOperand(12);
#define DEFINE_DecodeFromCyclicRange(B) \
static DecodeStatus CONCAT(DecodeFromCyclicRange, B)( \
MCInst * Inst, unsigned InsnS, uint64_t Address, \
const void * Decoder) \
{ \
CS_ASSERT(B > 0 && "field is empty"); \
const unsigned max = (1u << B) - 1; \
MCOperand_CreateImm0(Inst, (InsnS < max ? (int)(InsnS) : -1)); \
return MCDisassembler_Success; \
}
DEFINE_DecodeFromCyclicRange(3);
static DecodeStatus DecodeStLImmInstruction(MCInst *Inst, uint64_t Insn,
uint64_t Address,
const void *Decoder)
{
unsigned SrcC, DstB, LImm;
DstB = decodeBField(Insn);
if (DstB != 62) {
return MCDisassembler_Fail;
}
SrcC = decodeCField(Insn);
if (DecodeGPR32RegisterClass(Inst, SrcC, Address, Decoder) == MCDisassembler_Fail) {
return MCDisassembler_Fail;
}
LImm = (Insn >> 32);
MCOperand_CreateImm0(Inst, (LImm));
MCOperand_CreateImm0(Inst, (0));
return MCDisassembler_Success;
}
static DecodeStatus DecodeLdLImmInstruction(MCInst *Inst, uint64_t Insn,
uint64_t Address,
const void *Decoder)
{
unsigned DstA, SrcB, LImm;
;
SrcB = decodeBField(Insn);
if (SrcB != 62) {
;
return MCDisassembler_Fail;
}
DstA = decodeAField(Insn);
if (DecodeGPR32RegisterClass(Inst, DstA, Address, Decoder) == MCDisassembler_Fail) {
return MCDisassembler_Fail;
}
LImm = (Insn >> 32);
MCOperand_CreateImm0(Inst, (LImm));
MCOperand_CreateImm0(Inst, (0));
return MCDisassembler_Success;
}
static DecodeStatus DecodeLdRLImmInstruction(MCInst *Inst, uint64_t Insn,
uint64_t Address,
const void *Decoder)
{
unsigned DstA, SrcB;
;
DstA = decodeAField(Insn);
if (DecodeGPR32RegisterClass(Inst, DstA, Address, Decoder) == MCDisassembler_Fail) {
return MCDisassembler_Fail;
}
SrcB = decodeBField(Insn);
if (DecodeGPR32RegisterClass(Inst, SrcB, Address, Decoder) == MCDisassembler_Fail) {
return MCDisassembler_Fail;
}
if (decodeCField(Insn) != 62) {
;
return MCDisassembler_Fail;
}
MCOperand_CreateImm0(Inst, ((uint32_t)(Insn >> 32)));
return MCDisassembler_Success;
}
static DecodeStatus DecodeRegisterOrImm(MCInst *Inst, uint64_t Address,
const void *Decoder, uint64_t RegNum,
uint64_t Value)
{
if (30 == RegNum) {
MCOperand_CreateImm0(Inst, (Value));
return MCDisassembler_Success;
}
return DecodeGPR32RegisterClass(Inst, RegNum, Address, Decoder);
}
static DecodeStatus DecodeMoveHRegInstruction(MCInst *Inst, uint64_t Insn,
uint64_t Address,
const void *Decoder)
{
;
uint64_t H = fieldFromInstruction_8(Insn, 5, 3) |
(fieldFromInstruction_8(Insn, 0, 2) << 3);
uint64_t G = fieldFromInstruction_8(Insn, 8, 3) |
(fieldFromInstruction_8(Insn, 3, 2) << 3);
if (MCDisassembler_Success != DecodeRegisterOrImm(Inst, Address,
Decoder, G, 0))
return MCDisassembler_Fail;
return DecodeRegisterOrImm(Inst, Address, Decoder, H, Insn >> 16u);
}
static DecodeStatus DecodeCCRU6Instruction(MCInst *Inst, uint64_t Insn,
uint64_t Address,
const void *Decoder)
{
unsigned DstB;
;
DstB = decodeBField(Insn);
if (DecodeGPR32RegisterClass(Inst, DstB, Address, Decoder) == MCDisassembler_Fail) {
return MCDisassembler_Fail;
}
uint64_t U6Field = fieldFromInstruction_8(Insn, 6, 6);
MCOperand_CreateImm0(Inst, (U6Field));
uint64_t CCField = fieldFromInstruction_8(Insn, 0, 4);
MCOperand_CreateImm0(Inst, (CCField));
return MCDisassembler_Success;
}
static DecodeStatus DecodeSOPwithRU6(MCInst *Inst, uint64_t Insn,
uint64_t Address, const void *Decoder)
{
unsigned DstB = decodeBField(Insn);
if (DecodeGPR32RegisterClass(Inst, DstB, Address, Decoder) == MCDisassembler_Fail) {
return MCDisassembler_Fail;
}
uint64_t U6 = fieldFromInstruction_8(Insn, 6, 6);
MCOperand_CreateImm0(Inst, (U6));
return MCDisassembler_Success;
}
static DecodeStatus DecodeSOPwithRS12(MCInst *Inst, uint64_t Insn,
uint64_t Address, const void *Decoder)
{
unsigned DstB = decodeBField(Insn);
if (DecodeGPR32RegisterClass(Inst, DstB, Address, Decoder) == MCDisassembler_Fail) {
return MCDisassembler_Fail;
}
uint64_t Lower = fieldFromInstruction_8(Insn, 6, 6);
uint64_t Upper = fieldFromInstruction_8(Insn, 0, 5);
uint64_t Sign = fieldFromInstruction_8(Insn, 5, 1) ? -1 : 1;
uint64_t Result = Sign * ((Upper << 6) + Lower);
MCOperand_CreateImm0(Inst, (Result));
return MCDisassembler_Success;
}
static DecodeStatus getInstruction(MCInst *Instr, uint64_t *Size, const uint8_t *Bytes,
size_t BytesLen, uint64_t Address, SStream *cStream)
{
DecodeStatus Result;
if (BytesLen < 2) {
*Size = 0;
return MCDisassembler_Fail;
}
uint8_t DecodeByte = (Bytes[1] & 0xF7) >> 3;
// 0x00 -> 0x07 are 32-bit instructions.
// 0x08 -> 0x1F are 16-bit instructions.
if (DecodeByte < 0x08) {
// 32-bit instruction.
if (BytesLen < 4) {
// Did we decode garbage?
*Size = 0;
return MCDisassembler_Fail;
}
if (BytesLen >= 8) {
// Attempt to decode 64-bit instruction.
uint64_t Insn64;
if (!readInstruction64(Bytes, BytesLen, Address, Size, &Insn64))
return MCDisassembler_Fail;
Result = decodeInstruction_8(DecoderTable64, Instr,
Insn64, Address, NULL);
if (MCDisassembler_Success == Result) {
;
return Result;
};
}
uint32_t Insn32;
if (!readInstruction32(Bytes, BytesLen, Address, Size, &Insn32)) {
return MCDisassembler_Fail;
}
// Calling the auto-generated decoder function.
return decodeInstruction_4(DecoderTable32, Instr, Insn32,
Address, NULL);
} else {
if (BytesLen >= 6) {
// Attempt to treat as instr. with limm data.
uint64_t Insn48;
if (!readInstruction48(Bytes, BytesLen, Address, Size, &Insn48))
return MCDisassembler_Fail;
Result = decodeInstruction_8(DecoderTable48, Instr,
Insn48, Address, NULL);
if (MCDisassembler_Success == Result) {
;
return Result;
};
}
uint32_t Insn16;
if (!readInstruction16(Bytes, BytesLen, Address, Size, &Insn16))
return MCDisassembler_Fail;
// Calling the auto-generated decoder function.
return decodeInstruction_2(DecoderTable16, Instr, Insn16,
Address, NULL);
}
}
DecodeStatus ARC_LLVM_getInstruction(MCInst *MI, uint64_t *Size,
const uint8_t *Bytes,
size_t BytesLen, uint64_t Address,
SStream *CS)
{
return getInstruction(MI, Size, Bytes, BytesLen, Address, CS);
}
#endif

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external/capstone/arch/ARC/ARCGenAsmWriter.inc vendored Normal file
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external/capstone/arch/ARC/ARCGenCSInsnEnum.inc vendored Normal file
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/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
ARC_INS_INVALID,
ARC_INS_h,
ARC_INS_PBR,
ARC_INS_ERROR_FLS,
ARC_INS_ERROR_FFS,
ARC_INS_PLDFI,
ARC_INS_STB_FAR,
ARC_INS_STH_FAR,
ARC_INS_ST_FAR,
ARC_INS_ADC,
ARC_INS_ADC_F,
ARC_INS_ADD_S,
ARC_INS_ADD,
ARC_INS_ADD_F,
ARC_INS_AND,
ARC_INS_AND_F,
ARC_INS_ASL_S,
ARC_INS_ASL,
ARC_INS_ASL_F,
ARC_INS_ASR_S,
ARC_INS_ASR,
ARC_INS_ASR_F,
ARC_INS_BCLR_S,
ARC_INS_BEQ_S,
ARC_INS_BGE_S,
ARC_INS_BGT_S,
ARC_INS_BHI_S,
ARC_INS_BHS_S,
ARC_INS_BL,
ARC_INS_BLE_S,
ARC_INS_BLO_S,
ARC_INS_BLS_S,
ARC_INS_BLT_S,
ARC_INS_BL_S,
ARC_INS_BMSK_S,
ARC_INS_BNE_S,
ARC_INS_B,
ARC_INS_BREQ_S,
ARC_INS_BRNE_S,
ARC_INS_BR,
ARC_INS_BSET_S,
ARC_INS_BTST_S,
ARC_INS_B_S,
ARC_INS_CMP_S,
ARC_INS_CMP,
ARC_INS_LD_S,
ARC_INS_MOV_S,
ARC_INS_EI_S,
ARC_INS_ENTER_S,
ARC_INS_FFS_F,
ARC_INS_FFS,
ARC_INS_FLS_F,
ARC_INS_FLS,
ARC_INS_ABS_S,
ARC_INS_ADD1_S,
ARC_INS_ADD2_S,
ARC_INS_ADD3_S,
ARC_INS_AND_S,
ARC_INS_BIC_S,
ARC_INS_BRK_S,
ARC_INS_EXTB_S,
ARC_INS_EXTH_S,
ARC_INS_JEQ_S,
ARC_INS_JL_S,
ARC_INS_JL_S_D,
ARC_INS_JNE_S,
ARC_INS_J_S,
ARC_INS_J_S_D,
ARC_INS_LSR_S,
ARC_INS_MPYUW_S,
ARC_INS_MPYW_S,
ARC_INS_MPY_S,
ARC_INS_NEG_S,
ARC_INS_NOP_S,
ARC_INS_NOT_S,
ARC_INS_OR_S,
ARC_INS_SEXB_S,
ARC_INS_SEXH_S,
ARC_INS_SUB_S,
ARC_INS_SUB_S_NE,
ARC_INS_SWI_S,
ARC_INS_TRAP_S,
ARC_INS_TST_S,
ARC_INS_UNIMP_S,
ARC_INS_XOR_S,
ARC_INS_LDB_S,
ARC_INS_LDH_S,
ARC_INS_J,
ARC_INS_JL,
ARC_INS_JLI_S,
ARC_INS_LDB_AB,
ARC_INS_LDB_AW,
ARC_INS_LDB_DI_AB,
ARC_INS_LDB_DI_AW,
ARC_INS_LDB_DI,
ARC_INS_LDB_X_AB,
ARC_INS_LDB_X_AW,
ARC_INS_LDB_X_DI_AB,
ARC_INS_LDB_X_DI_AW,
ARC_INS_LDB_X_DI,
ARC_INS_LDB_X,
ARC_INS_LDB,
ARC_INS_LDH_AB,
ARC_INS_LDH_AW,
ARC_INS_LDH_DI_AB,
ARC_INS_LDH_DI_AW,
ARC_INS_LDH_DI,
ARC_INS_LDH_S_X,
ARC_INS_LDH_X_AB,
ARC_INS_LDH_X_AW,
ARC_INS_LDH_X_DI_AB,
ARC_INS_LDH_X_DI_AW,
ARC_INS_LDH_X_DI,
ARC_INS_LDH_X,
ARC_INS_LDH,
ARC_INS_LDI_S,
ARC_INS_LD_AB,
ARC_INS_LD_AW,
ARC_INS_LD_DI_AB,
ARC_INS_LD_DI_AW,
ARC_INS_LD_DI,
ARC_INS_LD_S_AS,
ARC_INS_LD,
ARC_INS_LEAVE_S,
ARC_INS_LR,
ARC_INS_LSR,
ARC_INS_LSR_F,
ARC_INS_MAX,
ARC_INS_MAX_F,
ARC_INS_MIN,
ARC_INS_MIN_F,
ARC_INS_MOV_S_NE,
ARC_INS_MOV,
ARC_INS_MOV_F,
ARC_INS_MPYMU,
ARC_INS_MPYMU_F,
ARC_INS_MPYM,
ARC_INS_MPYM_F,
ARC_INS_MPY,
ARC_INS_MPY_F,
ARC_INS_NORMH_F,
ARC_INS_NORMH,
ARC_INS_NORM_F,
ARC_INS_NORM,
ARC_INS_OR,
ARC_INS_OR_F,
ARC_INS_POP_S,
ARC_INS_PUSH_S,
ARC_INS_ROR,
ARC_INS_ROR_F,
ARC_INS_RSUB,
ARC_INS_RSUB_F,
ARC_INS_SBC,
ARC_INS_SBC_F,
ARC_INS_SETEQ,
ARC_INS_SETEQ_F,
ARC_INS_SEXB_F,
ARC_INS_SEXB,
ARC_INS_SEXH_F,
ARC_INS_SEXH,
ARC_INS_STB_S,
ARC_INS_ST_S,
ARC_INS_STB_AB,
ARC_INS_STB_AW,
ARC_INS_STB_DI_AB,
ARC_INS_STB_DI_AW,
ARC_INS_STB_DI,
ARC_INS_STB,
ARC_INS_STH_AB,
ARC_INS_STH_AW,
ARC_INS_STH_DI_AB,
ARC_INS_STH_DI_AW,
ARC_INS_STH_DI,
ARC_INS_STH_S,
ARC_INS_STH,
ARC_INS_ST_AB,
ARC_INS_ST_AW,
ARC_INS_ST_DI_AB,
ARC_INS_ST_DI_AW,
ARC_INS_ST_DI,
ARC_INS_ST,
ARC_INS_SUB1,
ARC_INS_SUB1_F,
ARC_INS_SUB2,
ARC_INS_SUB2_F,
ARC_INS_SUB3,
ARC_INS_SUB3_F,
ARC_INS_SUB,
ARC_INS_SUB_F,
ARC_INS_XOR,
ARC_INS_XOR_F,

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external/capstone/arch/ARC/ARCGenCSMappingInsn.inc vendored Normal file
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204
external/capstone/arch/ARC/ARCGenCSMappingInsnName.inc vendored Normal file
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/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
"invalid", // ARC_INS_INVALID
"h", // ARC_INS_h
"pbr", // ARC_INS_PBR
"error_fls", // ARC_INS_ERROR_FLS
"error_ffs", // ARC_INS_ERROR_FFS
"pldfi", // ARC_INS_PLDFI
"STB_FAR", // ARC_INS_STB_FAR
"STH_FAR", // ARC_INS_STH_FAR
"ST_FAR", // ARC_INS_ST_FAR
"adc", // ARC_INS_ADC
"adc_f", // ARC_INS_ADC_F
"add_s", // ARC_INS_ADD_S
"add", // ARC_INS_ADD
"add_f", // ARC_INS_ADD_F
"and", // ARC_INS_AND
"and_f", // ARC_INS_AND_F
"asl_s", // ARC_INS_ASL_S
"asl", // ARC_INS_ASL
"asl_f", // ARC_INS_ASL_F
"asr_s", // ARC_INS_ASR_S
"asr", // ARC_INS_ASR
"asr_f", // ARC_INS_ASR_F
"bclr_s", // ARC_INS_BCLR_S
"beq_s", // ARC_INS_BEQ_S
"bge_s", // ARC_INS_BGE_S
"bgt_s", // ARC_INS_BGT_S
"bhi_s", // ARC_INS_BHI_S
"bhs_s", // ARC_INS_BHS_S
"bl", // ARC_INS_BL
"ble_s", // ARC_INS_BLE_S
"blo_s", // ARC_INS_BLO_S
"bls_s", // ARC_INS_BLS_S
"blt_s", // ARC_INS_BLT_S
"bl_s", // ARC_INS_BL_S
"bmsk_s", // ARC_INS_BMSK_S
"bne_s", // ARC_INS_BNE_S
"b", // ARC_INS_B
"breq_s", // ARC_INS_BREQ_S
"brne_s", // ARC_INS_BRNE_S
"br", // ARC_INS_BR
"bset_s", // ARC_INS_BSET_S
"btst_s", // ARC_INS_BTST_S
"b_s", // ARC_INS_B_S
"cmp_s", // ARC_INS_CMP_S
"cmp", // ARC_INS_CMP
"ld_s", // ARC_INS_LD_S
"mov_s", // ARC_INS_MOV_S
"ei_s", // ARC_INS_EI_S
"enter_s", // ARC_INS_ENTER_S
"ffs_f", // ARC_INS_FFS_F
"ffs", // ARC_INS_FFS
"fls_f", // ARC_INS_FLS_F
"fls", // ARC_INS_FLS
"abs_s", // ARC_INS_ABS_S
"add1_s", // ARC_INS_ADD1_S
"add2_s", // ARC_INS_ADD2_S
"add3_s", // ARC_INS_ADD3_S
"and_s", // ARC_INS_AND_S
"bic_s", // ARC_INS_BIC_S
"brk_s", // ARC_INS_BRK_S
"extb_s", // ARC_INS_EXTB_S
"exth_s", // ARC_INS_EXTH_S
"jeq_s", // ARC_INS_JEQ_S
"jl_s", // ARC_INS_JL_S
"jl_s_d", // ARC_INS_JL_S_D
"jne_s", // ARC_INS_JNE_S
"j_s", // ARC_INS_J_S
"j_s_d", // ARC_INS_J_S_D
"lsr_s", // ARC_INS_LSR_S
"mpyuw_s", // ARC_INS_MPYUW_S
"mpyw_s", // ARC_INS_MPYW_S
"mpy_s", // ARC_INS_MPY_S
"neg_s", // ARC_INS_NEG_S
"nop_s", // ARC_INS_NOP_S
"not_s", // ARC_INS_NOT_S
"or_s", // ARC_INS_OR_S
"sexb_s", // ARC_INS_SEXB_S
"sexh_s", // ARC_INS_SEXH_S
"sub_s", // ARC_INS_SUB_S
"sub_s_ne", // ARC_INS_SUB_S_NE
"swi_s", // ARC_INS_SWI_S
"trap_s", // ARC_INS_TRAP_S
"tst_s", // ARC_INS_TST_S
"unimp_s", // ARC_INS_UNIMP_S
"xor_s", // ARC_INS_XOR_S
"ldb_s", // ARC_INS_LDB_S
"ldh_s", // ARC_INS_LDH_S
"j", // ARC_INS_J
"jl", // ARC_INS_JL
"jli_s", // ARC_INS_JLI_S
"ldb_ab", // ARC_INS_LDB_AB
"ldb_aw", // ARC_INS_LDB_AW
"ldb_di_ab", // ARC_INS_LDB_DI_AB
"ldb_di_aw", // ARC_INS_LDB_DI_AW
"ldb_di", // ARC_INS_LDB_DI
"ldb_x_ab", // ARC_INS_LDB_X_AB
"ldb_x_aw", // ARC_INS_LDB_X_AW
"ldb_x_di_ab", // ARC_INS_LDB_X_DI_AB
"ldb_x_di_aw", // ARC_INS_LDB_X_DI_AW
"ldb_x_di", // ARC_INS_LDB_X_DI
"ldb_x", // ARC_INS_LDB_X
"ldb", // ARC_INS_LDB
"ldh_ab", // ARC_INS_LDH_AB
"ldh_aw", // ARC_INS_LDH_AW
"ldh_di_ab", // ARC_INS_LDH_DI_AB
"ldh_di_aw", // ARC_INS_LDH_DI_AW
"ldh_di", // ARC_INS_LDH_DI
"ldh_s_x", // ARC_INS_LDH_S_X
"ldh_x_ab", // ARC_INS_LDH_X_AB
"ldh_x_aw", // ARC_INS_LDH_X_AW
"ldh_x_di_ab", // ARC_INS_LDH_X_DI_AB
"ldh_x_di_aw", // ARC_INS_LDH_X_DI_AW
"ldh_x_di", // ARC_INS_LDH_X_DI
"ldh_x", // ARC_INS_LDH_X
"ldh", // ARC_INS_LDH
"ldi_s", // ARC_INS_LDI_S
"ld_ab", // ARC_INS_LD_AB
"ld_aw", // ARC_INS_LD_AW
"ld_di_ab", // ARC_INS_LD_DI_AB
"ld_di_aw", // ARC_INS_LD_DI_AW
"ld_di", // ARC_INS_LD_DI
"ld_s_as", // ARC_INS_LD_S_AS
"ld", // ARC_INS_LD
"leave_s", // ARC_INS_LEAVE_S
"lr", // ARC_INS_LR
"lsr", // ARC_INS_LSR
"lsr_f", // ARC_INS_LSR_F
"max", // ARC_INS_MAX
"max_f", // ARC_INS_MAX_F
"min", // ARC_INS_MIN
"min_f", // ARC_INS_MIN_F
"mov_s_ne", // ARC_INS_MOV_S_NE
"mov", // ARC_INS_MOV
"mov_f", // ARC_INS_MOV_F
"mpymu", // ARC_INS_MPYMU
"mpymu_f", // ARC_INS_MPYMU_F
"mpym", // ARC_INS_MPYM
"mpym_f", // ARC_INS_MPYM_F
"mpy", // ARC_INS_MPY
"mpy_f", // ARC_INS_MPY_F
"normh_f", // ARC_INS_NORMH_F
"normh", // ARC_INS_NORMH
"norm_f", // ARC_INS_NORM_F
"norm", // ARC_INS_NORM
"or", // ARC_INS_OR
"or_f", // ARC_INS_OR_F
"pop_s", // ARC_INS_POP_S
"push_s", // ARC_INS_PUSH_S
"ror", // ARC_INS_ROR
"ror_f", // ARC_INS_ROR_F
"rsub", // ARC_INS_RSUB
"rsub_f", // ARC_INS_RSUB_F
"sbc", // ARC_INS_SBC
"sbc_f", // ARC_INS_SBC_F
"seteq", // ARC_INS_SETEQ
"seteq_f", // ARC_INS_SETEQ_F
"sexb_f", // ARC_INS_SEXB_F
"sexb", // ARC_INS_SEXB
"sexh_f", // ARC_INS_SEXH_F
"sexh", // ARC_INS_SEXH
"stb_s", // ARC_INS_STB_S
"st_s", // ARC_INS_ST_S
"stb_ab", // ARC_INS_STB_AB
"stb_aw", // ARC_INS_STB_AW
"stb_di_ab", // ARC_INS_STB_DI_AB
"stb_di_aw", // ARC_INS_STB_DI_AW
"stb_di", // ARC_INS_STB_DI
"stb", // ARC_INS_STB
"sth_ab", // ARC_INS_STH_AB
"sth_aw", // ARC_INS_STH_AW
"sth_di_ab", // ARC_INS_STH_DI_AB
"sth_di_aw", // ARC_INS_STH_DI_AW
"sth_di", // ARC_INS_STH_DI
"sth_s", // ARC_INS_STH_S
"sth", // ARC_INS_STH
"st_ab", // ARC_INS_ST_AB
"st_aw", // ARC_INS_ST_AW
"st_di_ab", // ARC_INS_ST_DI_AB
"st_di_aw", // ARC_INS_ST_DI_AW
"st_di", // ARC_INS_ST_DI
"st", // ARC_INS_ST
"sub1", // ARC_INS_SUB1
"sub1_f", // ARC_INS_SUB1_F
"sub2", // ARC_INS_SUB2
"sub2_f", // ARC_INS_SUB2_F
"sub3", // ARC_INS_SUB3
"sub3_f", // ARC_INS_SUB3_F
"sub", // ARC_INS_SUB
"sub_f", // ARC_INS_SUB_F
"xor", // ARC_INS_XOR
"xor_f", // ARC_INS_XOR_F

3850
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19
external/capstone/arch/ARC/ARCGenCSOpGroup.inc vendored Normal file
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/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
ARC_OP_GROUP_Operand = 0,
ARC_OP_GROUP_PredicateOperand = 1,
ARC_OP_GROUP_MemOperandRI = 2,
ARC_OP_GROUP_BRCCPredicateOperand = 3,
ARC_OP_GROUP_CCOperand = 4,
ARC_OP_GROUP_U6 = 5,

80
external/capstone/arch/ARC/ARCGenCSRegEnum.inc vendored Normal file
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/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
ARC_REG_INVALID = 0,
ARC_REG_BLINK = 1,
ARC_REG_FP = 2,
ARC_REG_GP = 3,
ARC_REG_ILINK = 4,
ARC_REG_SP = 5,
ARC_REG_R0 = 6,
ARC_REG_R1 = 7,
ARC_REG_R2 = 8,
ARC_REG_R3 = 9,
ARC_REG_R4 = 10,
ARC_REG_R5 = 11,
ARC_REG_R6 = 12,
ARC_REG_R7 = 13,
ARC_REG_R8 = 14,
ARC_REG_R9 = 15,
ARC_REG_R10 = 16,
ARC_REG_R11 = 17,
ARC_REG_R12 = 18,
ARC_REG_R13 = 19,
ARC_REG_R14 = 20,
ARC_REG_R15 = 21,
ARC_REG_R16 = 22,
ARC_REG_R17 = 23,
ARC_REG_R18 = 24,
ARC_REG_R19 = 25,
ARC_REG_R20 = 26,
ARC_REG_R21 = 27,
ARC_REG_R22 = 28,
ARC_REG_R23 = 29,
ARC_REG_R24 = 30,
ARC_REG_R25 = 31,
ARC_REG_R30 = 32,
ARC_REG_R32 = 33,
ARC_REG_R33 = 34,
ARC_REG_R34 = 35,
ARC_REG_R35 = 36,
ARC_REG_R36 = 37,
ARC_REG_R37 = 38,
ARC_REG_R38 = 39,
ARC_REG_R39 = 40,
ARC_REG_R40 = 41,
ARC_REG_R41 = 42,
ARC_REG_R42 = 43,
ARC_REG_R43 = 44,
ARC_REG_R44 = 45,
ARC_REG_R45 = 46,
ARC_REG_R46 = 47,
ARC_REG_R47 = 48,
ARC_REG_R48 = 49,
ARC_REG_R49 = 50,
ARC_REG_R50 = 51,
ARC_REG_R51 = 52,
ARC_REG_R52 = 53,
ARC_REG_R53 = 54,
ARC_REG_R54 = 55,
ARC_REG_R55 = 56,
ARC_REG_R56 = 57,
ARC_REG_R57 = 58,
ARC_REG_R58 = 59,
ARC_REG_R59 = 60,
ARC_REG_R60 = 61,
ARC_REG_R61 = 62,
ARC_REG_R62 = 63,
ARC_REG_R63 = 64,
ARC_REG_STATUS32 = 65,
ARC_REG_ENDING, // 66

1803
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1616
external/capstone/arch/ARC/ARCGenInstrInfo.inc vendored Normal file
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296
external/capstone/arch/ARC/ARCGenRegisterInfo.inc vendored Normal file
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#ifdef GET_REGINFO_ENUM
#undef GET_REGINFO_ENUM
enum {
ARC_NoRegister,
ARC_BLINK = 1,
ARC_FP = 2,
ARC_GP = 3,
ARC_ILINK = 4,
ARC_SP = 5,
ARC_R0 = 6,
ARC_R1 = 7,
ARC_R2 = 8,
ARC_R3 = 9,
ARC_R4 = 10,
ARC_R5 = 11,
ARC_R6 = 12,
ARC_R7 = 13,
ARC_R8 = 14,
ARC_R9 = 15,
ARC_R10 = 16,
ARC_R11 = 17,
ARC_R12 = 18,
ARC_R13 = 19,
ARC_R14 = 20,
ARC_R15 = 21,
ARC_R16 = 22,
ARC_R17 = 23,
ARC_R18 = 24,
ARC_R19 = 25,
ARC_R20 = 26,
ARC_R21 = 27,
ARC_R22 = 28,
ARC_R23 = 29,
ARC_R24 = 30,
ARC_R25 = 31,
ARC_R30 = 32,
ARC_R32 = 33,
ARC_R33 = 34,
ARC_R34 = 35,
ARC_R35 = 36,
ARC_R36 = 37,
ARC_R37 = 38,
ARC_R38 = 39,
ARC_R39 = 40,
ARC_R40 = 41,
ARC_R41 = 42,
ARC_R42 = 43,
ARC_R43 = 44,
ARC_R44 = 45,
ARC_R45 = 46,
ARC_R46 = 47,
ARC_R47 = 48,
ARC_R48 = 49,
ARC_R49 = 50,
ARC_R50 = 51,
ARC_R51 = 52,
ARC_R52 = 53,
ARC_R53 = 54,
ARC_R54 = 55,
ARC_R55 = 56,
ARC_R56 = 57,
ARC_R57 = 58,
ARC_R58 = 59,
ARC_R59 = 60,
ARC_R60 = 61,
ARC_R61 = 62,
ARC_R62 = 63,
ARC_R63 = 64,
ARC_STATUS32 = 65,
NUM_TARGET_REGS // 66
};
// Register classes
enum {
ARC_SREGRegClassID = 0,
ARC_GPR_SRegClassID = 1,
ARC_GPR32RegClassID = 2,
ARC_GPR32_and_GPR_SRegClassID = 3,
};
#endif // GET_REGINFO_ENUM
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
#ifdef GET_REGINFO_MC_DESC
#undef GET_REGINFO_MC_DESC
static const MCPhysReg ARCRegDiffLists[] = {
/* 0 */ 0,
};
static const uint16_t ARCSubRegIdxLists[] = {
/* 0 */ 0,
};
static const MCRegisterDesc ARCRegDesc[] = { // Descriptors
{ 3, 0, 0, 0, 0, 0 },
{ 235, 0, 0, 0, 0, 0 },
{ 247, 0, 0, 0, 1, 0 },
{ 250, 0, 0, 0, 2, 0 },
{ 241, 0, 0, 0, 3, 0 },
{ 253, 0, 0, 0, 4, 0 },
{ 24, 0, 0, 0, 5, 0 },
{ 47, 0, 0, 0, 6, 0 },
{ 83, 0, 0, 0, 7, 0 },
{ 110, 0, 0, 0, 8, 0 },
{ 133, 0, 0, 0, 9, 0 },
{ 156, 0, 0, 0, 10, 0 },
{ 175, 0, 0, 0, 11, 0 },
{ 194, 0, 0, 0, 12, 0 },
{ 213, 0, 0, 0, 13, 0 },
{ 232, 0, 0, 0, 14, 0 },
{ 0, 0, 0, 0, 15, 0 },
{ 27, 0, 0, 0, 16, 0 },
{ 50, 0, 0, 0, 17, 0 },
{ 86, 0, 0, 0, 18, 0 },
{ 113, 0, 0, 0, 19, 0 },
{ 136, 0, 0, 0, 20, 0 },
{ 159, 0, 0, 0, 21, 0 },
{ 178, 0, 0, 0, 22, 0 },
{ 197, 0, 0, 0, 23, 0 },
{ 216, 0, 0, 0, 24, 0 },
{ 4, 0, 0, 0, 25, 0 },
{ 31, 0, 0, 0, 26, 0 },
{ 54, 0, 0, 0, 27, 0 },
{ 90, 0, 0, 0, 28, 0 },
{ 117, 0, 0, 0, 29, 0 },
{ 140, 0, 0, 0, 30, 0 },
{ 8, 0, 0, 0, 31, 0 },
{ 58, 0, 0, 0, 32, 0 },
{ 94, 0, 0, 0, 33, 0 },
{ 121, 0, 0, 0, 34, 0 },
{ 144, 0, 0, 0, 35, 0 },
{ 163, 0, 0, 0, 36, 0 },
{ 182, 0, 0, 0, 37, 0 },
{ 201, 0, 0, 0, 38, 0 },
{ 220, 0, 0, 0, 39, 0 },
{ 12, 0, 0, 0, 40, 0 },
{ 35, 0, 0, 0, 41, 0 },
{ 71, 0, 0, 0, 42, 0 },
{ 98, 0, 0, 0, 43, 0 },
{ 125, 0, 0, 0, 44, 0 },
{ 148, 0, 0, 0, 45, 0 },
{ 167, 0, 0, 0, 46, 0 },
{ 186, 0, 0, 0, 47, 0 },
{ 205, 0, 0, 0, 48, 0 },
{ 224, 0, 0, 0, 49, 0 },
{ 16, 0, 0, 0, 50, 0 },
{ 39, 0, 0, 0, 51, 0 },
{ 75, 0, 0, 0, 52, 0 },
{ 102, 0, 0, 0, 53, 0 },
{ 129, 0, 0, 0, 54, 0 },
{ 152, 0, 0, 0, 55, 0 },
{ 171, 0, 0, 0, 56, 0 },
{ 190, 0, 0, 0, 57, 0 },
{ 209, 0, 0, 0, 58, 0 },
{ 228, 0, 0, 0, 59, 0 },
{ 20, 0, 0, 0, 60, 0 },
{ 43, 0, 0, 0, 61, 0 },
{ 79, 0, 0, 0, 62, 0 },
{ 106, 0, 0, 0, 63, 0 },
{ 62, 0, 0, 0, 64, 0 },
};
// SREG Register Class...
static const MCPhysReg SREG[] = {
ARC_STATUS32,
};
// SREG Bit set.
static const uint8_t SREGBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
};
// GPR_S Register Class...
static const MCPhysReg GPR_S[] = {
ARC_R0, ARC_R1, ARC_R2, ARC_R3, ARC_R12, ARC_R13, ARC_R14, ARC_R15,
};
// GPR_S Bit set.
static const uint8_t GPR_SBits[] = {
0xc0, 0x03, 0x3c,
};
// GPR32 Register Class...
static const MCPhysReg GPR32[] = {
ARC_R0, ARC_R1, ARC_R2, ARC_R3, ARC_R4, ARC_R5, ARC_R6, ARC_R7, ARC_R8, ARC_R9, ARC_R10, ARC_R11, ARC_R12, ARC_R13, ARC_R14, ARC_R15, ARC_R16, ARC_R17, ARC_R18, ARC_R19, ARC_R20, ARC_R21, ARC_R22, ARC_R23, ARC_R24, ARC_R25, ARC_GP, ARC_FP, ARC_SP, ARC_ILINK, ARC_R30, ARC_BLINK, ARC_R32, ARC_R33, ARC_R34, ARC_R35, ARC_R36, ARC_R37, ARC_R38, ARC_R39, ARC_R40, ARC_R41, ARC_R42, ARC_R43, ARC_R44, ARC_R45, ARC_R46, ARC_R47, ARC_R48, ARC_R49, ARC_R50, ARC_R51, ARC_R52, ARC_R53, ARC_R54, ARC_R55, ARC_R56, ARC_R57, ARC_R58, ARC_R59, ARC_R60, ARC_R61, ARC_R62, ARC_R63,
};
// GPR32 Bit set.
static const uint8_t GPR32Bits[] = {
0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01,
};
// GPR32_and_GPR_S Register Class...
static const MCPhysReg GPR32_and_GPR_S[] = {
ARC_R0, ARC_R1, ARC_R2, ARC_R3, ARC_R12, ARC_R13, ARC_R14, ARC_R15,
};
// GPR32_and_GPR_S Bit set.
static const uint8_t GPR32_and_GPR_SBits[] = {
0xc0, 0x03, 0x3c,
};
static const MCRegisterClass ARCMCRegisterClasses[] = {
{ SREG, SREGBits, sizeof(SREGBits) },
{ GPR_S, GPR_SBits, sizeof(GPR_SBits) },
{ GPR32, GPR32Bits, sizeof(GPR32Bits) },
{ GPR32_and_GPR_S, GPR32_and_GPR_SBits, sizeof(GPR32_and_GPR_SBits) },
};
static const uint16_t ARCRegEncodingTable[] = {
0,
31,
27,
26,
29,
28,
0,
1,
2,
3,
4,
5,
6,
7,
8,
9,
10,
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
30,
32,
33,
34,
35,
36,
37,
38,
39,
40,
41,
42,
43,
44,
45,
46,
47,
48,
49,
50,
51,
52,
53,
54,
55,
56,
57,
58,
59,
60,
61,
62,
63,
10,
};
#endif // GET_REGINFO_MC_DESC

24
external/capstone/arch/ARC/ARCGenSubtargetInfo.inc vendored Normal file
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/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
#ifdef GET_SUBTARGETINFO_ENUM
#undef GET_SUBTARGETINFO_ENUM
enum {
ARC_FeatureNORM = 0,
ARC_NumSubtargetFeatures = 1
};
#endif // GET_SUBTARGETINFO_ENUM

72
external/capstone/arch/ARC/ARCInfo.h vendored Normal file
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/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2023 */
/* Automatically translated source file from LLVM. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Only small edits allowed. */
/* For multiple similar edits, please create a Patch for the translator. */
/* Capstone's C++ file translator: */
/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
//===- ARCInfo.h - Additional ARC Info --------------------------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file contains small standalone helper functions and enum definitions for
// the ARC target useful for the compiler back-end and the MC libraries.
// As such, it deliberately does not include references to LLVM core
// code gen types, passes, etc..
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_LIB_TARGET_ARC_MCTARGETDESC_ARCINFO_H
#define LLVM_LIB_TARGET_ARC_MCTARGETDESC_ARCINFO_H
// Enums corresponding to ARC condition codes
// CS namespace begin: ARCCC
typedef enum ARCCondCode {
ARCCC_AL = 0x0,
ARCCC_EQ = 0x1,
ARCCC_NE = 0x2,
ARCCC_P = 0x3,
ARCCC_N = 0x4,
ARCCC_LO = 0x5,
ARCCC_HS = 0x6,
ARCCC_VS = 0x7,
ARCCC_VC = 0x8,
ARCCC_GT = 0x9,
ARCCC_GE = 0xa,
ARCCC_LT = 0xb,
ARCCC_LE = 0xc,
ARCCC_HI = 0xd,
ARCCC_LS = 0xe,
ARCCC_PNZ = 0xf,
ARCCC_Z = 0x11, // Low 4-bits = EQ
ARCCC_NZ = 0x12 // Low 4-bits = NE
} ARCCC_CondCode;
typedef enum BRCondCode {
ARCCC_BREQ = 0x0,
ARCCC_BRNE = 0x1,
ARCCC_BRLT = 0x2,
ARCCC_BRGE = 0x3,
ARCCC_BRLO = 0x4,
ARCCC_BRHS = 0x5
} ARCCC_BRCondCode;
// CS namespace end: ARCCC
// end namespace ARCCC
// end namespace llvm
#endif

210
external/capstone/arch/ARC/ARCInstPrinter.c vendored Normal file
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@@ -0,0 +1,210 @@
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2023 */
/* Automatically translated source file from LLVM. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Only small edits allowed. */
/* For multiple similar edits, please create a Patch for the translator. */
/* Capstone's C++ file translator: */
/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
//===- ARCInstPrinter.cpp - ARC MCInst to assembly syntax -------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This class prints an ARC MCInst to a .s file.
//
//===----------------------------------------------------------------------===//
#ifdef CAPSTONE_HAS_ARC
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <capstone/platform.h>
#include "../../SStream.h"
#include "../../MCInst.h"
#include "../../MCInstPrinter.h"
#include "ARCInfo.h"
#include "ARCInstPrinter.h"
#include "ARCLinkage.h"
#include "ARCMapping.h"
#define CONCAT(a, b) CONCAT_(a, b)
#define CONCAT_(a, b) a##_##b
#define DEBUG_TYPE "asm-printer"
#include "ARCGenAsmWriter.inc"
static const char *ARCBRCondCodeToString(ARCCC_BRCondCode BRCC)
{
switch (BRCC) {
case ARCCC_BREQ:
return "eq";
case ARCCC_BRNE:
return "ne";
case ARCCC_BRLT:
return "lt";
case ARCCC_BRGE:
return "ge";
case ARCCC_BRLO:
return "lo";
case ARCCC_BRHS:
return "hs";
}
// CS_ASSERT(0 && "Unknown condition code passed");
return "";
}
static const char *ARCCondCodeToString(ARCCC_CondCode CC)
{
switch (CC) {
case ARCCC_EQ:
return "eq";
case ARCCC_NE:
return "ne";
case ARCCC_P:
return "p";
case ARCCC_N:
return "n";
case ARCCC_HS:
return "hs";
case ARCCC_LO:
return "lo";
case ARCCC_GT:
return "gt";
case ARCCC_GE:
return "ge";
case ARCCC_VS:
return "vs";
case ARCCC_VC:
return "vc";
case ARCCC_LT:
return "lt";
case ARCCC_LE:
return "le";
case ARCCC_HI:
return "hi";
case ARCCC_LS:
return "ls";
case ARCCC_PNZ:
return "pnz";
case ARCCC_AL:
return "al";
case ARCCC_NZ:
return "nz";
case ARCCC_Z:
return "z";
}
// CS_ASSERT(0 && "Unknown condition code passed");
return "";
}
static void printRegName(SStream *OS, MCRegister Reg)
{
SStream_concat0(OS, getRegisterName(Reg));
}
static void printInst(MCInst *MI, uint64_t Address, const char *Annot, SStream *O)
{
printInstruction(MI, Address, O);
}
static void printOperand(MCInst *MI, unsigned OpNum, SStream *O)
{
add_cs_detail(MI, ARC_OP_GROUP_Operand, OpNum);
MCOperand *Op = MCInst_getOperand(MI, (OpNum));
if (MCOperand_isReg(Op)) {
printRegName(O, MCOperand_getReg(Op));
} else if (MCOperand_isImm(Op)) {
SStream_concat(O, "%" PRId64, MCOperand_getImm(Op));
} else if (MCOperand_isExpr(Op)) {
printExpr(O, MCOperand_getExpr(Op));
}
}
static void printOperandAddr(MCInst *MI, uint64_t Address, unsigned OpNum, SStream *O)
{
printOperand(MI, OpNum, O);
}
static void printMemOperandRI(MCInst *MI, unsigned OpNum, SStream *O)
{
add_cs_detail(MI, ARC_OP_GROUP_MemOperandRI, OpNum);
MCOperand *base = MCInst_getOperand(MI, (OpNum));
MCOperand *offset = MCInst_getOperand(MI, (OpNum + 1));
CS_ASSERT((MCOperand_isReg(base) && "Base should be register."));
CS_ASSERT((MCOperand_isImm(offset) && "Offset should be immediate."));
printRegName(O, MCOperand_getReg(base));
SStream_concat(O, "%s", ",");
printInt64(O, MCOperand_getImm(offset));
}
static void printPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O)
{
add_cs_detail(MI, ARC_OP_GROUP_PredicateOperand, OpNum);
MCOperand *Op = MCInst_getOperand(MI, (OpNum));
CS_ASSERT((MCOperand_isImm(Op) && "Predicate operand is immediate."));
SStream_concat0(
O, ARCCondCodeToString((ARCCC_CondCode)MCOperand_getImm(Op)));
}
static void printBRCCPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O)
{
add_cs_detail(MI, ARC_OP_GROUP_BRCCPredicateOperand, OpNum);
MCOperand *Op = MCInst_getOperand(MI, (OpNum));
CS_ASSERT((MCOperand_isImm(Op) && "Predicate operand is immediate."));
SStream_concat0(O, ARCBRCondCodeToString(
(ARCCC_BRCondCode)MCOperand_getImm(Op)));
}
static void printCCOperand(MCInst *MI, int OpNum, SStream *O)
{
add_cs_detail(MI, ARC_OP_GROUP_CCOperand, OpNum);
SStream_concat0(O, ARCCondCodeToString((ARCCC_CondCode)MCOperand_getImm(
MCInst_getOperand(MI, (OpNum)))));
}
static void printU6ShiftedBy(unsigned ShiftBy, MCInst *MI, int OpNum, SStream *O)
{
MCOperand *MO = MCInst_getOperand(MI, (OpNum));
if (MCOperand_isImm(MO)) {
unsigned Value = MCOperand_getImm(MO);
unsigned Value2 = Value >> ShiftBy;
if (Value2 > 0x3F || (Value2 << ShiftBy != Value)) {
CS_ASSERT((false && "instruction has wrong format"));
}
}
printOperand(MI, OpNum, O);
}
static void printU6(MCInst *MI, int OpNum, SStream *O)
{
add_cs_detail(MI, ARC_OP_GROUP_U6, OpNum);
printU6ShiftedBy(0, MI, OpNum, O);
}
void ARC_LLVM_printInst(MCInst *MI, uint64_t Address, const char *Annot,
SStream *O)
{
printInst(MI, Address, Annot, O);
}
const char *ARC_LLVM_getRegisterName(unsigned RegNo)
{
return getRegisterName(RegNo);
}
#endif

58
external/capstone/arch/ARC/ARCInstPrinter.h vendored Normal file
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@@ -0,0 +1,58 @@
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2023 */
/* Automatically translated source file from LLVM. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Only small edits allowed. */
/* For multiple similar edits, please create a Patch for the translator. */
/* Capstone's C++ file translator: */
/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
//===- ARCInstPrinter.h - Convert ARC MCInst to assembly syntax -*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
///
/// \file
/// This file contains the declaration of the ARCInstPrinter class,
/// which is used to print ARC MCInst to a .s file.
///
//===----------------------------------------------------------------------===//
#ifndef LLVM_LIB_TARGET_ARC_INSTPRINTER_ARCINSTPRINTER_H
#define LLVM_LIB_TARGET_ARC_INSTPRINTER_ARCINSTPRINTER_H
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <capstone/platform.h>
#include "../../SStream.h"
#include "../../MCInst.h"
#define CONCAT(a, b) CONCAT_(a, b)
#define CONCAT_(a, b) a##_##b
// Autogenerated by tblgen.
static void printInstruction(MCInst *MI, uint64_t Address, SStream *O);
static void printRegName(SStream *OS, MCRegister Reg);
static void printInst(MCInst *MI, uint64_t Address, const char *Annot, SStream *O);
static void printCCOperand(MCInst *MI, int OpNum, SStream *O);
static void printU6(MCInst *MI, int OpNum, SStream *O);
static void printMemOperandRI(MCInst *MI, unsigned OpNum, SStream *O);
static void printOperand(MCInst *MI, unsigned OpNum, SStream *O);
static void printOperandAddr(MCInst *MI, uint64_t Address, unsigned OpNum, SStream *O);
static void printPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O);
static void printBRCCPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O);
static void printU6ShiftedBy(unsigned ShiftBy, MCInst *MI, int OpNum, SStream *O);
;
// end namespace llvm
#endif // LLVM_LIB_TARGET_ARC_INSTPRINTER_ARCINSTPRINTER_H

23
external/capstone/arch/ARC/ARCLinkage.h vendored Normal file
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@@ -0,0 +1,23 @@
/* Capstone Disassembly Engine */
/* By Dmitry Sibirtsev <sibirtsevdl@gmail.com>, 2024 */
#ifndef CS_ARC_LINKAGE_H
#define CS_ARC_LINKAGE_H
// Function definitions to call static LLVM functions.
#include "../../MCDisassembler.h"
#include "../../MCInst.h"
#include "../../MCRegisterInfo.h"
#include "../../SStream.h"
#include "capstone/capstone.h"
const char *ARC_LLVM_getRegisterName(unsigned RegNo);
void ARC_LLVM_printInst(MCInst *MI, uint64_t Address, const char *Annot,
SStream *O);
DecodeStatus ARC_LLVM_getInstruction(MCInst *MI, uint64_t *Size,
const uint8_t *Bytes,
size_t BytesLen, uint64_t Address,
SStream *CS);
#endif // CS_ARC_LINKAGE_H

290
external/capstone/arch/ARC/ARCMapping.c vendored Normal file
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@@ -0,0 +1,290 @@
/* Capstone Disassembly Engine */
/* By Dmitry Sibirtsev <sibirtsevdl@gmail.com>, 2024 */
#ifdef CAPSTONE_HAS_ARC
#include <stdio.h>
#include <string.h>
#include <capstone/capstone.h>
#include <capstone/arc.h>
#include "../../Mapping.h"
#include "../../MCDisassembler.h"
#include "../../cs_priv.h"
#include "../../cs_simple_types.h"
#include "ARCMapping.h"
#include "ARCLinkage.h"
#define GET_REGINFO_ENUM
#define GET_REGINFO_MC_DESC
#include "ARCGenRegisterInfo.inc"
#define GET_INSTRINFO_ENUM
#include "ARCGenInstrInfo.inc"
void ARC_init_mri(MCRegisterInfo *MRI)
{
MCRegisterInfo_InitMCRegisterInfo(MRI, ARCRegDesc,
sizeof(ARCRegDesc), 0, 0,
ARCMCRegisterClasses,
ARR_SIZE(ARCMCRegisterClasses),
0, 0, ARCRegDiffLists, 0,
ARCSubRegIdxLists,
ARR_SIZE(ARCSubRegIdxLists), 0);
}
const char *ARC_reg_name(csh handle, unsigned int reg)
{
return ARC_LLVM_getRegisterName(reg);
}
void ARC_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
{
// Not used by ARC. Information is set after disassembly.
}
static const char *const insn_name_maps[] = {
#include "ARCGenCSMappingInsnName.inc"
};
const char *ARC_insn_name(csh handle, unsigned int id)
{
#ifndef CAPSTONE_DIET
if (id < ARR_SIZE(insn_name_maps))
return insn_name_maps[id];
// not found
return NULL;
#else
return NULL;
#endif
}
#ifndef CAPSTONE_DIET
static const name_map group_name_maps[] = {
{ ARC_GRP_INVALID, NULL },
{ ARC_GRP_JUMP, "jump" },
{ ARC_GRP_CALL, "call" },
{ ARC_GRP_RET, "return" },
{ ARC_GRP_BRANCH_RELATIVE, "branch_relative" },
};
#endif
const char *ARC_group_name(csh handle, unsigned int id)
{
#ifndef CAPSTONE_DIET
return id2name(group_name_maps, ARR_SIZE(group_name_maps), id);
#else
return NULL;
#endif
}
void ARC_reg_access(const cs_insn *insn, cs_regs regs_read,
uint8_t *regs_read_count, cs_regs regs_write,
uint8_t *regs_write_count)
{
uint8_t i;
uint8_t read_count, write_count;
cs_arc *arc = &(insn->detail->arc);
read_count = insn->detail->regs_read_count;
write_count = insn->detail->regs_write_count;
// implicit registers
memcpy(regs_read, insn->detail->regs_read,
read_count * sizeof(insn->detail->regs_read[0]));
memcpy(regs_write, insn->detail->regs_write,
write_count * sizeof(insn->detail->regs_write[0]));
// explicit registers
for (i = 0; i < arc->op_count; i++) {
cs_arc_op *op = &(arc->operands[i]);
switch ((int)op->type) {
case ARC_OP_REG:
if ((op->access & CS_AC_READ) &&
!arr_exist(regs_read, read_count, op->reg)) {
regs_read[read_count] = (uint16_t)op->reg;
read_count++;
}
if ((op->access & CS_AC_WRITE) &&
!arr_exist(regs_write, write_count, op->reg)) {
regs_write[write_count] = (uint16_t)op->reg;
write_count++;
}
break;
default:
break;
}
}
*regs_read_count = read_count;
*regs_write_count = write_count;
}
const insn_map arc_insns[] = {
#include "ARCGenCSMappingInsn.inc"
};
void ARC_set_instr_map_data(MCInst *MI)
{
map_cs_id(MI, arc_insns, ARR_SIZE(arc_insns));
map_implicit_reads(MI, arc_insns);
map_implicit_writes(MI, arc_insns);
map_groups(MI, arc_insns);
}
bool ARC_getInstruction(csh handle, const uint8_t *code, size_t code_len,
MCInst *instr, uint16_t *size, uint64_t address,
void *info)
{
uint64_t temp_size;
ARC_init_cs_detail(instr);
DecodeStatus Result = ARC_LLVM_getInstruction(instr, &temp_size, code,
code_len, address, info);
ARC_set_instr_map_data(instr);
*size = temp_size;
if (Result == MCDisassembler_SoftFail) {
MCInst_setSoftFail(instr);
}
return Result != MCDisassembler_Fail;
}
void ARC_printer(MCInst *MI, SStream *O,
void * /* MCRegisterInfo* */ info)
{
MCRegisterInfo *MRI = (MCRegisterInfo *)info;
MI->MRI = MRI;
ARC_LLVM_printInst(MI, MI->address, "", O);
}
void ARC_setup_op(cs_arc_op *op)
{
memset(op, 0, sizeof(cs_arc_op));
op->type = ARC_OP_INVALID;
}
void ARC_init_cs_detail(MCInst *MI)
{
if (!detail_is_set(MI)) {
return;
}
unsigned int i;
memset(get_detail(MI), 0,
offsetof(cs_detail, arc) + sizeof(cs_arc));
for (i = 0; i < ARR_SIZE(ARC_get_detail(MI)->operands);
i++)
ARC_setup_op(
&ARC_get_detail(MI)->operands[i]);
}
static const map_insn_ops insn_operands[] = {
#include "ARCGenCSMappingInsnOp.inc"
};
void ARC_set_detail_op_imm(MCInst *MI, unsigned OpNum,
arc_op_type ImmType, int64_t Imm)
{
if (!detail_is_set(MI))
return;
ARC_check_safe_inc(MI);
CS_ASSERT((map_get_op_type(MI, OpNum) & ~CS_OP_MEM) == CS_OP_IMM);
CS_ASSERT(ImmType == ARC_OP_IMM);
ARC_get_detail_op(MI, 0)->type = ImmType;
ARC_get_detail_op(MI, 0)->imm = Imm;
ARC_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum);
ARC_inc_op_count(MI);
}
void ARC_set_detail_op_reg(MCInst *MI, unsigned OpNum, arc_reg Reg)
{
if (!detail_is_set(MI))
return;
ARC_check_safe_inc(MI);
CS_ASSERT((map_get_op_type(MI, OpNum) & ~CS_OP_MEM) == CS_OP_REG);
ARC_get_detail_op(MI, 0)->type = ARC_OP_REG;
ARC_get_detail_op(MI, 0)->reg = Reg;
ARC_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum);
ARC_inc_op_count(MI);
}
void ARC_add_cs_detail(MCInst *MI, int op_group,
va_list args)
{
if (!detail_is_set(MI))
return;
unsigned OpNum = va_arg(args, unsigned);
cs_op_type op_type = map_get_op_type(MI, OpNum);
cs_op_type base_op_type = op_type;
cs_op_type offset_op_type;
// Fill cs_detail
switch (op_group) {
default:
printf("ERROR: Operand group %d not handled!\n", op_group);
CS_ASSERT_RET(0);
case ARC_OP_GROUP_Operand:
if (op_type == CS_OP_IMM) {
ARC_set_detail_op_imm(MI, OpNum, ARC_OP_IMM,
MCInst_getOpVal(MI, OpNum));
} else if (op_type == CS_OP_REG) {
ARC_set_detail_op_reg(MI, OpNum,
MCInst_getOpVal(MI, OpNum));
} else {
// Expression
ARC_set_detail_op_imm(MI, OpNum, ARC_OP_IMM,
MCOperand_getImm(MCInst_getOperand(MI, OpNum)));
}
break;
case ARC_OP_GROUP_PredicateOperand:
if (op_type == CS_OP_IMM) {
ARC_set_detail_op_imm(MI, OpNum, ARC_OP_IMM,
MCInst_getOpVal(MI, OpNum));
} else
CS_ASSERT(0 && "Op type not handled.");
break;
case ARC_OP_GROUP_MemOperandRI:
if (base_op_type == CS_OP_REG) {
ARC_set_detail_op_reg(MI, OpNum,
MCInst_getOpVal(MI, OpNum));
} else
CS_ASSERT(0 && "Op type not handled.");
offset_op_type = map_get_op_type(MI, OpNum+1);
if (offset_op_type == CS_OP_IMM) {
ARC_set_detail_op_imm(MI, OpNum+1, ARC_OP_IMM,
MCInst_getOpVal(MI, OpNum+1));
} else
CS_ASSERT(0 && "Op type not handled.");
break;
case ARC_OP_GROUP_BRCCPredicateOperand:
if (op_type == CS_OP_IMM) {
ARC_set_detail_op_imm(MI, OpNum, ARC_OP_IMM,
MCInst_getOpVal(MI, OpNum));
} else
CS_ASSERT(0 && "Op type not handled.");
break;
case ARC_OP_GROUP_CCOperand:
if (op_type == CS_OP_IMM) {
ARC_set_detail_op_imm(MI, OpNum, ARC_OP_IMM,
MCInst_getOpVal(MI, OpNum));
} else
CS_ASSERT(0 && "Op type not handled.");
break;
case ARC_OP_GROUP_U6:
if (op_type == CS_OP_IMM) {
ARC_set_detail_op_imm(MI, OpNum, ARC_OP_IMM,
MCInst_getOpVal(MI, OpNum));
} else
CS_ASSERT(0 && "Op type not handled.");
break;
}
}
#endif

55
external/capstone/arch/ARC/ARCMapping.h vendored Normal file
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@@ -0,0 +1,55 @@
/* Capstone Disassembly Engine */
/* By Dmitry Sibirtsev <sibirtsevdl@gmail.com>, 2024 */
#ifndef CS_ARC_MAP_H
#define CS_ARC_MAP_H
#include "../../Mapping.h"
#include "../../include/capstone/capstone.h"
#include "../../utils.h"
typedef enum {
#include "ARCGenCSOpGroup.inc"
} arc_op_group;
void ARC_init_mri(MCRegisterInfo *MRI);
// return name of register in friendly string
const char *ARC_reg_name(csh handle, unsigned int reg);
void ARC_printer(MCInst *MI, SStream *O,
void * /* MCRegisterInfo* */ info);
// given internal insn id, return public instruction ID
void ARC_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
const char *ARC_insn_name(csh handle, unsigned int id);
const char *ARC_group_name(csh handle, unsigned int id);
void ARC_reg_access(const cs_insn *insn, cs_regs regs_read,
uint8_t *regs_read_count, cs_regs regs_write,
uint8_t *regs_write_count);
bool ARC_getInstruction(csh handle, const uint8_t *code, size_t code_len,
MCInst *instr, uint16_t *size, uint64_t address,
void *info);
// cs_detail related functions
void ARC_init_cs_detail(MCInst *MI);
void ARC_set_detail_op_imm(MCInst *MI, unsigned OpNum,
arc_op_type ImmType, int64_t Imm);
void ARC_add_cs_detail(MCInst *MI, int /* arc_op_group */ op_group,
va_list args);
static inline void add_cs_detail(MCInst *MI,
int /* arc_op_group */ op_group, ...)
{
if (!detail_is_set(MI))
return;
va_list args;
va_start(args, op_group);
ARC_add_cs_detail(MI, op_group, args);
va_end(args);
}
#endif

52
external/capstone/arch/ARC/ARCModule.c vendored Normal file
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@@ -0,0 +1,52 @@
/* Capstone Disassembly Engine */
/* By Dmitry Sibirtsev <sibirtsevdl@gmail.com>, 2024 */
#ifdef CAPSTONE_HAS_ARC
#include <capstone/capstone.h>
#include "ARCModule.h"
#include "../../MCRegisterInfo.h"
#include "../../cs_priv.h"
#include "ARCMapping.h"
cs_err ARC_global_init(cs_struct *ud)
{
MCRegisterInfo *mri;
mri = cs_mem_malloc(sizeof(*mri));
ARC_init_mri(mri);
ud->printer = ARC_printer;
ud->printer_info = mri;
ud->reg_name = ARC_reg_name;
ud->insn_id = ARC_get_insn_id;
ud->insn_name = ARC_insn_name;
ud->group_name = ARC_group_name;
ud->post_printer = NULL;
#ifndef CAPSTONE_DIET
ud->reg_access = ARC_reg_access;
#endif
ud->disasm = ARC_getInstruction;
return CS_ERR_OK;
}
cs_err ARC_option(cs_struct *handle, cs_opt_type type, size_t value)
{
switch (type) {
case CS_OPT_MODE:
handle->mode = (cs_mode)value;
break;
case CS_OPT_SYNTAX:
handle->syntax |= (int)value;
break;
default:
break;
}
return CS_ERR_OK;
}
#endif

12
external/capstone/arch/ARC/ARCModule.h vendored Normal file
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@@ -0,0 +1,12 @@
/* Capstone Disassembly Engine */
/* By Dmitry Sibirtsev <sibirtsevdl@gmail.com>, 2024 */
#ifndef CS_ARC_MODULE_H
#define CS_ARC_MODULE_H
#include "../../utils.h"
cs_err ARC_global_init(cs_struct *ud);
cs_err ARC_option(cs_struct *handle, cs_opt_type type, size_t value);
#endif

2
external/capstone/arch/ARM/ARMGenCSMappingInsnOp.inc vendored
View File

@@ -36878,7 +36878,7 @@
{
{ CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
{ CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
{ CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
{ CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
{ CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */
{ 0 }
}},

9
external/capstone/arch/ARM/ARMMapping.c vendored
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@@ -816,11 +816,14 @@ bool ARM_getInstruction(csh handle, const uint8_t *code, size_t code_len,
void *info)
{
ARM_init_cs_detail(instr);
bool Result = ARM_LLVM_getInstruction(handle, code, code_len, instr,
DecodeStatus Result = ARM_LLVM_getInstruction(handle, code, code_len, instr,
size, address,
info) != MCDisassembler_Fail;
info);
ARM_set_instr_map_data(instr);
return Result;
if (Result == MCDisassembler_SoftFail) {
MCInst_setSoftFail(instr);
}
return Result != MCDisassembler_Fail;
}
#define GET_REGINFO_MC_DESC

7
external/capstone/arch/Alpha/AlphaMapping.c vendored
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@@ -173,10 +173,13 @@ bool Alpha_getInstruction(csh handle, const uint8_t *code,
uint16_t *size, uint64_t address, void *info)
{
Alpha_init_cs_detail(instr);
bool Result = Alpha_LLVM_getInstruction(handle, code, code_len, instr, size,
DecodeStatus Result = Alpha_LLVM_getInstruction(handle, code, code_len, instr, size,
address, info);
Alpha_set_instr_map_data(instr);
return Result;
if (Result == MCDisassembler_SoftFail) {
MCInst_setSoftFail(instr);
}
return Result != MCDisassembler_Fail;
}
#endif

4
external/capstone/arch/BPF/BPFDisassembler.c vendored
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@@ -539,9 +539,7 @@ static bpf_insn op2insn_st(unsigned opcode, const uint32_t imm)
CASE(DW);
}
CS_ASSERT_RET_VAL(
false && "Malformed atomic BPF instruction",
BPF_INS_INVALID);
return BPF_INS_INVALID;
}
#undef CASE

38
external/capstone/arch/EVM/EVMDisassembler.c vendored
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@@ -1,5 +1,6 @@
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh, 2018 */
/* By Andelf, 2025 */
#include <string.h>
#include <stddef.h> // offsetof macro
@@ -36,9 +37,9 @@ static const short opcodes[256] = {
EVM_INS_XOR,
EVM_INS_NOT,
EVM_INS_BYTE,
-1,
-1,
-1,
EVM_INS_SHL,
EVM_INS_SHR,
EVM_INS_SAR,
-1,
-1,
EVM_INS_SHA3,
@@ -79,11 +80,11 @@ static const short opcodes[256] = {
EVM_INS_NUMBER,
EVM_INS_DIFFICULTY,
EVM_INS_GASLIMIT,
-1,
-1,
-1,
-1,
-1,
EVM_INS_CHAINID,
EVM_INS_SELFBALANCE,
EVM_INS_BASEFEE,
EVM_INS_BLOBHASH,
EVM_INS_BLOBBASEFEE,
-1,
-1,
-1,
@@ -101,10 +102,10 @@ static const short opcodes[256] = {
EVM_INS_MSIZE,
EVM_INS_GAS,
EVM_INS_JUMPDEST,
-1,
-1,
-1,
-1,
EVM_INS_TLOAD,
EVM_INS_TSTORE,
EVM_INS_MCOPY,
EVM_INS_PUSH0,
EVM_INS_PUSH1,
EVM_INS_PUSH2,
EVM_INS_PUSH3,
@@ -254,7 +255,7 @@ static const short opcodes[256] = {
EVM_INS_CALLCODE,
EVM_INS_RETURN,
EVM_INS_DELEGATECALL,
EVM_INS_CALLBLACKBOX,
EVM_INS_CREATE2,
-1,
-1,
-1,
@@ -264,7 +265,7 @@ static const short opcodes[256] = {
-1,
EVM_INS_REVERT,
-1,
EVM_INS_SUICIDE,
EVM_INS_SELFDESTRUCT,
};
bool EVM_getInstruction(csh ud, const uint8_t *code, size_t code_len,
@@ -326,6 +327,9 @@ bool EVM_getInstruction(csh ud, const uint8_t *code, size_t code_len,
case EVM_INS_MULMOD:
case EVM_INS_EXP:
case EVM_INS_SIGNEXTEND:
case EVM_INS_SHL:
case EVM_INS_SHR:
case EVM_INS_SAR:
MI->flat_insn->detail->groups[MI->flat_insn->detail->groups_count] = EVM_GRP_MATH;
MI->flat_insn->detail->groups_count++;
break;
@@ -335,6 +339,7 @@ bool EVM_getInstruction(csh ud, const uint8_t *code, size_t code_len,
case EVM_INS_CALLDATACOPY:
case EVM_INS_CODECOPY:
case EVM_INS_EXTCODECOPY:
case EVM_INS_MCOPY:
MI->flat_insn->detail->groups[MI->flat_insn->detail->groups_count] = EVM_GRP_MEM_WRITE;
MI->flat_insn->detail->groups_count++;
break;
@@ -346,16 +351,19 @@ bool EVM_getInstruction(csh ud, const uint8_t *code, size_t code_len,
case EVM_INS_RETURN:
case EVM_INS_DELEGATECALL:
case EVM_INS_REVERT:
case EVM_INS_CREATE2:
MI->flat_insn->detail->groups[MI->flat_insn->detail->groups_count] = EVM_GRP_MEM_READ;
MI->flat_insn->detail->groups_count++;
break;
case EVM_INS_SSTORE:
case EVM_INS_TSTORE:
MI->flat_insn->detail->groups[MI->flat_insn->detail->groups_count] = EVM_GRP_STORE_WRITE;
MI->flat_insn->detail->groups_count++;
break;
case EVM_INS_SLOAD:
case EVM_INS_TLOAD:
MI->flat_insn->detail->groups[MI->flat_insn->detail->groups_count] = EVM_GRP_STORE_READ;
MI->flat_insn->detail->groups_count++;
break;
@@ -367,7 +375,7 @@ bool EVM_getInstruction(csh ud, const uint8_t *code, size_t code_len,
break;
case EVM_INS_STOP:
case EVM_INS_SUICIDE:
case EVM_INS_SELFDESTRUCT:
MI->flat_insn->detail->groups[MI->flat_insn->detail->groups_count] = EVM_GRP_HALT;
MI->flat_insn->detail->groups_count++;
break;

29
external/capstone/arch/EVM/EVMMapping.c vendored
View File

@@ -1,5 +1,6 @@
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh, 2018 */
/* By Andelf, 2025 */
#ifdef CAPSTONE_HAS_EVM
@@ -73,9 +74,9 @@ static const name_map insn_name_maps[256] = {
{ EVM_INS_XOR, "xor" },
{ EVM_INS_NOT, "not" },
{ EVM_INS_BYTE, "byte" },
{ EVM_INS_INVALID, NULL },
{ EVM_INS_INVALID, NULL },
{ EVM_INS_INVALID, NULL },
{ EVM_INS_SHL, "shl" },
{ EVM_INS_SHR, "shr" },
{ EVM_INS_SAR, "sar" },
{ EVM_INS_INVALID, NULL },
{ EVM_INS_INVALID, NULL },
{ EVM_INS_SHA3, "sha3" },
@@ -116,11 +117,11 @@ static const name_map insn_name_maps[256] = {
{ EVM_INS_NUMBER, "number" },
{ EVM_INS_DIFFICULTY, "difficulty" },
{ EVM_INS_GASLIMIT, "gaslimit" },
{ EVM_INS_INVALID, NULL },
{ EVM_INS_INVALID, NULL },
{ EVM_INS_INVALID, NULL },
{ EVM_INS_INVALID, NULL },
{ EVM_INS_INVALID, NULL },
{ EVM_INS_CHAINID, "chainid" },
{ EVM_INS_SELFBALANCE, "selfbalance" },
{ EVM_INS_BASEFEE, "basefee" },
{ EVM_INS_BLOBHASH, "blobhash" },
{ EVM_INS_BLOBBASEFEE, "blobbasefee" },
{ EVM_INS_INVALID, NULL },
{ EVM_INS_INVALID, NULL },
{ EVM_INS_INVALID, NULL },
@@ -138,10 +139,10 @@ static const name_map insn_name_maps[256] = {
{ EVM_INS_MSIZE, "msize" },
{ EVM_INS_GAS, "gas" },
{ EVM_INS_JUMPDEST, "jumpdest" },
{ EVM_INS_INVALID, NULL },
{ EVM_INS_INVALID, NULL },
{ EVM_INS_INVALID, NULL },
{ EVM_INS_INVALID, NULL },
{ EVM_INS_TLOAD, "tload" },
{ EVM_INS_TSTORE, "tstore" },
{ EVM_INS_MCOPY, "mcopy" },
{ EVM_INS_PUSH0, "push0" },
{ EVM_INS_PUSH1, "push1" },
{ EVM_INS_PUSH2, "push2" },
{ EVM_INS_PUSH3, "push3" },
@@ -291,7 +292,7 @@ static const name_map insn_name_maps[256] = {
{ EVM_INS_CALLCODE, "callcode" },
{ EVM_INS_RETURN, "return" },
{ EVM_INS_DELEGATECALL, "delegatecall" },
{ EVM_INS_CALLBLACKBOX, "callblackbox" },
{ EVM_INS_CREATE2, "create2" },
{ EVM_INS_INVALID, NULL },
{ EVM_INS_INVALID, NULL },
{ EVM_INS_INVALID, NULL },
@@ -301,7 +302,7 @@ static const name_map insn_name_maps[256] = {
{ EVM_INS_INVALID, NULL },
{ EVM_INS_REVERT, "revert" },
{ EVM_INS_INVALID, NULL },
{ EVM_INS_SUICIDE, "suicide" },
{ EVM_INS_SELFDESTRUCT, "selfdestruct" },
};
#endif

37
external/capstone/arch/EVM/EVMMappingInsn.inc vendored
View File

@@ -1,5 +1,6 @@
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh, 2018 */
/* By Andelf, 2025 */
{ 0, 0, 0 }, // STOP
{ 2, 1, 3 }, // ADD
@@ -28,9 +29,9 @@
{ 2, 1, 3 }, // XOR
{ 1, 1, 3 }, // NOT
{ 2, 1, 3 }, // BYTE
{ 0, 0, 0xffffffff }, // unused
{ 0, 0, 0xffffffff }, // unused
{ 0, 0, 0xffffffff }, // unused
{ 2, 1, 3 }, // SHL
{ 2, 1, 3 }, // SHR
{ 2, 1, 3 }, // SAR
{ 0, 0, 0xffffffff }, // unused
{ 0, 0, 0xffffffff }, // unused
{ 2, 1, 30 }, // SHA3
@@ -71,11 +72,11 @@
{ 0, 1, 2 }, // NUMBER
{ 0, 1, 2 }, // DIFFICULTY
{ 0, 1, 2 }, // GASLIMIT
{ 0, 0, 0xffffffff }, // unused
{ 0, 0, 0xffffffff }, // unused
{ 0, 0, 0xffffffff }, // unused
{ 0, 0, 0xffffffff }, // unused
{ 0, 0, 0xffffffff }, // unused
{ 0, 1, 2 }, // CHAINID
{ 0, 1, 5 }, // SELFBALANCE
{ 0, 1, 2 }, // BASEFEE
{ 0, 1, 3 }, // BLOBHASH
{ 0, 1, 2 }, // BLOBBASEFEE
{ 0, 0, 0xffffffff }, // unused
{ 0, 0, 0xffffffff }, // unused
{ 0, 0, 0xffffffff }, // unused
@@ -93,10 +94,10 @@
{ 0, 1, 2 }, // MSIZE
{ 0, 1, 2 }, // GAS
{ 0, 0, 1 }, // JUMPDEST
{ 0, 0, 0xffffffff }, // unused
{ 0, 0, 0xffffffff }, // unused
{ 0, 0, 0xffffffff }, // unused
{ 0, 0, 0xffffffff }, // unused
{ 1, 1, 100 }, // TLOAD
{ 2, 0, 100 }, // TSTORE
{ 3, 0, 3 }, // MCOPY
{ 0, 1, 3 }, // PUSH0
{ 0, 1, 3 }, // PUSH1
{ 0, 1, 3 }, // PUSH2
{ 0, 1, 3 }, // PUSH3
@@ -242,18 +243,18 @@
{ 0, 0, 0xffffffff }, // unused
{ 0, 0, 0xffffffff }, // unused
{ 3, 1, 32000 }, // CREATE
{ 7, 1, 40 }, // CALL
{ 7, 1, 40 }, // CALLCODE
{ 7, 1, 100 }, // CALL
{ 7, 1, 100 }, // CALLCODE
{ 2, 0, 0 }, // RETURN
{ 6, 1, 40 }, // DELEGATECALL
{ 7, 1, 40 }, // CALLBLACKBOX
{ 6, 1, 100 }, // DELEGATECALL
{ 4, 1, 32000 }, // CREATE2
{ 0, 0, 0xffffffff }, // unused
{ 0, 0, 0xffffffff }, // unused
{ 0, 0, 0xffffffff }, // unused
{ 0, 0, 0xffffffff }, // unused
{ 6, 1, 40 }, // STATICCALL
{ 6, 1, 100 }, // STATICCALL
{ 0, 0, 0xffffffff }, // unused
{ 0, 0, 0xffffffff }, // unused
{ 2, 0, 0 }, // REVERT
{ 0, 0, 0xffffffff }, // unused
{ 1, 0, 0 }, // SUICIDE
{ 1, 0, 5000 }, // SELFDESTRUCT

22
external/capstone/arch/LoongArch/LoongArchGenCSMappingInsnOp.inc vendored
View File

@@ -3383,49 +3383,49 @@
}},
{ /* LOONGARCH_LD_B (690) - LOONGARCH_INS_LD_B - ld.b $rd, $rj, $imm12 */
{
{ CS_OP_REG | CS_OP_MEM, CS_AC_READ, { CS_DATA_TYPE_INVALID_SIMPLE_VALUE_TYPE, CS_DATA_TYPE_LAST } }, /* rd */
{ CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_INVALID_SIMPLE_VALUE_TYPE, CS_DATA_TYPE_LAST } }, /* rd */
{ CS_OP_REG | CS_OP_MEM, CS_AC_READ, { CS_DATA_TYPE_INVALID_SIMPLE_VALUE_TYPE, CS_DATA_TYPE_LAST } }, /* rj */
{ CS_OP_IMM | CS_OP_MEM, CS_AC_READ, { CS_DATA_TYPE_INVALID_SIMPLE_VALUE_TYPE, CS_DATA_TYPE_LAST } }, /* imm12 */
{ 0 }
}},
{ /* LOONGARCH_LD_BU (691) - LOONGARCH_INS_LD_BU - ld.bu $rd, $rj, $imm12 */
{
{ CS_OP_REG | CS_OP_MEM, CS_AC_READ, { CS_DATA_TYPE_INVALID_SIMPLE_VALUE_TYPE, CS_DATA_TYPE_LAST } }, /* rd */
{ CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_INVALID_SIMPLE_VALUE_TYPE, CS_DATA_TYPE_LAST } }, /* rd */
{ CS_OP_REG | CS_OP_MEM, CS_AC_READ, { CS_DATA_TYPE_INVALID_SIMPLE_VALUE_TYPE, CS_DATA_TYPE_LAST } }, /* rj */
{ CS_OP_IMM | CS_OP_MEM, CS_AC_READ, { CS_DATA_TYPE_INVALID_SIMPLE_VALUE_TYPE, CS_DATA_TYPE_LAST } }, /* imm12 */
{ 0 }
}},
{ /* LOONGARCH_LD_D (692) - LOONGARCH_INS_LD_D - ld.d $rd, $rj, $imm12 */
{
{ CS_OP_REG | CS_OP_MEM, CS_AC_READ, { CS_DATA_TYPE_INVALID_SIMPLE_VALUE_TYPE, CS_DATA_TYPE_LAST } }, /* rd */
{ CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_INVALID_SIMPLE_VALUE_TYPE, CS_DATA_TYPE_LAST } }, /* rd */
{ CS_OP_REG | CS_OP_MEM, CS_AC_READ, { CS_DATA_TYPE_INVALID_SIMPLE_VALUE_TYPE, CS_DATA_TYPE_LAST } }, /* rj */
{ CS_OP_IMM | CS_OP_MEM, CS_AC_READ, { CS_DATA_TYPE_INVALID_SIMPLE_VALUE_TYPE, CS_DATA_TYPE_LAST } }, /* imm12 */
{ 0 }
}},
{ /* LOONGARCH_LD_H (693) - LOONGARCH_INS_LD_H - ld.h $rd, $rj, $imm12 */
{
{ CS_OP_REG | CS_OP_MEM, CS_AC_READ, { CS_DATA_TYPE_INVALID_SIMPLE_VALUE_TYPE, CS_DATA_TYPE_LAST } }, /* rd */
{ CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_INVALID_SIMPLE_VALUE_TYPE, CS_DATA_TYPE_LAST } }, /* rd */
{ CS_OP_REG | CS_OP_MEM, CS_AC_READ, { CS_DATA_TYPE_INVALID_SIMPLE_VALUE_TYPE, CS_DATA_TYPE_LAST } }, /* rj */
{ CS_OP_IMM | CS_OP_MEM, CS_AC_READ, { CS_DATA_TYPE_INVALID_SIMPLE_VALUE_TYPE, CS_DATA_TYPE_LAST } }, /* imm12 */
{ 0 }
}},
{ /* LOONGARCH_LD_HU (694) - LOONGARCH_INS_LD_HU - ld.hu $rd, $rj, $imm12 */
{
{ CS_OP_REG | CS_OP_MEM, CS_AC_READ, { CS_DATA_TYPE_INVALID_SIMPLE_VALUE_TYPE, CS_DATA_TYPE_LAST } }, /* rd */
{ CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_INVALID_SIMPLE_VALUE_TYPE, CS_DATA_TYPE_LAST } }, /* rd */
{ CS_OP_REG | CS_OP_MEM, CS_AC_READ, { CS_DATA_TYPE_INVALID_SIMPLE_VALUE_TYPE, CS_DATA_TYPE_LAST } }, /* rj */
{ CS_OP_IMM | CS_OP_MEM, CS_AC_READ, { CS_DATA_TYPE_INVALID_SIMPLE_VALUE_TYPE, CS_DATA_TYPE_LAST } }, /* imm12 */
{ 0 }
}},
{ /* LOONGARCH_LD_W (695) - LOONGARCH_INS_LD_W - ld.w $rd, $rj, $imm12 */
{
{ CS_OP_REG | CS_OP_MEM, CS_AC_READ, { CS_DATA_TYPE_INVALID_SIMPLE_VALUE_TYPE, CS_DATA_TYPE_LAST } }, /* rd */
{ CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_INVALID_SIMPLE_VALUE_TYPE, CS_DATA_TYPE_LAST } }, /* rd */
{ CS_OP_REG | CS_OP_MEM, CS_AC_READ, { CS_DATA_TYPE_INVALID_SIMPLE_VALUE_TYPE, CS_DATA_TYPE_LAST } }, /* rj */
{ CS_OP_IMM | CS_OP_MEM, CS_AC_READ, { CS_DATA_TYPE_INVALID_SIMPLE_VALUE_TYPE, CS_DATA_TYPE_LAST } }, /* imm12 */
{ 0 }
}},
{ /* LOONGARCH_LD_WU (696) - LOONGARCH_INS_LD_WU - ld.wu $rd, $rj, $imm12 */
{
{ CS_OP_REG | CS_OP_MEM, CS_AC_READ, { CS_DATA_TYPE_INVALID_SIMPLE_VALUE_TYPE, CS_DATA_TYPE_LAST } }, /* rd */
{ CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_INVALID_SIMPLE_VALUE_TYPE, CS_DATA_TYPE_LAST } }, /* rd */
{ CS_OP_REG | CS_OP_MEM, CS_AC_READ, { CS_DATA_TYPE_INVALID_SIMPLE_VALUE_TYPE, CS_DATA_TYPE_LAST } }, /* rj */
{ CS_OP_IMM | CS_OP_MEM, CS_AC_READ, { CS_DATA_TYPE_INVALID_SIMPLE_VALUE_TYPE, CS_DATA_TYPE_LAST } }, /* imm12 */
{ 0 }
@@ -4233,28 +4233,28 @@
}},
{ /* LOONGARCH_ST_B (818) - LOONGARCH_INS_ST_B - st.b $rd, $rj, $imm12 */
{
{ CS_OP_REG | CS_OP_MEM, CS_AC_WRITE, { CS_DATA_TYPE_INVALID_SIMPLE_VALUE_TYPE, CS_DATA_TYPE_LAST } }, /* rd */
{ CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_INVALID_SIMPLE_VALUE_TYPE, CS_DATA_TYPE_LAST } }, /* rd */
{ CS_OP_REG | CS_OP_MEM, CS_AC_WRITE, { CS_DATA_TYPE_INVALID_SIMPLE_VALUE_TYPE, CS_DATA_TYPE_LAST } }, /* rj */
{ CS_OP_IMM | CS_OP_MEM, CS_AC_WRITE, { CS_DATA_TYPE_INVALID_SIMPLE_VALUE_TYPE, CS_DATA_TYPE_LAST } }, /* imm12 */
{ 0 }
}},
{ /* LOONGARCH_ST_D (819) - LOONGARCH_INS_ST_D - st.d $rd, $rj, $imm12 */
{
{ CS_OP_REG | CS_OP_MEM, CS_AC_WRITE, { CS_DATA_TYPE_INVALID_SIMPLE_VALUE_TYPE, CS_DATA_TYPE_LAST } }, /* rd */
{ CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_INVALID_SIMPLE_VALUE_TYPE, CS_DATA_TYPE_LAST } }, /* rd */
{ CS_OP_REG | CS_OP_MEM, CS_AC_WRITE, { CS_DATA_TYPE_INVALID_SIMPLE_VALUE_TYPE, CS_DATA_TYPE_LAST } }, /* rj */
{ CS_OP_IMM | CS_OP_MEM, CS_AC_WRITE, { CS_DATA_TYPE_INVALID_SIMPLE_VALUE_TYPE, CS_DATA_TYPE_LAST } }, /* imm12 */
{ 0 }
}},
{ /* LOONGARCH_ST_H (820) - LOONGARCH_INS_ST_H - st.h $rd, $rj, $imm12 */
{
{ CS_OP_REG | CS_OP_MEM, CS_AC_WRITE, { CS_DATA_TYPE_INVALID_SIMPLE_VALUE_TYPE, CS_DATA_TYPE_LAST } }, /* rd */
{ CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_INVALID_SIMPLE_VALUE_TYPE, CS_DATA_TYPE_LAST } }, /* rd */
{ CS_OP_REG | CS_OP_MEM, CS_AC_WRITE, { CS_DATA_TYPE_INVALID_SIMPLE_VALUE_TYPE, CS_DATA_TYPE_LAST } }, /* rj */
{ CS_OP_IMM | CS_OP_MEM, CS_AC_WRITE, { CS_DATA_TYPE_INVALID_SIMPLE_VALUE_TYPE, CS_DATA_TYPE_LAST } }, /* imm12 */
{ 0 }
}},
{ /* LOONGARCH_ST_W (821) - LOONGARCH_INS_ST_W - st.w $rd, $rj, $imm12 */
{
{ CS_OP_REG | CS_OP_MEM, CS_AC_WRITE, { CS_DATA_TYPE_INVALID_SIMPLE_VALUE_TYPE, CS_DATA_TYPE_LAST } }, /* rd */
{ CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_INVALID_SIMPLE_VALUE_TYPE, CS_DATA_TYPE_LAST } }, /* rd */
{ CS_OP_REG | CS_OP_MEM, CS_AC_WRITE, { CS_DATA_TYPE_INVALID_SIMPLE_VALUE_TYPE, CS_DATA_TYPE_LAST } }, /* rj */
{ CS_OP_IMM | CS_OP_MEM, CS_AC_WRITE, { CS_DATA_TYPE_INVALID_SIMPLE_VALUE_TYPE, CS_DATA_TYPE_LAST } }, /* imm12 */
{ 0 }

4
external/capstone/arch/LoongArch/LoongArchGenCSOpGroup.inc vendored
View File

@@ -11,5 +11,5 @@
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
LOONGARCH_OP_GROUP_OPERAND = 0,
LOONGARCH_OP_GROUP_ATOMICMEMOP = 1,
LoongArch_OP_GROUP_Operand = 0,
LoongArch_OP_GROUP_AtomicMemOp = 1,

29
external/capstone/arch/LoongArch/LoongArchInstPrinter.c vendored
View File

@@ -91,7 +91,7 @@ static void printRegName(MCInst *MI, SStream *O, MCRegister Reg)
static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
add_cs_detail(MI, LOONGARCH_OP_GROUP_OPERAND, OpNo);
add_cs_detail(MI, LoongArch_OP_GROUP_Operand, OpNo);
MCOperand *MO = MCInst_getOperand(MI, (OpNo));
if (MCOperand_isReg(MO)) {
@@ -100,6 +100,31 @@ static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
}
if (MCOperand_isImm(MO)) {
// rewrite offset immediate operand to absolute address in direct branch instructions
// convert e.g.
// 0x1000: beqz $t0, 0xc
// to:
// 0x1000: beqz $t0, 0x100c
switch (MI->flat_insn->id) {
case LOONGARCH_INS_B:
case LOONGARCH_INS_BCEQZ:
case LOONGARCH_INS_BCNEZ:
case LOONGARCH_INS_BEQ:
case LOONGARCH_INS_BEQZ:
case LOONGARCH_INS_BGE:
case LOONGARCH_INS_BGEU:
case LOONGARCH_INS_BL:
case LOONGARCH_INS_BLT:
case LOONGARCH_INS_BLTU:
case LOONGARCH_INS_BNE:
case LOONGARCH_INS_BNEZ:
printInt64(O, MCOperand_getImm(MO) + MI->address);
return;
default:
break;
}
printInt64(O, MCOperand_getImm(MO));
return;
}
@@ -109,7 +134,7 @@ static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
static void printAtomicMemOp(MCInst *MI, unsigned OpNo, SStream *O)
{
add_cs_detail(MI, LOONGARCH_OP_GROUP_ATOMICMEMOP, OpNo);
add_cs_detail(MI, LoongArch_OP_GROUP_AtomicMemOp, OpNo);
MCOperand *MO = MCInst_getOperand(MI, (OpNo));
printRegName(MI, O, MCOperand_getReg(MO));

61
external/capstone/arch/LoongArch/LoongArchMapping.c vendored
View File

@@ -324,6 +324,49 @@ void LoongArch_rewrite_memory_operand(MCInst *MI)
}
}
void LoongArch_rewrite_address_operand(MCInst *MI)
{
// rewrite offset immediate operand to absolute address in direct branch instructions
// convert e.g.
// 0x1000: beqz $t0, 0x100c
// op_count: 2
// operands[0].type: REG = t0
// operands[0].access: READ
// operands[1].type: IMM = 0xc
// operands[1].access: READ
// to:
// op_count: 2
// operands[0].type: REG = t0
// operands[0].access: READ
// operands[1].type: IMM = 0x100c
// operands[1].access: READ
if (!detail_is_set(MI))
return;
// handle different types of branch instructions
switch (MI->flat_insn->id) {
case LOONGARCH_INS_B:
case LOONGARCH_INS_BCEQZ:
case LOONGARCH_INS_BCNEZ:
case LOONGARCH_INS_BEQ:
case LOONGARCH_INS_BEQZ:
case LOONGARCH_INS_BGE:
case LOONGARCH_INS_BGEU:
case LOONGARCH_INS_BL:
case LOONGARCH_INS_BLT:
case LOONGARCH_INS_BLTU:
case LOONGARCH_INS_BNE:
case LOONGARCH_INS_BNEZ:
// last operand is address operand
LoongArch_get_detail_op(MI, -1)->imm += MI->address;
return;
default:
break;
}
}
void LoongArch_set_instr_map_data(MCInst *MI)
{
map_cs_id(MI, loongarch_insns, ARR_SIZE(loongarch_insns));
@@ -343,12 +386,14 @@ bool LoongArch_getInstruction(csh handle, const uint8_t *code, size_t code_len,
{
uint64_t temp_size;
LoongArch_init_cs_detail(instr);
bool Result = LoongArch_LLVM_getInstruction(instr, &temp_size, code,
code_len, address, info) !=
MCDisassembler_Fail;
DecodeStatus Result = LoongArch_LLVM_getInstruction(instr, &temp_size, code,
code_len, address, info);
LoongArch_set_instr_map_data(instr);
*size = temp_size;
return Result;
if (Result == MCDisassembler_SoftFail) {
MCInst_setSoftFail(instr);
}
return Result != MCDisassembler_Fail;
}
/// Adds group to the instruction which are not defined in LLVM.
@@ -375,6 +420,9 @@ static void LoongArch_add_cs_groups(MCInst *MI)
} else if (loongarch->op_count == 1) {
// jr rj
add_group(MI, LOONGARCH_GRP_JUMP);
} else if (loongarch->op_count == 3) {
// none of the above, generic jirl
add_group(MI, LOONGARCH_GRP_JUMP);
}
break;
case LOONGARCH_INS_B:
@@ -429,6 +477,7 @@ void LoongArch_printer(MCInst *MI, SStream *O,
LoongArch_LLVM_printInst(MI, MI->address, "", O);
LoongArch_rewrite_memory_operand(MI);
LoongArch_rewrite_address_operand(MI);
LoongArch_add_cs_groups(MI);
#ifndef CAPSTONE_DIET
map_set_alias_id(MI, O, insn_alias_mnem_map,
@@ -502,7 +551,7 @@ void LoongArch_add_cs_detail(MCInst *MI, int /* loongarch_op_group */ op_group,
default:
printf("ERROR: Operand group %d not handled!\n", op_group);
CS_ASSERT_RET(0);
case LOONGARCH_OP_GROUP_OPERAND:
case LoongArch_OP_GROUP_Operand:
if (op_type == CS_OP_IMM) {
LoongArch_set_detail_op_imm(MI, OpNum, LOONGARCH_OP_IMM,
MCInst_getOpVal(MI, OpNum));
@@ -512,7 +561,7 @@ void LoongArch_add_cs_detail(MCInst *MI, int /* loongarch_op_group */ op_group,
} else
CS_ASSERT_RET(0 && "Op type not handled.");
break;
case LOONGARCH_OP_GROUP_ATOMICMEMOP:
case LoongArch_OP_GROUP_AtomicMemOp:
CS_ASSERT_RET(op_type == CS_OP_REG);
// converted to MEM operand later in LoongArch_rewrite_memory_operand
LoongArch_set_detail_op_reg(MI, OpNum,

11
external/capstone/arch/M680X/M680XDisassembler.c vendored
View File

@@ -103,12 +103,11 @@ typedef enum e_access_mode {
} e_access_mode;
// Access type values are compatible with enum cs_ac_type:
typedef enum e_access {
UNCHANGED = CS_AC_INVALID,
READ = CS_AC_READ,
WRITE = CS_AC_WRITE,
MODIFY = (CS_AC_READ | CS_AC_WRITE),
} e_access;
typedef cs_ac_type e_access;
#define UNCHANGED CS_AC_INVALID
#define READ CS_AC_READ
#define WRITE CS_AC_WRITE
#define MODIFY CS_AC_READ_WRITE
/* Properties of one instruction in PAGE1 (without prefix) */
typedef struct inst_page1 {

74
external/capstone/arch/Mips/MipsDisassembler.c vendored
View File

@@ -236,8 +236,6 @@ bool Mips_getFeatureBits(unsigned int mode, unsigned int feature)
}
return true;
}
case Mips_FeatureUseIndirectJumpsHazard:
return true;
default:
return false;
}
@@ -1458,7 +1456,9 @@ static DecodeStatus getInstruction(MCInst *Instr, uint64_t *Size, const uint8_t
bool IsMicroMips = Mips_getFeatureBits(mode, Mips_FeatureMicroMips);
bool IsNanoMips = Mips_getFeatureBits(mode, Mips_FeatureNanoMips);
bool IsMips32r6 = Mips_getFeatureBits(mode, Mips_FeatureMips32r6);
bool IsMips64r6 = Mips_getFeatureBits(mode, Mips_FeatureMips64r6);
bool IsMips2 = Mips_getFeatureBits(mode, Mips_FeatureMips2);
bool IsMips16 = Mips_getFeatureBits(mode, Mips_FeatureMips16);
bool IsCnMips = Mips_getFeatureBits(mode, Mips_FeatureCnMips);
bool IsCnMipsP = Mips_getFeatureBits(mode, Mips_FeatureCnMipsP);
bool IsFP64 = Mips_getFeatureBits(mode, Mips_FeatureFP64Bit);
@@ -1507,6 +1507,14 @@ static DecodeStatus getInstruction(MCInst *Instr, uint64_t *Size, const uint8_t
*Size = 2;
return Result;
}
Result = decodeInstruction_2(DecoderTableNanoMips_Conflict_Space16,
Instr, Insn, Address,
NULL);
if (Result != MCDisassembler_Fail) {
*Size = 2;
return Result;
}
}
// This is an invalid instruction. Claim that the Size is 2 bytes. Since
@@ -1550,6 +1558,14 @@ static DecodeStatus getInstruction(MCInst *Instr, uint64_t *Size, const uint8_t
if (IsMips32r6) {
// Calling the auto-generated decoder function.
Result = decodeInstruction_4(DecoderTableMicroMipsR6_Ambiguous32,
Instr, Insn, Address,
NULL);
if (Result != MCDisassembler_Fail) {
*Size = 4;
return Result;
}
Result = decodeInstruction_4(DecoderTableMicroMipsR632,
Instr, Insn, Address,
NULL);
@@ -1567,6 +1583,13 @@ static DecodeStatus getInstruction(MCInst *Instr, uint64_t *Size, const uint8_t
return Result;
}
Result = decodeInstruction_4(DecoderTableMicroMipsDSP32, Instr,
Insn, Address, NULL);
if (Result != MCDisassembler_Fail) {
*Size = 4;
return Result;
}
if (IsFP64) {
Result =
decodeInstruction_4(DecoderTableMicroMipsFP6432,
@@ -1586,6 +1609,28 @@ static DecodeStatus getInstruction(MCInst *Instr, uint64_t *Size, const uint8_t
return MCDisassembler_Fail;
}
if (IsMips16) {
Result = readInstruction32(Bytes, BytesLen, Address, Size,
&Insn, IsBigEndian, IsMicroMips);
if (Result != MCDisassembler_Fail) {
Result = decodeInstruction_4(DecoderTable32, Instr, Insn, Address,
NULL);
if (Result != MCDisassembler_Fail) {
*Size = 4;
return Result;
}
}
Result = readInstruction16(Bytes, BytesLen, Address, Size,
&Insn, IsBigEndian);
if (Result == MCDisassembler_Fail) {
return MCDisassembler_Fail;
}
*Size = 2;
return decodeInstruction_2(DecoderTable16, Instr, Insn, Address, NULL);
}
// Attempt to read the instruction so that we can attempt to decode it. If
// the buffer is not 4 bytes long, let the higher level logic figure out
// what to do with a size of zero and MCDisassembler::Fail.
@@ -1618,11 +1663,21 @@ static DecodeStatus getInstruction(MCInst *Instr, uint64_t *Size, const uint8_t
return Result;
}
if (IsMips32r6) {
if (IsMips32r6 || IsMips64r6) {
Result = decodeInstruction_4(DecoderTableMips32r6_64r6_BranchZero32, Instr,
Insn, Address, NULL);
if (Result != MCDisassembler_Fail)
return Result;
Result = decodeInstruction_4(DecoderTableMips32r6_64r632, Instr,
Insn, Address, NULL);
if (Result != MCDisassembler_Fail)
return Result;
Result = decodeInstruction_4(DecoderTableMips32r6_64r6_Ambiguous32, Instr,
Insn, Address, NULL);
if (Result != MCDisassembler_Fail)
return Result;
}
if (IsMips2 && IsPTR64) {
@@ -1660,6 +1715,11 @@ static DecodeStatus getInstruction(MCInst *Instr, uint64_t *Size, const uint8_t
return Result;
}
Result = decodeInstruction_4(DecoderTableMipsDSP32, Instr, Insn,
Address, NULL);
if (Result != MCDisassembler_Fail)
return Result;
// Calling the auto-generated decoder function.
Result = decodeInstruction_4(DecoderTableMips32, Instr, Insn, Address,
NULL);
@@ -1673,7 +1733,15 @@ static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address,
const void *Decoder)
{
if (RegNo > 7)
return MCDisassembler_Fail;
if (RegNo < 2)
RegNo += 16;
unsigned Reg = getReg(Inst, Mips_GPR32RegClassID, RegNo);
MCOperand_CreateReg0(Inst, (Reg));
return MCDisassembler_Success;
}
static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, unsigned RegNo,

4
external/capstone/arch/Mips/MipsGenDisassemblerTables.inc vendored
View File

@@ -101,7 +101,7 @@ static const uint8_t DecoderTable16[] = {
/* 299 */ MCD_OPC_CheckPredicate, 0, 57, 1, 0, // Skip to: 617
/* 304 */ MCD_OPC_CheckField, 8, 3, 0, 50, 1, 0, // Skip to: 617
/* 311 */ MCD_OPC_Decode, 150, 15, 10, // Opcode: JrcRx16
/* 315 */ MCD_OPC_FilterValue, 7, 41, 1, 0, // Skip to: 617
/* 315 */ MCD_OPC_FilterValue, 5, 41, 1, 0, // Skip to: 617
/* 320 */ MCD_OPC_CheckPredicate, 0, 36, 1, 0, // Skip to: 617
/* 325 */ MCD_OPC_CheckField, 8, 3, 0, 29, 1, 0, // Skip to: 617
/* 332 */ MCD_OPC_Decode, 149, 15, 10, // Opcode: JrcRa16
@@ -190,7 +190,7 @@ static const uint8_t DecoderTable32[] = {
/* 97 */ MCD_OPC_CheckField, 27, 5, 30, 167, 1, 0, // Skip to: 527
/* 104 */ MCD_OPC_CheckField, 5, 3, 0, 160, 1, 0, // Skip to: 527
/* 111 */ MCD_OPC_Decode, 240, 8, 16, // Opcode: BnezRxImmX16
/* 115 */ MCD_OPC_FilterValue, 6, 106, 0, 0, // Skip to: 226
/* 115 */ MCD_OPC_FilterValue, 12, 106, 0, 0, // Skip to: 226
/* 120 */ MCD_OPC_ExtractField, 27, 5, // Inst{31-27} ...
/* 123 */ MCD_OPC_FilterValue, 30, 143, 1, 0, // Skip to: 527
/* 128 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ...

107
external/capstone/arch/Mips/MipsInstPrinter.c vendored
View File

@@ -121,6 +121,110 @@ static void printRegName(MCInst *MI, SStream *OS, MCRegister Reg)
SStream_concat0(OS, Mips_LLVM_getRegisterName(Reg, syntax_opt & CS_OPT_SYNTAX_NOREGNAME));
}
static void patch_cs_printer(MCInst *MI, SStream *O) {
// replace '# 16 bit inst' to empty.
SStream_replc(O, '#', 0);
SStream_trimls(O);
if (MI->csh->syntax & CS_OPT_SYNTAX_NO_DOLLAR) {
char *dollar = strchr(O->buffer, '$');
if (!dollar) {
return;
}
size_t dollar_len = strlen(dollar + 1);
// to include `\0`
memmove(dollar, dollar + 1, dollar_len + 1);
}
}
static void patch_cs_detail_operand_reg(cs_mips_op *op, unsigned reg, unsigned access) {
op->type = MIPS_OP_REG;
op->reg = reg;
op->is_reglist = false;
op->access = access;
}
static void patch_cs_details(MCInst *MI) {
if (!detail_is_set(MI))
return;
cs_mips_op *op0 = NULL, *op1 = NULL, *op2 = NULL;
unsigned opcode = MCInst_getOpcode(MI);
unsigned n_ops = MCInst_getNumOperands(MI);
switch(opcode) {
/* mips r2 to r5 only 64bit */
case Mips_DSDIV: /// ddiv $$zero, $rs, $rt
/* fall-thru */
case Mips_DUDIV: /// ddivu $$zero, $rs, $rt
if (n_ops != 2) {
return;
}
Mips_inc_op_count(MI);
op0 = Mips_get_detail_op(MI, -3);
op1 = Mips_get_detail_op(MI, -2);
op2 = Mips_get_detail_op(MI, -1);
// move all details by one and add $zero reg
*op2 = *op1;
*op1 = *op0;
patch_cs_detail_operand_reg(op0, MIPS_REG_ZERO_64, CS_AC_WRITE);
return;
/* mips r2 to r5 only */
case Mips_SDIV: /// div $$zero, $rs, $rt
/* fall-thru */
case Mips_UDIV: /// divu $$zero, $rs, $rt
/* fall-thru */
/* microMIPS only */
case Mips_SDIV_MM: /// div $$zero, $rs, $rt
/* fall-thru */
case Mips_UDIV_MM: /// divu $$zero, $rs, $rt
/* fall-thru */
/* MIPS16 only */
case Mips_DivRxRy16: /// div $$zero, $rx, $ry
/* fall-thru */
case Mips_DivuRxRy16: /// divu $$zero, $rx, $ry
if (n_ops != 2) {
return;
}
Mips_inc_op_count(MI);
op0 = Mips_get_detail_op(MI, -3);
op1 = Mips_get_detail_op(MI, -2);
op2 = Mips_get_detail_op(MI, -1);
// move all details by one and add $zero reg
*op2 = *op1;
*op1 = *op0;
patch_cs_detail_operand_reg(op0, MIPS_REG_ZERO, CS_AC_WRITE);
return;
case Mips_AddiuSpImm16: /// addiu $$sp, imm8
/* fall-thru */
case Mips_AddiuSpImmX16: /// addiu $$sp, imm8
if (n_ops != 1) {
return;
}
Mips_inc_op_count(MI);
op0 = Mips_get_detail_op(MI, -2);
op1 = Mips_get_detail_op(MI, -1);
// move all details by one and add $sp reg
*op1 = *op0;
patch_cs_detail_operand_reg(op0, MIPS_REG_SP, CS_AC_READ_WRITE);
return;
case Mips_JrcRa16: /// jrc $ra
/* fall-thru */
case Mips_JrRa16: /// jr $ra
if (n_ops > 0) {
return;
}
Mips_inc_op_count(MI);
op0 = Mips_get_detail_op(MI, -1);
patch_cs_detail_operand_reg(op0, MIPS_REG_RA, CS_AC_READ);
return;
default:
return;
}
}
void Mips_LLVM_printInst(MCInst *MI, uint64_t Address, SStream *O) {
bool useAliasDetails = map_use_alias_details(MI);
if (!useAliasDetails) {
@@ -137,6 +241,9 @@ void Mips_LLVM_printInst(MCInst *MI, uint64_t Address, SStream *O) {
printInstruction(MI, Address, O);
}
patch_cs_printer(MI, O);
patch_cs_details(MI);
if (!useAliasDetails) {
map_set_fill_detail_ops(MI, true);
}

37
external/capstone/arch/Mips/MipsMapping.c vendored
View File

@@ -51,9 +51,29 @@ static const char *const insn_name_maps[] = {
#include "MipsGenCSMappingInsnName.inc"
};
#ifndef CAPSTONE_DIET
static const name_map insn_alias_mnem_map[] = {
#include "MipsGenCSAliasMnemMap.inc"
// The followings aliases are not generated by LLVM table gen.
{ MIPS_INS_ALIAS_B, "b" }, // beq
{ MIPS_INS_ALIAS_BEQZ, "beqz" }, // beq
{ MIPS_INS_ALIAS_BNEZ, "bnez" }, // bne
{ MIPS_INS_ALIAS_LI, "li" }, // addiu
{ MIPS_INS_ALIAS_END, NULL },
};
#endif
const char *Mips_insn_name(csh handle, unsigned int id)
{
#ifndef CAPSTONE_DIET
if (id < MIPS_INS_ALIAS_END && id > MIPS_INS_ALIAS_BEGIN) {
if (id - MIPS_INS_ALIAS_BEGIN >= ARR_SIZE(insn_alias_mnem_map))
return NULL;
return insn_alias_mnem_map[id - MIPS_INS_ALIAS_BEGIN - 1].name;
}
if (id >= MIPS_INS_ENDING)
return NULL;
if (id < ARR_SIZE(insn_name_maps))
return insn_name_maps[id];
// not found
@@ -177,14 +197,17 @@ bool Mips_getInstruction(csh handle, const uint8_t *code, size_t code_len,
instr->MRI = (MCRegisterInfo *)info;
map_set_fill_detail_ops(instr, true);
bool result = Mips_LLVM_getInstruction(instr, &size64, code, code_len,
DecodeStatus Result = Mips_LLVM_getInstruction(instr, &size64, code, code_len,
address,
info) != MCDisassembler_Fail;
if (result) {
info);
*size = size64;
if (Result != MCDisassembler_Fail) {
Mips_set_instr_map_data(instr);
}
*size = size64;
return result;
if (Result == MCDisassembler_SoftFail) {
MCInst_setSoftFail(instr);
}
return Result != MCDisassembler_Fail;
}
void Mips_printer(MCInst *MI, SStream *O, void * /* MCRegisterInfo* */ info)
@@ -193,6 +216,10 @@ void Mips_printer(MCInst *MI, SStream *O, void * /* MCRegisterInfo* */ info)
MI->MRI = MRI;
Mips_LLVM_printInst(MI, MI->address, O);
#ifndef CAPSTONE_DIET
map_set_alias_id(MI, O, insn_alias_mnem_map,
ARR_SIZE(insn_alias_mnem_map));
#endif
}
static void Mips_setup_op(cs_mips_op *op)

6
external/capstone/arch/RISCV/RISCVDisassembler.c vendored
View File

@@ -421,11 +421,15 @@ bool RISCV_getInstruction(csh ud, const uint8_t *code, size_t code_len,
{
cs_struct *handle = (cs_struct *)(uintptr_t)ud;
return MCDisassembler_Success ==
DecodeStatus Result =
RISCVDisassembler_getInstruction(handle->mode, instr,
code, code_len,
size, address,
(MCRegisterInfo *)info);
if (Result == MCDisassembler_SoftFail) {
MCInst_setSoftFail(instr);
}
return Result != MCDisassembler_Fail;
}

63
external/capstone/arch/Sparc/Sparc.h vendored
View File

@@ -1,63 +0,0 @@
//===-- Sparc.h - Top-level interface for Sparc representation --*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file contains the entry points for global functions defined in the LLVM
// Sparc back-end.
//
//===----------------------------------------------------------------------===//
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
#ifndef CS_SPARC_TARGET_SPARC_H
#define CS_SPARC_TARGET_SPARC_H
#include "capstone/sparc.h"
inline static const char *SPARCCondCodeToString(sparc_cc CC)
{
switch (CC) {
default: return NULL; // unreachable
case SPARC_CC_ICC_A: return "a";
case SPARC_CC_ICC_N: return "n";
case SPARC_CC_ICC_NE: return "ne";
case SPARC_CC_ICC_E: return "e";
case SPARC_CC_ICC_G: return "g";
case SPARC_CC_ICC_LE: return "le";
case SPARC_CC_ICC_GE: return "ge";
case SPARC_CC_ICC_L: return "l";
case SPARC_CC_ICC_GU: return "gu";
case SPARC_CC_ICC_LEU: return "leu";
case SPARC_CC_ICC_CC: return "cc";
case SPARC_CC_ICC_CS: return "cs";
case SPARC_CC_ICC_POS: return "pos";
case SPARC_CC_ICC_NEG: return "neg";
case SPARC_CC_ICC_VC: return "vc";
case SPARC_CC_ICC_VS: return "vs";
case SPARC_CC_FCC_A: return "a";
case SPARC_CC_FCC_N: return "n";
case SPARC_CC_FCC_U: return "u";
case SPARC_CC_FCC_G: return "g";
case SPARC_CC_FCC_UG: return "ug";
case SPARC_CC_FCC_L: return "l";
case SPARC_CC_FCC_UL: return "ul";
case SPARC_CC_FCC_LG: return "lg";
case SPARC_CC_FCC_NE: return "ne";
case SPARC_CC_FCC_E: return "e";
case SPARC_CC_FCC_UE: return "ue";
case SPARC_CC_FCC_GE: return "ge";
case SPARC_CC_FCC_UGE: return "uge";
case SPARC_CC_FCC_LE: return "le";
case SPARC_CC_FCC_ULE: return "ule";
case SPARC_CC_FCC_O: return "o";
}
}
#endif

644
external/capstone/arch/Sparc/SparcDisassembler.c vendored
View File

@@ -1,500 +1,342 @@
//===------ SparcDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===//
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2023 */
/* Automatically translated source file from LLVM. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Only small edits allowed. */
/* For multiple similar edits, please create a Patch for the translator. */
/* Capstone's C++ file translator: */
/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
//===- SparcDisassembler.cpp - Disassembler for Sparc -----------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//===----------------------------------------------------------------------===//
//
// This file is part of the Sparc Disassembler.
//
//===----------------------------------------------------------------------===//
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
#ifdef CAPSTONE_HAS_SPARC
#include <stdio.h> // DEBUG
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <capstone/platform.h>
#include "../../cs_priv.h"
#include "../../utils.h"
#include "SparcDisassembler.h"
#include "../../MCInst.h"
#include "../../MCInstrDesc.h"
#include "../../MCFixedLenDisassembler.h"
#include "../../MCRegisterInfo.h"
#include "../../MCDisassembler.h"
#include "../../MathExtras.h"
#include "../../MCFixedLenDisassembler.h"
#include "SparcDisassemblerExtension.h"
#include "SparcLinkage.h"
#include "SparcMapping.h"
#include "SparcMCTargetDesc.h"
#define CONCAT(a, b) CONCAT_(a, b)
#define CONCAT_(a, b) a##_##b
#define DEBUG_TYPE "sparc-disassembler"
#define GET_REGINFO_MC_DESC
#define GET_REGINFO_ENUM
#include "SparcGenRegisterInfo.inc"
static const unsigned IntRegDecoderTable[] = {
SP_G0, SP_G1, SP_G2, SP_G3,
SP_G4, SP_G5, SP_G6, SP_G7,
SP_O0, SP_O1, SP_O2, SP_O3,
SP_O4, SP_O5, SP_O6, SP_O7,
SP_L0, SP_L1, SP_L2, SP_L3,
SP_L4, SP_L5, SP_L6, SP_L7,
SP_I0, SP_I1, SP_I2, SP_I3,
SP_I4, SP_I5, SP_I6, SP_I7
Sparc_G0, Sparc_G1, Sparc_G2, Sparc_G3, Sparc_G4, Sparc_G5, Sparc_G6, Sparc_G7,
Sparc_O0, Sparc_O1, Sparc_O2, Sparc_O3, Sparc_O4, Sparc_O5, Sparc_O6, Sparc_O7,
Sparc_L0, Sparc_L1, Sparc_L2, Sparc_L3, Sparc_L4, Sparc_L5, Sparc_L6, Sparc_L7,
Sparc_I0, Sparc_I1, Sparc_I2, Sparc_I3, Sparc_I4, Sparc_I5, Sparc_I6, Sparc_I7
};
static const unsigned FPRegDecoderTable[] = {
SP_F0, SP_F1, SP_F2, SP_F3,
SP_F4, SP_F5, SP_F6, SP_F7,
SP_F8, SP_F9, SP_F10, SP_F11,
SP_F12, SP_F13, SP_F14, SP_F15,
SP_F16, SP_F17, SP_F18, SP_F19,
SP_F20, SP_F21, SP_F22, SP_F23,
SP_F24, SP_F25, SP_F26, SP_F27,
SP_F28, SP_F29, SP_F30, SP_F31
Sparc_F0, Sparc_F1, Sparc_F2, Sparc_F3, Sparc_F4, Sparc_F5, Sparc_F6, Sparc_F7,
Sparc_F8, Sparc_F9, Sparc_F10, Sparc_F11, Sparc_F12, Sparc_F13, Sparc_F14, Sparc_F15,
Sparc_F16, Sparc_F17, Sparc_F18, Sparc_F19, Sparc_F20, Sparc_F21, Sparc_F22, Sparc_F23,
Sparc_F24, Sparc_F25, Sparc_F26, Sparc_F27, Sparc_F28, Sparc_F29, Sparc_F30, Sparc_F31
};
static const unsigned DFPRegDecoderTable[] = {
SP_D0, SP_D16, SP_D1, SP_D17,
SP_D2, SP_D18, SP_D3, SP_D19,
SP_D4, SP_D20, SP_D5, SP_D21,
SP_D6, SP_D22, SP_D7, SP_D23,
SP_D8, SP_D24, SP_D9, SP_D25,
SP_D10, SP_D26, SP_D11, SP_D27,
SP_D12, SP_D28, SP_D13, SP_D29,
SP_D14, SP_D30, SP_D15, SP_D31
Sparc_D0, Sparc_D16, Sparc_D1, Sparc_D17, Sparc_D2, Sparc_D18, Sparc_D3, Sparc_D19,
Sparc_D4, Sparc_D20, Sparc_D5, Sparc_D21, Sparc_D6, Sparc_D22, Sparc_D7, Sparc_D23,
Sparc_D8, Sparc_D24, Sparc_D9, Sparc_D25, Sparc_D10, Sparc_D26, Sparc_D11, Sparc_D27,
Sparc_D12, Sparc_D28, Sparc_D13, Sparc_D29, Sparc_D14, Sparc_D30, Sparc_D15, Sparc_D31
};
static const unsigned QFPRegDecoderTable[] = {
SP_Q0, SP_Q8, ~0U, ~0U,
SP_Q1, SP_Q9, ~0U, ~0U,
SP_Q2, SP_Q10, ~0U, ~0U,
SP_Q3, SP_Q11, ~0U, ~0U,
SP_Q4, SP_Q12, ~0U, ~0U,
SP_Q5, SP_Q13, ~0U, ~0U,
SP_Q6, SP_Q14, ~0U, ~0U,
SP_Q7, SP_Q15, ~0U, ~0U
Sparc_Q0, Sparc_Q8, ~0U, ~0U, Sparc_Q1, Sparc_Q9, ~0U, ~0U,
Sparc_Q2, Sparc_Q10, ~0U, ~0U, Sparc_Q3, Sparc_Q11, ~0U, ~0U,
Sparc_Q4, Sparc_Q12, ~0U, ~0U, Sparc_Q5, Sparc_Q13, ~0U, ~0U,
Sparc_Q6, Sparc_Q14, ~0U, ~0U, Sparc_Q7, Sparc_Q15, ~0U, ~0U
};
static const unsigned FCCRegDecoderTable[] = {
SP_FCC0, SP_FCC1, SP_FCC2, SP_FCC3
static const unsigned FCCRegDecoderTable[] = { Sparc_FCC0, Sparc_FCC1, Sparc_FCC2,
Sparc_FCC3 };
static const unsigned ASRRegDecoderTable[] = {
Sparc_Y, Sparc_ASR1, Sparc_ASR2, Sparc_ASR3, Sparc_ASR4, Sparc_ASR5, Sparc_ASR6,
Sparc_ASR7, Sparc_ASR8, Sparc_ASR9, Sparc_ASR10, Sparc_ASR11, Sparc_ASR12, Sparc_ASR13,
Sparc_ASR14, Sparc_ASR15, Sparc_ASR16, Sparc_ASR17, Sparc_ASR18, Sparc_ASR19, Sparc_ASR20,
Sparc_ASR21, Sparc_ASR22, Sparc_ASR23, Sparc_ASR24, Sparc_ASR25, Sparc_ASR26, Sparc_ASR27,
Sparc_ASR28, Sparc_ASR29, Sparc_ASR30, Sparc_ASR31
};
static uint64_t getFeatureBits(int mode)
static const unsigned PRRegDecoderTable[] = {
Sparc_TPC, Sparc_TNPC, Sparc_TSTATE, Sparc_TT, Sparc_TICK,
Sparc_TBA, Sparc_PSTATE, Sparc_TL, Sparc_PIL, Sparc_CWP,
Sparc_CANSAVE, Sparc_CANRESTORE, Sparc_CLEANWIN, Sparc_OTHERWIN, Sparc_WSTATE
};
static const uint16_t IntPairDecoderTable[] = {
Sparc_G0_G1, Sparc_G2_G3, Sparc_G4_G5, Sparc_G6_G7, Sparc_O0_O1, Sparc_O2_O3,
Sparc_O4_O5, Sparc_O6_O7, Sparc_L0_L1, Sparc_L2_L3, Sparc_L4_L5, Sparc_L6_L7,
Sparc_I0_I1, Sparc_I2_I3, Sparc_I4_I5, Sparc_I6_I7,
};
static const unsigned CPRegDecoderTable[] = {
Sparc_C0, Sparc_C1, Sparc_C2, Sparc_C3, Sparc_C4, Sparc_C5, Sparc_C6, Sparc_C7,
Sparc_C8, Sparc_C9, Sparc_C10, Sparc_C11, Sparc_C12, Sparc_C13, Sparc_C14, Sparc_C15,
Sparc_C16, Sparc_C17, Sparc_C18, Sparc_C19, Sparc_C20, Sparc_C21, Sparc_C22, Sparc_C23,
Sparc_C24, Sparc_C25, Sparc_C26, Sparc_C27, Sparc_C28, Sparc_C29, Sparc_C30, Sparc_C31
};
static const uint16_t CPPairDecoderTable[] = {
Sparc_C0_C1, Sparc_C2_C3, Sparc_C4_C5, Sparc_C6_C7, Sparc_C8_C9, Sparc_C10_C11,
Sparc_C12_C13, Sparc_C14_C15, Sparc_C16_C17, Sparc_C18_C19, Sparc_C20_C21, Sparc_C22_C23,
Sparc_C24_C25, Sparc_C26_C27, Sparc_C28_C29, Sparc_C30_C31
};
static DecodeStatus DecodeDisp19(MCInst *Inst, uint32_t ImmVal,
uint64_t Address,
const void *Decoder)
{
// support everything
return (uint64_t)-1;
int64_t BranchTarget = Address + (SignExtend64(ImmVal, 19) * 4);
MCOperand_CreateImm0(Inst, BranchTarget);
return MCDisassembler_Success;
}
static DecodeStatus DecodeDisp16(MCInst *Inst, uint32_t ImmVal,
uint64_t Address,
const void *Decoder)
{
int64_t BranchTarget = Address + (SignExtend64(ImmVal, 16) * 4);
MCOperand_CreateImm0(Inst, BranchTarget);
return MCDisassembler_Success;
}
static DecodeStatus DecodeDisp22(MCInst *Inst, uint32_t ImmVal,
uint64_t Address,
const void *Decoder)
{
int64_t BranchTarget = Address + (SignExtend64(ImmVal, 22) * 4);
MCOperand_CreateImm0(Inst, BranchTarget);
return MCDisassembler_Success;
}
static DecodeStatus DecodeIntRegsRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address, const void *Decoder)
uint64_t Address,
const void *Decoder)
{
unsigned Reg;
if (RegNo > 31)
return MCDisassembler_Fail;
Reg = IntRegDecoderTable[RegNo];
MCOperand_CreateReg0(Inst, Reg);
unsigned Reg = IntRegDecoderTable[RegNo];
MCOperand_CreateReg0(Inst, (Reg));
return MCDisassembler_Success;
}
static DecodeStatus DecodeI64RegsRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address, const void *Decoder)
uint64_t Address,
const void *Decoder)
{
unsigned Reg;
return DecodeIntRegsRegisterClass(Inst, RegNo, Address, Decoder);
}
if (RegNo > 31)
return MCDisassembler_Fail;
Reg = IntRegDecoderTable[RegNo];
MCOperand_CreateReg0(Inst, Reg);
return MCDisassembler_Success;
// This is used for the type "ptr_rc", which is either IntRegs or I64Regs
// depending on SparcRegisterInfo::getPointerRegClass.
static DecodeStatus DecodePointerLikeRegClass0(MCInst *Inst, unsigned RegNo,
uint64_t Address,
const void *Decoder)
{
return DecodeIntRegsRegisterClass(Inst, RegNo, Address, Decoder);
}
static DecodeStatus DecodeFPRegsRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address, const void *Decoder)
uint64_t Address,
const void *Decoder)
{
unsigned Reg;
if (RegNo > 31)
return MCDisassembler_Fail;
Reg = FPRegDecoderTable[RegNo];
MCOperand_CreateReg0(Inst, Reg);
unsigned Reg = FPRegDecoderTable[RegNo];
MCOperand_CreateReg0(Inst, (Reg));
return MCDisassembler_Success;
}
static DecodeStatus DecodeDFPRegsRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address, const void *Decoder)
uint64_t Address,
const void *Decoder)
{
unsigned Reg;
if (RegNo > 31)
return MCDisassembler_Fail;
Reg = DFPRegDecoderTable[RegNo];
MCOperand_CreateReg0(Inst, Reg);
unsigned Reg = DFPRegDecoderTable[RegNo];
MCOperand_CreateReg0(Inst, (Reg));
return MCDisassembler_Success;
}
static DecodeStatus DecodeQFPRegsRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address, const void *Decoder)
uint64_t Address,
const void *Decoder)
{
unsigned Reg;
if (RegNo > 31)
return MCDisassembler_Fail;
Reg = QFPRegDecoderTable[RegNo];
unsigned Reg = QFPRegDecoderTable[RegNo];
if (Reg == ~0U)
return MCDisassembler_Fail;
MCOperand_CreateReg0(Inst, (Reg));
return MCDisassembler_Success;
}
MCOperand_CreateReg0(Inst, Reg);
static DecodeStatus DecodeCoprocRegsRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address,
const void *Decoder)
{
if (RegNo > 31)
return MCDisassembler_Fail;
unsigned Reg = CPRegDecoderTable[RegNo];
MCOperand_CreateReg0(Inst, (Reg));
return MCDisassembler_Success;
}
static DecodeStatus DecodeFCCRegsRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address, const void *Decoder)
uint64_t Address,
const void *Decoder)
{
if (RegNo > 3)
return MCDisassembler_Fail;
MCOperand_CreateReg0(Inst, FCCRegDecoderTable[RegNo]);
MCOperand_CreateReg0(Inst, (FCCRegDecoderTable[RegNo]));
return MCDisassembler_Success;
}
static DecodeStatus DecodeLoadInt(MCInst *Inst, unsigned insn, uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeLoadFP(MCInst *Inst, unsigned insn, uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeLoadDFP(MCInst *Inst, unsigned insn, uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeLoadQFP(MCInst *Inst, unsigned insn, uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeStoreInt(MCInst *Inst, unsigned insn,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeStoreFP(MCInst *Inst, unsigned insn,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeStoreDFP(MCInst *Inst, unsigned insn,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeStoreQFP(MCInst *Inst, unsigned insn,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeCall(MCInst *Inst, unsigned insn,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeSIMM13(MCInst *Inst, unsigned insn,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeJMPL(MCInst *Inst, unsigned insn, uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeReturn(MCInst *MI, unsigned insn, uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeSWAP(MCInst *Inst, unsigned insn, uint64_t Address,
const void *Decoder);
#define GET_SUBTARGETINFO_ENUM
#include "SparcGenSubtargetInfo.inc"
#include "SparcGenDisassemblerTables.inc"
/// readInstruction - read four bytes and return 32 bit word.
static DecodeStatus readInstruction32(const uint8_t *code, size_t len, uint32_t *Insn)
static DecodeStatus DecodeASRRegsRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address,
const void *Decoder)
{
if (len < 4)
// not enough data
if (RegNo > 31)
return MCDisassembler_Fail;
MCOperand_CreateReg0(Inst, (ASRRegDecoderTable[RegNo]));
return MCDisassembler_Success;
}
static DecodeStatus DecodePRRegsRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address,
const void *Decoder)
{
if (RegNo >= ARR_SIZE(PRRegDecoderTable))
return MCDisassembler_Fail;
MCOperand_CreateReg0(Inst, (PRRegDecoderTable[RegNo]));
return MCDisassembler_Success;
}
static DecodeStatus DecodeIntPairRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address,
const void *Decoder)
{
DecodeStatus S = MCDisassembler_Success;
if (RegNo > 31)
return MCDisassembler_Fail;
// Encoded as a big-endian 32-bit word in the stream.
*Insn = (code[3] << 0) |
(code[2] << 8) |
(code[1] << 16) |
((uint32_t) code[0] << 24);
if ((RegNo & 1))
S = MCDisassembler_SoftFail;
unsigned RegisterPair = IntPairDecoderTable[RegNo / 2];
MCOperand_CreateReg0(Inst, (RegisterPair));
return S;
}
static DecodeStatus DecodeCoprocPairRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address,
const void *Decoder)
{
if (RegNo > 31)
return MCDisassembler_Fail;
unsigned RegisterPair = CPPairDecoderTable[RegNo / 2];
MCOperand_CreateReg0(Inst, (RegisterPair));
return MCDisassembler_Success;
}
bool Sparc_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *MI,
uint16_t *size, uint64_t address, void *info)
{
uint32_t Insn;
DecodeStatus Result;
Result = readInstruction32(code, code_len, &Insn);
if (Result == MCDisassembler_Fail)
return false;
if (MI->flat_insn->detail) {
memset(MI->flat_insn->detail, 0, offsetof(cs_detail, sparc)+sizeof(cs_sparc));
}
Result = decodeInstruction_4(DecoderTableSparc32, MI, Insn, address,
(MCRegisterInfo *)info, 0);
if (Result != MCDisassembler_Fail) {
*size = 4;
return true;
}
return false;
}
typedef DecodeStatus (*DecodeFunc)(MCInst *MI, unsigned insn, uint64_t Address,
static DecodeStatus DecodeCall(MCInst *Inst, unsigned insn, uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeSIMM13(MCInst *Inst, unsigned insn, uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeMem(MCInst *MI, unsigned insn, uint64_t Address,
const void *Decoder,
bool isLoad, DecodeFunc DecodeRD)
#include "SparcGenDisassemblerTables.inc"
static DecodeStatus getInstruction(MCInst *Instr, uint64_t *Size, const uint8_t *Bytes,
size_t BytesLen, uint64_t Address, SStream *CStream)
{
DecodeStatus status;
unsigned rd = fieldFromInstruction_4(insn, 25, 5);
unsigned rs1 = fieldFromInstruction_4(insn, 14, 5);
bool isImm = fieldFromInstruction_4(insn, 13, 1) != 0;
unsigned rs2 = 0;
unsigned simm13 = 0;
if (BytesLen < 4) {
return MCDisassembler_Fail;
}
uint32_t Insn = readBytes32(Instr, Bytes);
if (isImm)
simm13 = SignExtend32(fieldFromInstruction_4(insn, 0, 13), 13);
else
rs2 = fieldFromInstruction_4(insn, 0, 5);
if (isLoad) {
status = DecodeRD(MI, rd, Address, Decoder);
if (status != MCDisassembler_Success)
return status;
DecodeStatus Result = MCDisassembler_Fail;
// Calling the auto-generated decoder function.
if (Sparc_getFeatureBits(Instr->csh->mode, Sparc_FeatureV9)) {
Result = decodeInstruction_4(DecoderTableSparcV932, Instr, Insn,
Address, NULL);
} else {
Result = decodeInstruction_4(DecoderTableSparcV832, Instr, Insn,
Address, NULL);
}
if (Result != MCDisassembler_Fail) {
*Size = 4;
return Result;
}
// Decode rs1.
status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
if (status != MCDisassembler_Success)
return status;
Result = decodeInstruction_4(DecoderTableSparc32, Instr, Insn, Address,
NULL);
// Decode imm|rs2.
if (isImm)
MCOperand_CreateImm0(MI, simm13);
else {
status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
if (status != MCDisassembler_Success)
return status;
if (Result != MCDisassembler_Fail) {
*Size = 4;
return Result;
}
if (!isLoad) {
status = DecodeRD(MI, rd, Address, Decoder);
if (status != MCDisassembler_Success)
return status;
return MCDisassembler_Fail;
}
static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch,
uint64_t Address, uint64_t Offset,
uint64_t Width, MCInst *MI,
const void *Decoder)
{
// Capstone doesn't support symbols.
return false;
}
static DecodeStatus DecodeCall(MCInst *MI, unsigned insn, uint64_t Address,
const void *Decoder)
{
unsigned Offset = fieldFromInstruction_4(insn, 0, 30);
int64_t CallTarget = Address + (SignExtend64(Offset, 30) * 4);
if (!tryAddingSymbolicOperand(CallTarget, false, Address, 0, 30, MI,
Decoder))
MCOperand_CreateImm0(MI, CallTarget);
return MCDisassembler_Success;
}
static DecodeStatus DecodeLoadInt(MCInst *Inst, unsigned insn, uint64_t Address,
static DecodeStatus DecodeSIMM13(MCInst *MI, unsigned insn, uint64_t Address,
const void *Decoder)
{
return DecodeMem(Inst, insn, Address, Decoder, true,
DecodeIntRegsRegisterClass);
}
static DecodeStatus DecodeLoadFP(MCInst *Inst, unsigned insn, uint64_t Address,
const void *Decoder)
{
return DecodeMem(Inst, insn, Address, Decoder, true,
DecodeFPRegsRegisterClass);
}
static DecodeStatus DecodeLoadDFP(MCInst *Inst, unsigned insn, uint64_t Address,
const void *Decoder)
{
return DecodeMem(Inst, insn, Address, Decoder, true,
DecodeDFPRegsRegisterClass);
}
static DecodeStatus DecodeLoadQFP(MCInst *Inst, unsigned insn, uint64_t Address,
const void *Decoder)
{
return DecodeMem(Inst, insn, Address, Decoder, true,
DecodeQFPRegsRegisterClass);
}
static DecodeStatus DecodeStoreInt(MCInst *Inst, unsigned insn,
uint64_t Address, const void *Decoder)
{
return DecodeMem(Inst, insn, Address, Decoder, false,
DecodeIntRegsRegisterClass);
}
static DecodeStatus DecodeStoreFP(MCInst *Inst, unsigned insn, uint64_t Address,
const void *Decoder)
{
return DecodeMem(Inst, insn, Address, Decoder, false,
DecodeFPRegsRegisterClass);
}
static DecodeStatus DecodeStoreDFP(MCInst *Inst, unsigned insn,
uint64_t Address, const void *Decoder)
{
return DecodeMem(Inst, insn, Address, Decoder, false,
DecodeDFPRegsRegisterClass);
}
static DecodeStatus DecodeStoreQFP(MCInst *Inst, unsigned insn,
uint64_t Address, const void *Decoder)
{
return DecodeMem(Inst, insn, Address, Decoder, false,
DecodeQFPRegsRegisterClass);
}
static DecodeStatus DecodeCall(MCInst *MI, unsigned insn,
uint64_t Address, const void *Decoder)
{
unsigned tgt = fieldFromInstruction_4(insn, 0, 30);
tgt <<= 2;
MCOperand_CreateImm0(MI, tgt);
CS_ASSERT(isUIntN(13, insn));
MCOperand_CreateImm0(MI, (SignExtend64((insn), 13)));
return MCDisassembler_Success;
}
static DecodeStatus DecodeSIMM13(MCInst *MI, unsigned insn,
uint64_t Address, const void *Decoder)
{
unsigned tgt = SignExtend32(fieldFromInstruction_4(insn, 0, 13), 13);
MCOperand_CreateImm0(MI, tgt);
return MCDisassembler_Success;
}
static DecodeStatus DecodeJMPL(MCInst *MI, unsigned insn, uint64_t Address,
const void *Decoder)
{
DecodeStatus status;
unsigned rd = fieldFromInstruction_4(insn, 25, 5);
unsigned rs1 = fieldFromInstruction_4(insn, 14, 5);
unsigned isImm = fieldFromInstruction_4(insn, 13, 1);
unsigned rs2 = 0;
unsigned simm13 = 0;
if (isImm)
simm13 = SignExtend32(fieldFromInstruction_4(insn, 0, 13), 13);
else
rs2 = fieldFromInstruction_4(insn, 0, 5);
// Decode RD.
status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder);
if (status != MCDisassembler_Success)
return status;
// Decode RS1.
status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
if (status != MCDisassembler_Success)
return status;
// Decode RS1 | SIMM13.
if (isImm)
MCOperand_CreateImm0(MI, simm13);
else {
status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
if (status != MCDisassembler_Success)
DecodeStatus Sparc_LLVM_getInstruction(csh handle, const uint8_t *Bytes,
size_t ByteLen, MCInst *MI, uint16_t *Size,
uint64_t Address, void *Info) {
uint64_t s = 0;
DecodeStatus status = getInstruction(MI, &s, Bytes, ByteLen, Address, NULL);
*Size = (uint16_t) s;
return status;
}
return MCDisassembler_Success;
}
static DecodeStatus DecodeReturn(MCInst *MI, unsigned insn, uint64_t Address,
const void *Decoder)
{
DecodeStatus status;
unsigned rs1 = fieldFromInstruction_4(insn, 14, 5);
unsigned isImm = fieldFromInstruction_4(insn, 13, 1);
unsigned rs2 = 0;
unsigned simm13 = 0;
if (isImm)
simm13 = SignExtend32(fieldFromInstruction_4(insn, 0, 13), 13);
else
rs2 = fieldFromInstruction_4(insn, 0, 5);
// Decode RS1.
status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
if (status != MCDisassembler_Success)
return status;
// Decode RS2 | SIMM13.
if (isImm)
MCOperand_CreateImm0(MI, simm13);
else {
status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
if (status != MCDisassembler_Success)
return status;
}
return MCDisassembler_Success;
}
static DecodeStatus DecodeSWAP(MCInst *MI, unsigned insn, uint64_t Address,
const void *Decoder)
{
DecodeStatus status;
unsigned rd = fieldFromInstruction_4(insn, 25, 5);
unsigned rs1 = fieldFromInstruction_4(insn, 14, 5);
unsigned isImm = fieldFromInstruction_4(insn, 13, 1);
unsigned rs2 = 0;
unsigned simm13 = 0;
if (isImm)
simm13 = SignExtend32(fieldFromInstruction_4(insn, 0, 13), 13);
else
rs2 = fieldFromInstruction_4(insn, 0, 5);
// Decode RD.
status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder);
if (status != MCDisassembler_Success)
return status;
// Decode RS1.
status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
if (status != MCDisassembler_Success)
return status;
// Decode RS1 | SIMM13.
if (isImm)
MCOperand_CreateImm0(MI, simm13);
else {
status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
if (status != MCDisassembler_Success)
return status;
}
return MCDisassembler_Success;
}
void Sparc_init(MCRegisterInfo *MRI)
{
/*
InitMCRegisterInfo(SparcRegDesc, 119, RA, PC,
SparcMCRegisterClasses, 8,
SparcRegUnitRoots,
86,
SparcRegDiffLists,
SparcRegStrings,
SparcSubRegIdxLists,
7,
SparcSubRegIdxRanges,
SparcRegEncodingTable);
*/
MCRegisterInfo_InitMCRegisterInfo(MRI, SparcRegDesc, 119,
0, 0,
SparcMCRegisterClasses, 8,
0, 0,
SparcRegDiffLists,
0,
SparcSubRegIdxLists, 7,
0);
}
#endif

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external/capstone/arch/Sparc/SparcDisassembler.h vendored
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@@ -1,17 +0,0 @@
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
#ifndef CS_SPARCDISASSEMBLER_H
#define CS_SPARCDISASSEMBLER_H
#include "capstone/capstone.h"
#include "../../MCRegisterInfo.h"
#include "../../MCInst.h"
void Sparc_init(MCRegisterInfo *MRI);
bool Sparc_getInstruction(csh ud, const uint8_t *code, size_t code_len,
MCInst *instr, uint16_t *size, uint64_t address, void *info);
#endif

13
external/capstone/arch/Sparc/SparcDisassemblerExtension.c vendored Normal file
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@@ -0,0 +1,13 @@
/* Capstone Disassembly Engine */
/* By Rot127 <unisono@quyllur.org>, 2025 */
#include "SparcDisassemblerExtension.h"
#include "SparcMCTargetDesc.h"
bool Sparc_getFeatureBits(unsigned int mode, unsigned int feature)
{
if (feature == Sparc_FeatureV9) {
return mode & CS_MODE_V9;
}
return true;
}

11
external/capstone/arch/Sparc/SparcDisassemblerExtension.h vendored Normal file
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@@ -0,0 +1,11 @@
/* Capstone Disassembly Engine */
/* By Rot127 <unisono@quyllur.org>, 2025 */
#ifndef CS_SPARC_DISASSEMBLER_EXTENSION_H
#define CS_SPARC_DISASSEMBLER_EXTENSION_H
#include <capstone/capstone.h>
bool Sparc_getFeatureBits(unsigned int mode, unsigned int feature);
#endif // CS_SPARC_DISASSEMBLER_EXTENSION_H

11578
external/capstone/arch/Sparc/SparcGenAsmWriter.inc vendored
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File diff suppressed because it is too large Load Diff

394
external/capstone/arch/Sparc/SparcGenCSAliasMnemMap.inc vendored Normal file
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@@ -0,0 +1,394 @@
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
{ SPARC_INS_ALIAS_MOVA, "mova" },
{ SPARC_INS_ALIAS_FMOVSA, "fmovsa" },
{ SPARC_INS_ALIAS_FMOVDA, "fmovda" },
{ SPARC_INS_ALIAS_MOVRZ, "movrz" },
{ SPARC_INS_ALIAS_FMOVRSZ, "fmovrsz" },
{ SPARC_INS_ALIAS_FMOVRDZ, "fmovrdz" },
{ SPARC_INS_ALIAS_FMOVRQZ, "fmovrqz" },
{ SPARC_INS_ALIAS_BA, "ba" },
{ SPARC_INS_ALIAS_BA_A, "ba_a" },
{ SPARC_INS_ALIAS_BA_PT, "ba_pt" },
{ SPARC_INS_ALIAS_BA_A_PT, "ba_a_pt" },
{ SPARC_INS_ALIAS_BA_PN, "ba_pn" },
{ SPARC_INS_ALIAS_BA_A_PN, "ba_a_pn" },
{ SPARC_INS_ALIAS_FMOVQA, "fmovqa" },
{ SPARC_INS_ALIAS_TA, "ta" },
{ SPARC_INS_ALIAS_FBA, "fba" },
{ SPARC_INS_ALIAS_FBA_PT, "fba_pt" },
{ SPARC_INS_ALIAS_FBA_A, "fba_a" },
{ SPARC_INS_ALIAS_FBA_A_PT, "fba_a_pt" },
{ SPARC_INS_ALIAS_FBA_PN, "fba_pn" },
{ SPARC_INS_ALIAS_FBA_A_PN, "fba_a_pn" },
{ SPARC_INS_ALIAS_BRZ, "brz" },
{ SPARC_INS_ALIAS_BRZ_PT, "brz_pt" },
{ SPARC_INS_ALIAS_BRZ_PN, "brz_pn" },
{ SPARC_INS_ALIAS_BRZ_A, "brz_a" },
{ SPARC_INS_ALIAS_BRZ_A_PT, "brz_a_pt" },
{ SPARC_INS_ALIAS_BRZ_A_PN, "brz_a_pn" },
{ SPARC_INS_ALIAS_BN, "bn" },
{ SPARC_INS_ALIAS_BN_A, "bn_a" },
{ SPARC_INS_ALIAS_BN_PT, "bn_pt" },
{ SPARC_INS_ALIAS_BN_A_PT, "bn_a_pt" },
{ SPARC_INS_ALIAS_BN_PN, "bn_pn" },
{ SPARC_INS_ALIAS_BN_A_PN, "bn_a_pn" },
{ SPARC_INS_ALIAS_MOVN, "movn" },
{ SPARC_INS_ALIAS_FMOVSN, "fmovsn" },
{ SPARC_INS_ALIAS_FMOVDN, "fmovdn" },
{ SPARC_INS_ALIAS_FMOVQN, "fmovqn" },
{ SPARC_INS_ALIAS_TN, "tn" },
{ SPARC_INS_ALIAS_BNE, "bne" },
{ SPARC_INS_ALIAS_BNE_A, "bne_a" },
{ SPARC_INS_ALIAS_BNE_PT, "bne_pt" },
{ SPARC_INS_ALIAS_BNE_A_PT, "bne_a_pt" },
{ SPARC_INS_ALIAS_BNE_PN, "bne_pn" },
{ SPARC_INS_ALIAS_BNE_A_PN, "bne_a_pn" },
{ SPARC_INS_ALIAS_MOVNE, "movne" },
{ SPARC_INS_ALIAS_FMOVSNE, "fmovsne" },
{ SPARC_INS_ALIAS_FMOVDNE, "fmovdne" },
{ SPARC_INS_ALIAS_FMOVQNE, "fmovqne" },
{ SPARC_INS_ALIAS_TNE, "tne" },
{ SPARC_INS_ALIAS_BE, "be" },
{ SPARC_INS_ALIAS_BE_A, "be_a" },
{ SPARC_INS_ALIAS_BE_PT, "be_pt" },
{ SPARC_INS_ALIAS_BE_A_PT, "be_a_pt" },
{ SPARC_INS_ALIAS_BE_PN, "be_pn" },
{ SPARC_INS_ALIAS_BE_A_PN, "be_a_pn" },
{ SPARC_INS_ALIAS_MOVE, "move" },
{ SPARC_INS_ALIAS_FMOVSE, "fmovse" },
{ SPARC_INS_ALIAS_FMOVDE, "fmovde" },
{ SPARC_INS_ALIAS_FMOVQE, "fmovqe" },
{ SPARC_INS_ALIAS_TE, "te" },
{ SPARC_INS_ALIAS_BG, "bg" },
{ SPARC_INS_ALIAS_BG_A, "bg_a" },
{ SPARC_INS_ALIAS_BG_PT, "bg_pt" },
{ SPARC_INS_ALIAS_BG_A_PT, "bg_a_pt" },
{ SPARC_INS_ALIAS_BG_PN, "bg_pn" },
{ SPARC_INS_ALIAS_BG_A_PN, "bg_a_pn" },
{ SPARC_INS_ALIAS_MOVG, "movg" },
{ SPARC_INS_ALIAS_FMOVSG, "fmovsg" },
{ SPARC_INS_ALIAS_FMOVDG, "fmovdg" },
{ SPARC_INS_ALIAS_FMOVQG, "fmovqg" },
{ SPARC_INS_ALIAS_TG, "tg" },
{ SPARC_INS_ALIAS_BLE, "ble" },
{ SPARC_INS_ALIAS_BLE_A, "ble_a" },
{ SPARC_INS_ALIAS_BLE_PT, "ble_pt" },
{ SPARC_INS_ALIAS_BLE_A_PT, "ble_a_pt" },
{ SPARC_INS_ALIAS_BLE_PN, "ble_pn" },
{ SPARC_INS_ALIAS_BLE_A_PN, "ble_a_pn" },
{ SPARC_INS_ALIAS_MOVLE, "movle" },
{ SPARC_INS_ALIAS_FMOVSLE, "fmovsle" },
{ SPARC_INS_ALIAS_FMOVDLE, "fmovdle" },
{ SPARC_INS_ALIAS_FMOVQLE, "fmovqle" },
{ SPARC_INS_ALIAS_TLE, "tle" },
{ SPARC_INS_ALIAS_BGE, "bge" },
{ SPARC_INS_ALIAS_BGE_A, "bge_a" },
{ SPARC_INS_ALIAS_BGE_PT, "bge_pt" },
{ SPARC_INS_ALIAS_BGE_A_PT, "bge_a_pt" },
{ SPARC_INS_ALIAS_BGE_PN, "bge_pn" },
{ SPARC_INS_ALIAS_BGE_A_PN, "bge_a_pn" },
{ SPARC_INS_ALIAS_MOVGE, "movge" },
{ SPARC_INS_ALIAS_FMOVSGE, "fmovsge" },
{ SPARC_INS_ALIAS_FMOVDGE, "fmovdge" },
{ SPARC_INS_ALIAS_FMOVQGE, "fmovqge" },
{ SPARC_INS_ALIAS_TGE, "tge" },
{ SPARC_INS_ALIAS_BL, "bl" },
{ SPARC_INS_ALIAS_BL_A, "bl_a" },
{ SPARC_INS_ALIAS_BL_PT, "bl_pt" },
{ SPARC_INS_ALIAS_BL_A_PT, "bl_a_pt" },
{ SPARC_INS_ALIAS_BL_PN, "bl_pn" },
{ SPARC_INS_ALIAS_BL_A_PN, "bl_a_pn" },
{ SPARC_INS_ALIAS_MOVL, "movl" },
{ SPARC_INS_ALIAS_FMOVSL, "fmovsl" },
{ SPARC_INS_ALIAS_FMOVDL, "fmovdl" },
{ SPARC_INS_ALIAS_FMOVQL, "fmovql" },
{ SPARC_INS_ALIAS_TL, "tl" },
{ SPARC_INS_ALIAS_BGU, "bgu" },
{ SPARC_INS_ALIAS_BGU_A, "bgu_a" },
{ SPARC_INS_ALIAS_BGU_PT, "bgu_pt" },
{ SPARC_INS_ALIAS_BGU_A_PT, "bgu_a_pt" },
{ SPARC_INS_ALIAS_BGU_PN, "bgu_pn" },
{ SPARC_INS_ALIAS_BGU_A_PN, "bgu_a_pn" },
{ SPARC_INS_ALIAS_MOVGU, "movgu" },
{ SPARC_INS_ALIAS_FMOVSGU, "fmovsgu" },
{ SPARC_INS_ALIAS_FMOVDGU, "fmovdgu" },
{ SPARC_INS_ALIAS_FMOVQGU, "fmovqgu" },
{ SPARC_INS_ALIAS_TGU, "tgu" },
{ SPARC_INS_ALIAS_BLEU, "bleu" },
{ SPARC_INS_ALIAS_BLEU_A, "bleu_a" },
{ SPARC_INS_ALIAS_BLEU_PT, "bleu_pt" },
{ SPARC_INS_ALIAS_BLEU_A_PT, "bleu_a_pt" },
{ SPARC_INS_ALIAS_BLEU_PN, "bleu_pn" },
{ SPARC_INS_ALIAS_BLEU_A_PN, "bleu_a_pn" },
{ SPARC_INS_ALIAS_MOVLEU, "movleu" },
{ SPARC_INS_ALIAS_FMOVSLEU, "fmovsleu" },
{ SPARC_INS_ALIAS_FMOVDLEU, "fmovdleu" },
{ SPARC_INS_ALIAS_FMOVQLEU, "fmovqleu" },
{ SPARC_INS_ALIAS_TLEU, "tleu" },
{ SPARC_INS_ALIAS_BCC, "bcc" },
{ SPARC_INS_ALIAS_BCC_A, "bcc_a" },
{ SPARC_INS_ALIAS_BCC_PT, "bcc_pt" },
{ SPARC_INS_ALIAS_BCC_A_PT, "bcc_a_pt" },
{ SPARC_INS_ALIAS_BCC_PN, "bcc_pn" },
{ SPARC_INS_ALIAS_BCC_A_PN, "bcc_a_pn" },
{ SPARC_INS_ALIAS_MOVCC, "movcc" },
{ SPARC_INS_ALIAS_FMOVSCC, "fmovscc" },
{ SPARC_INS_ALIAS_FMOVDCC, "fmovdcc" },
{ SPARC_INS_ALIAS_FMOVQCC, "fmovqcc" },
{ SPARC_INS_ALIAS_TCC, "tcc" },
{ SPARC_INS_ALIAS_BCS, "bcs" },
{ SPARC_INS_ALIAS_BCS_A, "bcs_a" },
{ SPARC_INS_ALIAS_BCS_PT, "bcs_pt" },
{ SPARC_INS_ALIAS_BCS_A_PT, "bcs_a_pt" },
{ SPARC_INS_ALIAS_BCS_PN, "bcs_pn" },
{ SPARC_INS_ALIAS_BCS_A_PN, "bcs_a_pn" },
{ SPARC_INS_ALIAS_MOVCS, "movcs" },
{ SPARC_INS_ALIAS_FMOVSCS, "fmovscs" },
{ SPARC_INS_ALIAS_FMOVDCS, "fmovdcs" },
{ SPARC_INS_ALIAS_FMOVQCS, "fmovqcs" },
{ SPARC_INS_ALIAS_TCS, "tcs" },
{ SPARC_INS_ALIAS_BPOS, "bpos" },
{ SPARC_INS_ALIAS_BPOS_A, "bpos_a" },
{ SPARC_INS_ALIAS_BPOS_PT, "bpos_pt" },
{ SPARC_INS_ALIAS_BPOS_A_PT, "bpos_a_pt" },
{ SPARC_INS_ALIAS_BPOS_PN, "bpos_pn" },
{ SPARC_INS_ALIAS_BPOS_A_PN, "bpos_a_pn" },
{ SPARC_INS_ALIAS_MOVPOS, "movpos" },
{ SPARC_INS_ALIAS_FMOVSPOS, "fmovspos" },
{ SPARC_INS_ALIAS_FMOVDPOS, "fmovdpos" },
{ SPARC_INS_ALIAS_FMOVQPOS, "fmovqpos" },
{ SPARC_INS_ALIAS_TPOS, "tpos" },
{ SPARC_INS_ALIAS_BNEG, "bneg" },
{ SPARC_INS_ALIAS_BNEG_A, "bneg_a" },
{ SPARC_INS_ALIAS_BNEG_PT, "bneg_pt" },
{ SPARC_INS_ALIAS_BNEG_A_PT, "bneg_a_pt" },
{ SPARC_INS_ALIAS_BNEG_PN, "bneg_pn" },
{ SPARC_INS_ALIAS_BNEG_A_PN, "bneg_a_pn" },
{ SPARC_INS_ALIAS_MOVNEG, "movneg" },
{ SPARC_INS_ALIAS_FMOVSNEG, "fmovsneg" },
{ SPARC_INS_ALIAS_FMOVDNEG, "fmovdneg" },
{ SPARC_INS_ALIAS_FMOVQNEG, "fmovqneg" },
{ SPARC_INS_ALIAS_TNEG, "tneg" },
{ SPARC_INS_ALIAS_BVC, "bvc" },
{ SPARC_INS_ALIAS_BVC_A, "bvc_a" },
{ SPARC_INS_ALIAS_BVC_PT, "bvc_pt" },
{ SPARC_INS_ALIAS_BVC_A_PT, "bvc_a_pt" },
{ SPARC_INS_ALIAS_BVC_PN, "bvc_pn" },
{ SPARC_INS_ALIAS_BVC_A_PN, "bvc_a_pn" },
{ SPARC_INS_ALIAS_MOVVC, "movvc" },
{ SPARC_INS_ALIAS_FMOVSVC, "fmovsvc" },
{ SPARC_INS_ALIAS_FMOVDVC, "fmovdvc" },
{ SPARC_INS_ALIAS_FMOVQVC, "fmovqvc" },
{ SPARC_INS_ALIAS_TVC, "tvc" },
{ SPARC_INS_ALIAS_BVS, "bvs" },
{ SPARC_INS_ALIAS_BVS_A, "bvs_a" },
{ SPARC_INS_ALIAS_BVS_PT, "bvs_pt" },
{ SPARC_INS_ALIAS_BVS_A_PT, "bvs_a_pt" },
{ SPARC_INS_ALIAS_BVS_PN, "bvs_pn" },
{ SPARC_INS_ALIAS_BVS_A_PN, "bvs_a_pn" },
{ SPARC_INS_ALIAS_MOVVS, "movvs" },
{ SPARC_INS_ALIAS_FMOVSVS, "fmovsvs" },
{ SPARC_INS_ALIAS_FMOVDVS, "fmovdvs" },
{ SPARC_INS_ALIAS_FMOVQVS, "fmovqvs" },
{ SPARC_INS_ALIAS_TVS, "tvs" },
{ SPARC_INS_ALIAS_FBN, "fbn" },
{ SPARC_INS_ALIAS_FBN_PT, "fbn_pt" },
{ SPARC_INS_ALIAS_FBN_A, "fbn_a" },
{ SPARC_INS_ALIAS_FBN_A_PT, "fbn_a_pt" },
{ SPARC_INS_ALIAS_FBN_PN, "fbn_pn" },
{ SPARC_INS_ALIAS_FBN_A_PN, "fbn_a_pn" },
{ SPARC_INS_ALIAS_FBU, "fbu" },
{ SPARC_INS_ALIAS_FBU_PT, "fbu_pt" },
{ SPARC_INS_ALIAS_FBU_A, "fbu_a" },
{ SPARC_INS_ALIAS_FBU_A_PT, "fbu_a_pt" },
{ SPARC_INS_ALIAS_FBU_PN, "fbu_pn" },
{ SPARC_INS_ALIAS_FBU_A_PN, "fbu_a_pn" },
{ SPARC_INS_ALIAS_MOVU, "movu" },
{ SPARC_INS_ALIAS_FMOVSU, "fmovsu" },
{ SPARC_INS_ALIAS_FMOVDU, "fmovdu" },
{ SPARC_INS_ALIAS_FMOVQU, "fmovqu" },
{ SPARC_INS_ALIAS_FBG, "fbg" },
{ SPARC_INS_ALIAS_FBG_PT, "fbg_pt" },
{ SPARC_INS_ALIAS_FBG_A, "fbg_a" },
{ SPARC_INS_ALIAS_FBG_A_PT, "fbg_a_pt" },
{ SPARC_INS_ALIAS_FBG_PN, "fbg_pn" },
{ SPARC_INS_ALIAS_FBG_A_PN, "fbg_a_pn" },
{ SPARC_INS_ALIAS_FBUG, "fbug" },
{ SPARC_INS_ALIAS_FBUG_PT, "fbug_pt" },
{ SPARC_INS_ALIAS_FBUG_A, "fbug_a" },
{ SPARC_INS_ALIAS_FBUG_A_PT, "fbug_a_pt" },
{ SPARC_INS_ALIAS_FBUG_PN, "fbug_pn" },
{ SPARC_INS_ALIAS_FBUG_A_PN, "fbug_a_pn" },
{ SPARC_INS_ALIAS_MOVUG, "movug" },
{ SPARC_INS_ALIAS_FMOVSUG, "fmovsug" },
{ SPARC_INS_ALIAS_FMOVDUG, "fmovdug" },
{ SPARC_INS_ALIAS_FMOVQUG, "fmovqug" },
{ SPARC_INS_ALIAS_FBL, "fbl" },
{ SPARC_INS_ALIAS_FBL_PT, "fbl_pt" },
{ SPARC_INS_ALIAS_FBL_A, "fbl_a" },
{ SPARC_INS_ALIAS_FBL_A_PT, "fbl_a_pt" },
{ SPARC_INS_ALIAS_FBL_PN, "fbl_pn" },
{ SPARC_INS_ALIAS_FBL_A_PN, "fbl_a_pn" },
{ SPARC_INS_ALIAS_FBUL, "fbul" },
{ SPARC_INS_ALIAS_FBUL_PT, "fbul_pt" },
{ SPARC_INS_ALIAS_FBUL_A, "fbul_a" },
{ SPARC_INS_ALIAS_FBUL_A_PT, "fbul_a_pt" },
{ SPARC_INS_ALIAS_FBUL_PN, "fbul_pn" },
{ SPARC_INS_ALIAS_FBUL_A_PN, "fbul_a_pn" },
{ SPARC_INS_ALIAS_MOVUL, "movul" },
{ SPARC_INS_ALIAS_FMOVSUL, "fmovsul" },
{ SPARC_INS_ALIAS_FMOVDUL, "fmovdul" },
{ SPARC_INS_ALIAS_FMOVQUL, "fmovqul" },
{ SPARC_INS_ALIAS_FBLG, "fblg" },
{ SPARC_INS_ALIAS_FBLG_PT, "fblg_pt" },
{ SPARC_INS_ALIAS_FBLG_A, "fblg_a" },
{ SPARC_INS_ALIAS_FBLG_A_PT, "fblg_a_pt" },
{ SPARC_INS_ALIAS_FBLG_PN, "fblg_pn" },
{ SPARC_INS_ALIAS_FBLG_A_PN, "fblg_a_pn" },
{ SPARC_INS_ALIAS_MOVLG, "movlg" },
{ SPARC_INS_ALIAS_FMOVSLG, "fmovslg" },
{ SPARC_INS_ALIAS_FMOVDLG, "fmovdlg" },
{ SPARC_INS_ALIAS_FMOVQLG, "fmovqlg" },
{ SPARC_INS_ALIAS_FBNE, "fbne" },
{ SPARC_INS_ALIAS_FBNE_PT, "fbne_pt" },
{ SPARC_INS_ALIAS_FBNE_A, "fbne_a" },
{ SPARC_INS_ALIAS_FBNE_A_PT, "fbne_a_pt" },
{ SPARC_INS_ALIAS_FBNE_PN, "fbne_pn" },
{ SPARC_INS_ALIAS_FBNE_A_PN, "fbne_a_pn" },
{ SPARC_INS_ALIAS_FBE, "fbe" },
{ SPARC_INS_ALIAS_FBE_PT, "fbe_pt" },
{ SPARC_INS_ALIAS_FBE_A, "fbe_a" },
{ SPARC_INS_ALIAS_FBE_A_PT, "fbe_a_pt" },
{ SPARC_INS_ALIAS_FBE_PN, "fbe_pn" },
{ SPARC_INS_ALIAS_FBE_A_PN, "fbe_a_pn" },
{ SPARC_INS_ALIAS_FBUE, "fbue" },
{ SPARC_INS_ALIAS_FBUE_PT, "fbue_pt" },
{ SPARC_INS_ALIAS_FBUE_A, "fbue_a" },
{ SPARC_INS_ALIAS_FBUE_A_PT, "fbue_a_pt" },
{ SPARC_INS_ALIAS_FBUE_PN, "fbue_pn" },
{ SPARC_INS_ALIAS_FBUE_A_PN, "fbue_a_pn" },
{ SPARC_INS_ALIAS_MOVUE, "movue" },
{ SPARC_INS_ALIAS_FMOVSUE, "fmovsue" },
{ SPARC_INS_ALIAS_FMOVDUE, "fmovdue" },
{ SPARC_INS_ALIAS_FMOVQUE, "fmovque" },
{ SPARC_INS_ALIAS_FBGE, "fbge" },
{ SPARC_INS_ALIAS_FBGE_PT, "fbge_pt" },
{ SPARC_INS_ALIAS_FBGE_A, "fbge_a" },
{ SPARC_INS_ALIAS_FBGE_A_PT, "fbge_a_pt" },
{ SPARC_INS_ALIAS_FBGE_PN, "fbge_pn" },
{ SPARC_INS_ALIAS_FBGE_A_PN, "fbge_a_pn" },
{ SPARC_INS_ALIAS_FBUGE, "fbuge" },
{ SPARC_INS_ALIAS_FBUGE_PT, "fbuge_pt" },
{ SPARC_INS_ALIAS_FBUGE_A, "fbuge_a" },
{ SPARC_INS_ALIAS_FBUGE_A_PT, "fbuge_a_pt" },
{ SPARC_INS_ALIAS_FBUGE_PN, "fbuge_pn" },
{ SPARC_INS_ALIAS_FBUGE_A_PN, "fbuge_a_pn" },
{ SPARC_INS_ALIAS_MOVUGE, "movuge" },
{ SPARC_INS_ALIAS_FMOVSUGE, "fmovsuge" },
{ SPARC_INS_ALIAS_FMOVDUGE, "fmovduge" },
{ SPARC_INS_ALIAS_FMOVQUGE, "fmovquge" },
{ SPARC_INS_ALIAS_FBLE, "fble" },
{ SPARC_INS_ALIAS_FBLE_PT, "fble_pt" },
{ SPARC_INS_ALIAS_FBLE_A, "fble_a" },
{ SPARC_INS_ALIAS_FBLE_A_PT, "fble_a_pt" },
{ SPARC_INS_ALIAS_FBLE_PN, "fble_pn" },
{ SPARC_INS_ALIAS_FBLE_A_PN, "fble_a_pn" },
{ SPARC_INS_ALIAS_FBULE, "fbule" },
{ SPARC_INS_ALIAS_FBULE_PT, "fbule_pt" },
{ SPARC_INS_ALIAS_FBULE_A, "fbule_a" },
{ SPARC_INS_ALIAS_FBULE_A_PT, "fbule_a_pt" },
{ SPARC_INS_ALIAS_FBULE_PN, "fbule_pn" },
{ SPARC_INS_ALIAS_FBULE_A_PN, "fbule_a_pn" },
{ SPARC_INS_ALIAS_MOVULE, "movule" },
{ SPARC_INS_ALIAS_FMOVSULE, "fmovsule" },
{ SPARC_INS_ALIAS_FMOVDULE, "fmovdule" },
{ SPARC_INS_ALIAS_FMOVQULE, "fmovqule" },
{ SPARC_INS_ALIAS_FBO, "fbo" },
{ SPARC_INS_ALIAS_FBO_PT, "fbo_pt" },
{ SPARC_INS_ALIAS_FBO_A, "fbo_a" },
{ SPARC_INS_ALIAS_FBO_A_PT, "fbo_a_pt" },
{ SPARC_INS_ALIAS_FBO_PN, "fbo_pn" },
{ SPARC_INS_ALIAS_FBO_A_PN, "fbo_a_pn" },
{ SPARC_INS_ALIAS_MOVO, "movo" },
{ SPARC_INS_ALIAS_FMOVSO, "fmovso" },
{ SPARC_INS_ALIAS_FMOVDO, "fmovdo" },
{ SPARC_INS_ALIAS_FMOVQO, "fmovqo" },
{ SPARC_INS_ALIAS_BRLEZ, "brlez" },
{ SPARC_INS_ALIAS_BRLEZ_PT, "brlez_pt" },
{ SPARC_INS_ALIAS_BRLEZ_PN, "brlez_pn" },
{ SPARC_INS_ALIAS_BRLEZ_A, "brlez_a" },
{ SPARC_INS_ALIAS_BRLEZ_A_PT, "brlez_a_pt" },
{ SPARC_INS_ALIAS_BRLEZ_A_PN, "brlez_a_pn" },
{ SPARC_INS_ALIAS_MOVRLEZ, "movrlez" },
{ SPARC_INS_ALIAS_FMOVRSLEZ, "fmovrslez" },
{ SPARC_INS_ALIAS_FMOVRDLEZ, "fmovrdlez" },
{ SPARC_INS_ALIAS_FMOVRQLEZ, "fmovrqlez" },
{ SPARC_INS_ALIAS_BRLZ, "brlz" },
{ SPARC_INS_ALIAS_BRLZ_PT, "brlz_pt" },
{ SPARC_INS_ALIAS_BRLZ_PN, "brlz_pn" },
{ SPARC_INS_ALIAS_BRLZ_A, "brlz_a" },
{ SPARC_INS_ALIAS_BRLZ_A_PT, "brlz_a_pt" },
{ SPARC_INS_ALIAS_BRLZ_A_PN, "brlz_a_pn" },
{ SPARC_INS_ALIAS_MOVRLZ, "movrlz" },
{ SPARC_INS_ALIAS_FMOVRSLZ, "fmovrslz" },
{ SPARC_INS_ALIAS_FMOVRDLZ, "fmovrdlz" },
{ SPARC_INS_ALIAS_FMOVRQLZ, "fmovrqlz" },
{ SPARC_INS_ALIAS_BRNZ, "brnz" },
{ SPARC_INS_ALIAS_BRNZ_PT, "brnz_pt" },
{ SPARC_INS_ALIAS_BRNZ_PN, "brnz_pn" },
{ SPARC_INS_ALIAS_BRNZ_A, "brnz_a" },
{ SPARC_INS_ALIAS_BRNZ_A_PT, "brnz_a_pt" },
{ SPARC_INS_ALIAS_BRNZ_A_PN, "brnz_a_pn" },
{ SPARC_INS_ALIAS_MOVRNZ, "movrnz" },
{ SPARC_INS_ALIAS_FMOVRSNZ, "fmovrsnz" },
{ SPARC_INS_ALIAS_FMOVRDNZ, "fmovrdnz" },
{ SPARC_INS_ALIAS_FMOVRQNZ, "fmovrqnz" },
{ SPARC_INS_ALIAS_BRGZ, "brgz" },
{ SPARC_INS_ALIAS_BRGZ_PT, "brgz_pt" },
{ SPARC_INS_ALIAS_BRGZ_PN, "brgz_pn" },
{ SPARC_INS_ALIAS_BRGZ_A, "brgz_a" },
{ SPARC_INS_ALIAS_BRGZ_A_PT, "brgz_a_pt" },
{ SPARC_INS_ALIAS_BRGZ_A_PN, "brgz_a_pn" },
{ SPARC_INS_ALIAS_MOVRGZ, "movrgz" },
{ SPARC_INS_ALIAS_FMOVRSGZ, "fmovrsgz" },
{ SPARC_INS_ALIAS_FMOVRDGZ, "fmovrdgz" },
{ SPARC_INS_ALIAS_FMOVRQGZ, "fmovrqgz" },
{ SPARC_INS_ALIAS_BRGEZ, "brgez" },
{ SPARC_INS_ALIAS_BRGEZ_PT, "brgez_pt" },
{ SPARC_INS_ALIAS_BRGEZ_PN, "brgez_pn" },
{ SPARC_INS_ALIAS_BRGEZ_A, "brgez_a" },
{ SPARC_INS_ALIAS_BRGEZ_A_PT, "brgez_a_pt" },
{ SPARC_INS_ALIAS_BRGEZ_A_PN, "brgez_a_pn" },
{ SPARC_INS_ALIAS_MOVRGEZ, "movrgez" },
{ SPARC_INS_ALIAS_FMOVRSGEZ, "fmovrsgez" },
{ SPARC_INS_ALIAS_FMOVRDGEZ, "fmovrdgez" },
{ SPARC_INS_ALIAS_FMOVRQGEZ, "fmovrqgez" },
{ SPARC_INS_ALIAS_CMP, "cmp" },
{ SPARC_INS_ALIAS_TST, "tst" },
{ SPARC_INS_ALIAS_RET, "ret" },
{ SPARC_INS_ALIAS_RETL, "retl" },
{ SPARC_INS_ALIAS_RESTORE, "restore" },
{ SPARC_INS_ALIAS_SAVE, "save" },
{ SPARC_INS_ALIAS_CAS, "cas" },
{ SPARC_INS_ALIAS_CASL, "casl" },
{ SPARC_INS_ALIAS_CASX, "casx" },
{ SPARC_INS_ALIAS_CASXL, "casxl" },
{ SPARC_INS_ALIAS_MOV, "mov" },
{ SPARC_INS_ALIAS_FCMPS, "fcmps" },
{ SPARC_INS_ALIAS_FCMPD, "fcmpd" },
{ SPARC_INS_ALIAS_FCMPQ, "fcmpq" },
{ SPARC_INS_ALIAS_FCMPES, "fcmpes" },
{ SPARC_INS_ALIAS_FCMPED, "fcmped" },
{ SPARC_INS_ALIAS_FCMPEQ, "fcmpeq" },

21
external/capstone/arch/Sparc/SparcGenCSFeatureName.inc vendored Normal file
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@@ -0,0 +1,21 @@
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
{ SPARC_FEATURE_IS64BIT, "Is64Bit" },
{ SPARC_FEATURE_USESOFTMULDIV, "UseSoftMulDiv" },
{ SPARC_FEATURE_HASV9, "HasV9" },
{ SPARC_FEATURE_HASVIS, "HasVIS" },
{ SPARC_FEATURE_HASVIS2, "HasVIS2" },
{ SPARC_FEATURE_HASVIS3, "HasVIS3" },
{ SPARC_FEATURE_HASCASA, "HasCASA" },
{ SPARC_FEATURE_HASPWRPSR, "HasPWRPSR" },

5969
external/capstone/arch/Sparc/SparcGenCSMappingInsn.inc vendored Normal file
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298
external/capstone/arch/Sparc/SparcGenCSMappingInsnName.inc vendored Normal file
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@@ -0,0 +1,298 @@
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
"invalid", // SPARC_INS_INVALID
"set", // SPARC_INS_SET
"setx", // SPARC_INS_SETX
"addcc", // SPARC_INS_ADDCC
"addx", // SPARC_INS_ADDX
"addxcc", // SPARC_INS_ADDXCC
"addxc", // SPARC_INS_ADDXC
"addxccc", // SPARC_INS_ADDXCCC
"add", // SPARC_INS_ADD
"alignaddr", // SPARC_INS_ALIGNADDR
"alignaddrl", // SPARC_INS_ALIGNADDRL
"andcc", // SPARC_INS_ANDCC
"andncc", // SPARC_INS_ANDNCC
"andn", // SPARC_INS_ANDN
"and", // SPARC_INS_AND
"array16", // SPARC_INS_ARRAY16
"array32", // SPARC_INS_ARRAY32
"array8", // SPARC_INS_ARRAY8
"b", // SPARC_INS_B
"bmask", // SPARC_INS_BMASK
"fb", // SPARC_INS_FB
"br", // SPARC_INS_BR
"bshuffle", // SPARC_INS_BSHUFFLE
"call", // SPARC_INS_CALL
"casa", // SPARC_INS_CASA
"casxa", // SPARC_INS_CASXA
"cb", // SPARC_INS_CB
"cmask16", // SPARC_INS_CMASK16
"cmask32", // SPARC_INS_CMASK32
"cmask8", // SPARC_INS_CMASK8
"done", // SPARC_INS_DONE
"edge16", // SPARC_INS_EDGE16
"edge16l", // SPARC_INS_EDGE16L
"edge16ln", // SPARC_INS_EDGE16LN
"edge16n", // SPARC_INS_EDGE16N
"edge32", // SPARC_INS_EDGE32
"edge32l", // SPARC_INS_EDGE32L
"edge32ln", // SPARC_INS_EDGE32LN
"edge32n", // SPARC_INS_EDGE32N
"edge8", // SPARC_INS_EDGE8
"edge8l", // SPARC_INS_EDGE8L
"edge8ln", // SPARC_INS_EDGE8LN
"edge8n", // SPARC_INS_EDGE8N
"fabsd", // SPARC_INS_FABSD
"fabsq", // SPARC_INS_FABSQ
"fabss", // SPARC_INS_FABSS
"faddd", // SPARC_INS_FADDD
"faddq", // SPARC_INS_FADDQ
"fadds", // SPARC_INS_FADDS
"faligndata", // SPARC_INS_FALIGNDATA
"fand", // SPARC_INS_FAND
"fandnot1", // SPARC_INS_FANDNOT1
"fandnot1s", // SPARC_INS_FANDNOT1S
"fandnot2", // SPARC_INS_FANDNOT2
"fandnot2s", // SPARC_INS_FANDNOT2S
"fands", // SPARC_INS_FANDS
"fchksm16", // SPARC_INS_FCHKSM16
"fcmpeq16", // SPARC_INS_FCMPEQ16
"fcmpeq32", // SPARC_INS_FCMPEQ32
"fcmpgt16", // SPARC_INS_FCMPGT16
"fcmpgt32", // SPARC_INS_FCMPGT32
"fcmple16", // SPARC_INS_FCMPLE16
"fcmple32", // SPARC_INS_FCMPLE32
"fcmpne16", // SPARC_INS_FCMPNE16
"fcmpne32", // SPARC_INS_FCMPNE32
"fdivd", // SPARC_INS_FDIVD
"fdivq", // SPARC_INS_FDIVQ
"fdivs", // SPARC_INS_FDIVS
"fdmulq", // SPARC_INS_FDMULQ
"fdtoi", // SPARC_INS_FDTOI
"fdtoq", // SPARC_INS_FDTOQ
"fdtos", // SPARC_INS_FDTOS
"fdtox", // SPARC_INS_FDTOX
"fexpand", // SPARC_INS_FEXPAND
"fhaddd", // SPARC_INS_FHADDD
"fhadds", // SPARC_INS_FHADDS
"fhsubd", // SPARC_INS_FHSUBD
"fhsubs", // SPARC_INS_FHSUBS
"fitod", // SPARC_INS_FITOD
"fitoq", // SPARC_INS_FITOQ
"fitos", // SPARC_INS_FITOS
"flcmpd", // SPARC_INS_FLCMPD
"flcmps", // SPARC_INS_FLCMPS
"flush", // SPARC_INS_FLUSH
"flushw", // SPARC_INS_FLUSHW
"fmean16", // SPARC_INS_FMEAN16
"fmovd", // SPARC_INS_FMOVD
"fmovq", // SPARC_INS_FMOVQ
"fmovrd", // SPARC_INS_FMOVRD
"fmovrq", // SPARC_INS_FMOVRQ
"fmovrs", // SPARC_INS_FMOVRS
"fmovs", // SPARC_INS_FMOVS
"fmul8sux16", // SPARC_INS_FMUL8SUX16
"fmul8ulx16", // SPARC_INS_FMUL8ULX16
"fmul8x16", // SPARC_INS_FMUL8X16
"fmul8x16al", // SPARC_INS_FMUL8X16AL
"fmul8x16au", // SPARC_INS_FMUL8X16AU
"fmuld", // SPARC_INS_FMULD
"fmuld8sux16", // SPARC_INS_FMULD8SUX16
"fmuld8ulx16", // SPARC_INS_FMULD8ULX16
"fmulq", // SPARC_INS_FMULQ
"fmuls", // SPARC_INS_FMULS
"fnaddd", // SPARC_INS_FNADDD
"fnadds", // SPARC_INS_FNADDS
"fnand", // SPARC_INS_FNAND
"fnands", // SPARC_INS_FNANDS
"fnegd", // SPARC_INS_FNEGD
"fnegq", // SPARC_INS_FNEGQ
"fnegs", // SPARC_INS_FNEGS
"fnhaddd", // SPARC_INS_FNHADDD
"fnhadds", // SPARC_INS_FNHADDS
"fnor", // SPARC_INS_FNOR
"fnors", // SPARC_INS_FNORS
"fnot1", // SPARC_INS_FNOT1
"fnot1s", // SPARC_INS_FNOT1S
"fnot2", // SPARC_INS_FNOT2
"fnot2s", // SPARC_INS_FNOT2S
"fone", // SPARC_INS_FONE
"fones", // SPARC_INS_FONES
"for", // SPARC_INS_FOR
"fornot1", // SPARC_INS_FORNOT1
"fornot1s", // SPARC_INS_FORNOT1S
"fornot2", // SPARC_INS_FORNOT2
"fornot2s", // SPARC_INS_FORNOT2S
"fors", // SPARC_INS_FORS
"fpack16", // SPARC_INS_FPACK16
"fpack32", // SPARC_INS_FPACK32
"fpackfix", // SPARC_INS_FPACKFIX
"fpadd16", // SPARC_INS_FPADD16
"fpadd16s", // SPARC_INS_FPADD16S
"fpadd32", // SPARC_INS_FPADD32
"fpadd32s", // SPARC_INS_FPADD32S
"fpadd64", // SPARC_INS_FPADD64
"fpmerge", // SPARC_INS_FPMERGE
"fpsub16", // SPARC_INS_FPSUB16
"fpsub16S", // SPARC_INS_FPSUB16S
"fpsub32", // SPARC_INS_FPSUB32
"fpsub32S", // SPARC_INS_FPSUB32S
"fqtod", // SPARC_INS_FQTOD
"fqtoi", // SPARC_INS_FQTOI
"fqtos", // SPARC_INS_FQTOS
"fqtox", // SPARC_INS_FQTOX
"fslas16", // SPARC_INS_FSLAS16
"fslas32", // SPARC_INS_FSLAS32
"fsll16", // SPARC_INS_FSLL16
"fsll32", // SPARC_INS_FSLL32
"fsmuld", // SPARC_INS_FSMULD
"fsqrtd", // SPARC_INS_FSQRTD
"fsqrtq", // SPARC_INS_FSQRTQ
"fsqrts", // SPARC_INS_FSQRTS
"fsra16", // SPARC_INS_FSRA16
"fsra32", // SPARC_INS_FSRA32
"fsrc1", // SPARC_INS_FSRC1
"fsrc1s", // SPARC_INS_FSRC1S
"fsrc2", // SPARC_INS_FSRC2
"fsrc2s", // SPARC_INS_FSRC2S
"fsrl16", // SPARC_INS_FSRL16
"fsrl32", // SPARC_INS_FSRL32
"fstod", // SPARC_INS_FSTOD
"fstoi", // SPARC_INS_FSTOI
"fstoq", // SPARC_INS_FSTOQ
"fstox", // SPARC_INS_FSTOX
"fsubd", // SPARC_INS_FSUBD
"fsubq", // SPARC_INS_FSUBQ
"fsubs", // SPARC_INS_FSUBS
"fxnor", // SPARC_INS_FXNOR
"fxnors", // SPARC_INS_FXNORS
"fxor", // SPARC_INS_FXOR
"fxors", // SPARC_INS_FXORS
"fxtod", // SPARC_INS_FXTOD
"fxtoq", // SPARC_INS_FXTOQ
"fxtos", // SPARC_INS_FXTOS
"fzero", // SPARC_INS_FZERO
"fzeros", // SPARC_INS_FZEROS
"ldx", // SPARC_INS_LDX
"ld", // SPARC_INS_LD
"jmpl", // SPARC_INS_JMPL
"lda", // SPARC_INS_LDA
"ldda", // SPARC_INS_LDDA
"ldd", // SPARC_INS_LDD
"ldqa", // SPARC_INS_LDQA
"ldq", // SPARC_INS_LDQ
"ldsba", // SPARC_INS_LDSBA
"ldsb", // SPARC_INS_LDSB
"ldsha", // SPARC_INS_LDSHA
"ldsh", // SPARC_INS_LDSH
"ldstuba", // SPARC_INS_LDSTUBA
"ldstub", // SPARC_INS_LDSTUB
"ldswa", // SPARC_INS_LDSWA
"ldsw", // SPARC_INS_LDSW
"lduba", // SPARC_INS_LDUBA
"ldub", // SPARC_INS_LDUB
"lduha", // SPARC_INS_LDUHA
"lduh", // SPARC_INS_LDUH
"ldxa", // SPARC_INS_LDXA
"lzcnt", // SPARC_INS_LZCNT
"membar", // SPARC_INS_MEMBAR
"movdtox", // SPARC_INS_MOVDTOX
"mov", // SPARC_INS_MOV
"movr", // SPARC_INS_MOVR
"movstosw", // SPARC_INS_MOVSTOSW
"movstouw", // SPARC_INS_MOVSTOUW
"mulscc", // SPARC_INS_MULSCC
"mulx", // SPARC_INS_MULX
"nop", // SPARC_INS_NOP
"orcc", // SPARC_INS_ORCC
"orncc", // SPARC_INS_ORNCC
"orn", // SPARC_INS_ORN
"or", // SPARC_INS_OR
"pdist", // SPARC_INS_PDIST
"pdistn", // SPARC_INS_PDISTN
"popc", // SPARC_INS_POPC
"prefetch", // SPARC_INS_PREFETCH
"pwr", // SPARC_INS_PWR
"rd", // SPARC_INS_RD
"rdpr", // SPARC_INS_RDPR
"restored", // SPARC_INS_RESTORED
"restore", // SPARC_INS_RESTORE
"retry", // SPARC_INS_RETRY
"rett", // SPARC_INS_RETT
"saved", // SPARC_INS_SAVED
"save", // SPARC_INS_SAVE
"sdivcc", // SPARC_INS_SDIVCC
"sdivx", // SPARC_INS_SDIVX
"sdiv", // SPARC_INS_SDIV
"sethi", // SPARC_INS_SETHI
"shutdown", // SPARC_INS_SHUTDOWN
"siam", // SPARC_INS_SIAM
"sir", // SPARC_INS_SIR
"sllx", // SPARC_INS_SLLX
"sll", // SPARC_INS_SLL
"smac", // SPARC_INS_SMAC
"smulcc", // SPARC_INS_SMULCC
"smul", // SPARC_INS_SMUL
"srax", // SPARC_INS_SRAX
"sra", // SPARC_INS_SRA
"srlx", // SPARC_INS_SRLX
"srl", // SPARC_INS_SRL
"sta", // SPARC_INS_STA
"stbar", // SPARC_INS_STBAR
"stba", // SPARC_INS_STBA
"stb", // SPARC_INS_STB
"st", // SPARC_INS_ST
"stda", // SPARC_INS_STDA
"std", // SPARC_INS_STD
"stha", // SPARC_INS_STHA
"sth", // SPARC_INS_STH
"stqa", // SPARC_INS_STQA
"stq", // SPARC_INS_STQ
"stxa", // SPARC_INS_STXA
"stx", // SPARC_INS_STX
"subcc", // SPARC_INS_SUBCC
"subx", // SPARC_INS_SUBX
"subxcc", // SPARC_INS_SUBXCC
"sub", // SPARC_INS_SUB
"swapa", // SPARC_INS_SWAPA
"swap", // SPARC_INS_SWAP
"ta", // SPARC_INS_TA
"taddcctv", // SPARC_INS_TADDCCTV
"taddcc", // SPARC_INS_TADDCC
"t", // SPARC_INS_T
"tsubcctv", // SPARC_INS_TSUBCCTV
"tsubcc", // SPARC_INS_TSUBCC
"udivcc", // SPARC_INS_UDIVCC
"udivx", // SPARC_INS_UDIVX
"udiv", // SPARC_INS_UDIV
"umac", // SPARC_INS_UMAC
"umulcc", // SPARC_INS_UMULCC
"umulxhi", // SPARC_INS_UMULXHI
"umul", // SPARC_INS_UMUL
"unimp", // SPARC_INS_UNIMP
"fcmpd", // SPARC_INS_FCMPD
"fcmped", // SPARC_INS_FCMPED
"fcmpeq", // SPARC_INS_FCMPEQ
"fcmpes", // SPARC_INS_FCMPES
"fcmpq", // SPARC_INS_FCMPQ
"fcmps", // SPARC_INS_FCMPS
"wr", // SPARC_INS_WR
"wrpr", // SPARC_INS_WRPR
"xmulx", // SPARC_INS_XMULX
"xmulxhi", // SPARC_INS_XMULXHI
"xnorcc", // SPARC_INS_XNORCC
"xnor", // SPARC_INS_XNOR
"xorcc", // SPARC_INS_XORCC
"xor", // SPARC_INS_XOR

4202
external/capstone/arch/Sparc/SparcGenCSMappingInsnOp.inc vendored Normal file
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19
external/capstone/arch/Sparc/SparcGenCSOpGroup.inc vendored Normal file
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@@ -0,0 +1,19 @@
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
Sparc_OP_GROUP_Operand = 0,
Sparc_OP_GROUP_GetPCX = 1,
Sparc_OP_GROUP_CCOperand = 2,
Sparc_OP_GROUP_MemOperand = 3,
Sparc_OP_GROUP_ASITag = 4,
Sparc_OP_GROUP_MembarTag = 5,

4337
external/capstone/arch/Sparc/SparcGenDisassemblerTables.inc vendored
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2300
external/capstone/arch/Sparc/SparcGenInstrInfo.inc vendored
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1409
external/capstone/arch/Sparc/SparcGenRegisterInfo.inc vendored
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77
external/capstone/arch/Sparc/SparcGenSubtargetInfo.inc vendored
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@@ -1,27 +1,70 @@
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|* *|
|*Subtarget Enumeration Source Fragment *|
|* *|
|* Automatically generated file, do not edit! *|
|* *|
\*===----------------------------------------------------------------------===*/
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
#ifdef GET_SUBTARGETINFO_ENUM
#undef GET_SUBTARGETINFO_ENUM
enum {
Sparc_FeatureHardQuad = 1ULL << 0,
Sparc_FeatureV8Deprecated = 1ULL << 1,
Sparc_FeatureV9 = 1ULL << 2,
Sparc_FeatureVIS = 1ULL << 3,
Sparc_FeatureVIS2 = 1ULL << 4,
Sparc_FeatureVIS3 = 1ULL << 5,
Sparc_UsePopc = 1ULL << 6
Sparc_DetectRoundChange = 0,
Sparc_FeatureHardQuad = 1,
Sparc_FeatureLeon = 2,
Sparc_FeatureNoFMULS = 3,
Sparc_FeatureNoFSMULD = 4,
Sparc_FeaturePWRPSR = 5,
Sparc_FeatureReserveG1 = 6,
Sparc_FeatureReserveG2 = 7,
Sparc_FeatureReserveG3 = 8,
Sparc_FeatureReserveG4 = 9,
Sparc_FeatureReserveG5 = 10,
Sparc_FeatureReserveG6 = 11,
Sparc_FeatureReserveG7 = 12,
Sparc_FeatureReserveI0 = 13,
Sparc_FeatureReserveI1 = 14,
Sparc_FeatureReserveI2 = 15,
Sparc_FeatureReserveI3 = 16,
Sparc_FeatureReserveI4 = 17,
Sparc_FeatureReserveI5 = 18,
Sparc_FeatureReserveL0 = 19,
Sparc_FeatureReserveL1 = 20,
Sparc_FeatureReserveL2 = 21,
Sparc_FeatureReserveL3 = 22,
Sparc_FeatureReserveL4 = 23,
Sparc_FeatureReserveL5 = 24,
Sparc_FeatureReserveL6 = 25,
Sparc_FeatureReserveL7 = 26,
Sparc_FeatureReserveO0 = 27,
Sparc_FeatureReserveO1 = 28,
Sparc_FeatureReserveO2 = 29,
Sparc_FeatureReserveO3 = 30,
Sparc_FeatureReserveO4 = 31,
Sparc_FeatureReserveO5 = 32,
Sparc_FeatureSoftFloat = 33,
Sparc_FeatureSoftMulDiv = 34,
Sparc_FeatureV8Deprecated = 35,
Sparc_FeatureV9 = 36,
Sparc_FeatureVIS = 37,
Sparc_FeatureVIS2 = 38,
Sparc_FeatureVIS3 = 39,
Sparc_FixAllFDIVSQRT = 40,
Sparc_InsertNOPLoad = 41,
Sparc_LeonCASA = 42,
Sparc_LeonCycleCounter = 43,
Sparc_TuneSlowRDPC = 44,
Sparc_UMACSMACSupport = 45,
Sparc_UsePopc = 46,
Sparc_NumSubtargetFeatures = 47
};
#endif // GET_SUBTARGETINFO_ENUM

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external/capstone/arch/Sparc/SparcGenSystemOperands.inc vendored Normal file
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/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
#ifdef GET_ASITAG_DECL
#endif
#ifdef GET_ASITAG_DECL
const Sparc_ASITag_ASITag *Sparc_ASITag_lookupASITagByName(const char * Name);
const Sparc_ASITag_ASITag *Sparc_ASITag_lookupASITagByAltName(const char * AltName);
const Sparc_ASITag_ASITag *Sparc_ASITag_lookupASITagByEncoding(uint8_t Encoding);
#endif
#ifdef GET_ASITAG_IMPL
static const Sparc_ASITag_ASITag ASITagsList[] = {
{ "ASI_AIUP", { .raw_val = SPARC_ASITAG_ASI_AIUP }, "ASI_AS_IF_USER_PRIMARY", { .raw_val = SPARC_ASITAG_ASI_AS_IF_USER_PRIMARY }, 0x10 }, // 0
{ "ASI_AIUP_L", { .raw_val = SPARC_ASITAG_ASI_AIUP_L }, "ASI_AS_IF_USER_PRIMARY_LITTLE", { .raw_val = SPARC_ASITAG_ASI_AS_IF_USER_PRIMARY_LITTLE }, 0x18 }, // 1
{ "ASI_AIUS", { .raw_val = SPARC_ASITAG_ASI_AIUS }, "ASI_AS_IF_USER_SECONDARY", { .raw_val = SPARC_ASITAG_ASI_AS_IF_USER_SECONDARY }, 0x11 }, // 2
{ "ASI_AIUS_L", { .raw_val = SPARC_ASITAG_ASI_AIUS_L }, "ASI_AS_IF_USER_SECONDARY_LITTLE", { .raw_val = SPARC_ASITAG_ASI_AS_IF_USER_SECONDARY_LITTLE }, 0x19 }, // 3
{ "ASI_N", { .raw_val = SPARC_ASITAG_ASI_N }, "ASI_NUCLEUS", { .raw_val = SPARC_ASITAG_ASI_NUCLEUS }, 0x4 }, // 4
{ "ASI_N_L", { .raw_val = SPARC_ASITAG_ASI_N_L }, "ASI_NUCLEUS_LITTLE", { .raw_val = SPARC_ASITAG_ASI_NUCLEUS_LITTLE }, 0xC }, // 5
{ "ASI_P", { .raw_val = SPARC_ASITAG_ASI_P }, "ASI_PRIMARY", { .raw_val = SPARC_ASITAG_ASI_PRIMARY }, 0x80 }, // 6
{ "ASI_PNF", { .raw_val = SPARC_ASITAG_ASI_PNF }, "ASI_PRIMARY_NOFAULT", { .raw_val = SPARC_ASITAG_ASI_PRIMARY_NOFAULT }, 0x82 }, // 7
{ "ASI_PNF_L", { .raw_val = SPARC_ASITAG_ASI_PNF_L }, "ASI_PRIMARY_NOFAULT_LITTLE", { .raw_val = SPARC_ASITAG_ASI_PRIMARY_NOFAULT_LITTLE }, 0x8A }, // 8
{ "ASI_P_L", { .raw_val = SPARC_ASITAG_ASI_P_L }, "ASI_PRIMARY_LITTLE", { .raw_val = SPARC_ASITAG_ASI_PRIMARY_LITTLE }, 0x88 }, // 9
{ "ASI_S", { .raw_val = SPARC_ASITAG_ASI_S }, "ASI_SECONDARY", { .raw_val = SPARC_ASITAG_ASI_SECONDARY }, 0x81 }, // 10
{ "ASI_SNF", { .raw_val = SPARC_ASITAG_ASI_SNF }, "ASI_SECONDARY_NOFAULT", { .raw_val = SPARC_ASITAG_ASI_SECONDARY_NOFAULT }, 0x83 }, // 11
{ "ASI_SNF_L", { .raw_val = SPARC_ASITAG_ASI_SNF_L }, "ASI_SECONDARY_NOFAULT_LITTLE", { .raw_val = SPARC_ASITAG_ASI_SECONDARY_NOFAULT_LITTLE }, 0x8B }, // 12
{ "ASI_S_L", { .raw_val = SPARC_ASITAG_ASI_S_L }, "ASI_SECONDARY_LITTLE", { .raw_val = SPARC_ASITAG_ASI_SECONDARY_LITTLE }, 0x89 }, // 13
};
const Sparc_ASITag_ASITag *Sparc_ASITag_lookupASITagByName(const char * Name) {
static const struct IndexTypeStr Index[] = {
{ "ASI_AIUP", 0 },
{ "ASI_AIUP_L", 1 },
{ "ASI_AIUS", 2 },
{ "ASI_AIUS_L", 3 },
{ "ASI_N", 4 },
{ "ASI_N_L", 5 },
{ "ASI_P", 6 },
{ "ASI_PNF", 7 },
{ "ASI_PNF_L", 8 },
{ "ASI_P_L", 9 },
{ "ASI_S", 10 },
{ "ASI_SNF", 11 },
{ "ASI_SNF_L", 12 },
{ "ASI_S_L", 13 },
};
unsigned i = binsearch_IndexTypeStrEncoding(Index, ARR_SIZE(Index), Name);
if (i == -1)
return NULL;
else
return &ASITagsList[Index[i].index];
}
const Sparc_ASITag_ASITag *Sparc_ASITag_lookupASITagByAltName(const char * AltName) {
static const struct IndexTypeStr Index[] = {
{ "ASI_AS_IF_USER_PRIMARY", 0 },
{ "ASI_AS_IF_USER_PRIMARY_LITTLE", 1 },
{ "ASI_AS_IF_USER_SECONDARY", 2 },
{ "ASI_AS_IF_USER_SECONDARY_LITTLE", 3 },
{ "ASI_NUCLEUS", 4 },
{ "ASI_NUCLEUS_LITTLE", 5 },
{ "ASI_PRIMARY", 6 },
{ "ASI_PRIMARY_LITTLE", 9 },
{ "ASI_PRIMARY_NOFAULT", 7 },
{ "ASI_PRIMARY_NOFAULT_LITTLE", 8 },
{ "ASI_SECONDARY", 10 },
{ "ASI_SECONDARY_LITTLE", 13 },
{ "ASI_SECONDARY_NOFAULT", 11 },
{ "ASI_SECONDARY_NOFAULT_LITTLE", 12 },
};
unsigned i = binsearch_IndexTypeStrEncoding(Index, ARR_SIZE(Index), AltName);
if (i == -1)
return NULL;
else
return &ASITagsList[Index[i].index];
}
const Sparc_ASITag_ASITag *Sparc_ASITag_lookupASITagByEncoding(uint8_t Encoding) {
static const struct IndexType Index[] = {
{ 0x4, 4 },
{ 0xC, 5 },
{ 0x10, 0 },
{ 0x11, 2 },
{ 0x18, 1 },
{ 0x19, 3 },
{ 0x80, 6 },
{ 0x81, 10 },
{ 0x82, 7 },
{ 0x83, 11 },
{ 0x88, 9 },
{ 0x89, 13 },
{ 0x8A, 8 },
{ 0x8B, 12 },
};
unsigned i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Encoding);
if (i == -1)
return NULL;
else
return &ASITagsList[Index[i].index];
}
#endif
#undef GET_ASITAG_DECL
#undef GET_ASITAG_IMPL

624
external/capstone/arch/Sparc/SparcInstPrinter.c vendored
View File

@@ -1,9 +1,22 @@
//===-- SparcInstPrinter.cpp - Convert Sparc MCInst to assembly syntax --------===//
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2023 */
/* Automatically translated source file from LLVM. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Only small edits allowed. */
/* For multiple similar edits, please create a Patch for the translator. */
/* Capstone's C++ file translator: */
/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
//===-- SparcInstPrinter.cpp - Convert Sparc MCInst to assembly syntax -----==//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
@@ -11,148 +24,142 @@
//
//===----------------------------------------------------------------------===//
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
#ifdef CAPSTONE_HAS_SPARC
#ifdef _MSC_VER
#define _CRT_SECURE_NO_WARNINGS
#endif
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <limits.h>
#include <stdlib.h>
#include <capstone/platform.h>
#include "../../MCInstPrinter.h"
#include "../../Mapping.h"
#include "SparcInstPrinter.h"
#include "../../MCInst.h"
#include "../../utils.h"
#include "../../SStream.h"
#include "../../MCRegisterInfo.h"
#include "../../MathExtras.h"
#include "SparcLinkage.h"
#include "SparcMCTargetDesc.h"
#include "SparcMapping.h"
#include "SparcDisassemblerExtension.h"
#include "Sparc.h"
#define CONCAT(a, b) CONCAT_(a, b)
#define CONCAT_(a, b) a##_##b
static const char *getRegisterName(unsigned RegNo);
static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI);
static void printMemOperand(MCInst *MI, int opNum, SStream *O, const char *Modifier);
#define DEBUG_TYPE "asm-printer"
static void printCustomAliasOperand(
MCInst *MI, uint64_t Address, unsigned OpIdx,
unsigned PrintMethodIdx,
SStream *OS);
static void printOperand(MCInst *MI, int opNum, SStream *O);
static void Sparc_add_hint(MCInst *MI, unsigned int hint)
#define GET_INSTRUCTION_NAME
#define PRINT_ALIAS_INSTR
#include "SparcGenAsmWriter.inc"
static void printRegName(SStream *OS, MCRegister Reg)
{
if (MI->csh->detail_opt) {
MI->flat_insn->detail->sparc.hint = hint;
}
SStream_concat1(OS, '%');
SStream_concat0(OS, getRegisterName(Reg, Sparc_NoRegAltName));
}
static void Sparc_add_reg(MCInst *MI, unsigned int reg)
static void printRegNameAlt(SStream *OS, MCRegister Reg, unsigned AltIdx)
{
if (MI->csh->detail_opt) {
MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].type = SPARC_OP_REG;
MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].reg = reg;
MI->flat_insn->detail->sparc.op_count++;
}
SStream_concat1(OS, '%');
SStream_concat0(OS, getRegisterName(Reg, AltIdx));
}
static void set_mem_access(MCInst *MI, bool status)
static void printInst(MCInst *MI, uint64_t Address, SStream *O)
{
if (MI->csh->detail_opt != CS_OPT_ON)
return;
bool isAlias = false;
bool useAliasDetails = map_use_alias_details(MI);
map_set_fill_detail_ops(MI, useAliasDetails);
MI->csh->doing_mem = status;
if (status) {
MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].type = SPARC_OP_MEM;
MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.base = SPARC_REG_INVALID;
MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.disp = 0;
if (!printAliasInstr(MI, Address, O) &&
!printSparcAliasInstr(MI, O)) {
MCInst_setIsAlias(MI, false);
} else {
// done, create the next operand slot
MI->flat_insn->detail->sparc.op_count++;
}
}
void Sparc_post_printer(csh ud, cs_insn *insn, SStream *insn_asm, MCInst *mci)
{
if (((cs_struct *)ud)->detail_opt != CS_OPT_ON)
isAlias = true;
MCInst_setIsAlias(MI, isAlias);
if (useAliasDetails) {
return;
// fix up some instructions
if (insn->id == SPARC_INS_CASX) {
// first op is actually a memop, not regop
uint8_t base = (uint8_t)insn->detail->sparc.operands[0].reg;
memset(&insn->detail->sparc.operands[0], 0, sizeof(cs_sparc_op));
insn->detail->sparc.operands[0].type = SPARC_OP_MEM;
insn->detail->sparc.operands[0].mem.base = base;
insn->detail->sparc.operands[0].mem.disp = 0;
}
}
static void printRegName(SStream *OS, unsigned RegNo)
{
SStream_concat0(OS, "%");
SStream_concat0(OS, getRegisterName(RegNo));
if (!isAlias || !useAliasDetails) {
map_set_fill_detail_ops(MI, !(isAlias && useAliasDetails));
if (isAlias)
SStream_Close(O);
printInstruction(MI, Address, O);
if (isAlias)
SStream_Open(O);
}
}
#define GET_INSTRINFO_ENUM
#include "SparcGenInstrInfo.inc"
#define GET_REGINFO_ENUM
#include "SparcGenRegisterInfo.inc"
static bool printSparcAliasInstr(MCInst *MI, SStream *O)
bool printSparcAliasInstr(MCInst *MI, SStream *O)
{
switch (MCInst_getOpcode(MI)) {
default: return false;
case SP_JMPLrr:
case SP_JMPLri:
default:
return false;
case Sparc_JMPLrr:
case Sparc_JMPLri: {
if (MCInst_getNumOperands(MI) != 3)
return false;
if (!MCOperand_isReg(MCInst_getOperand(MI, 0)))
if (!MCOperand_isReg(MCInst_getOperand(MI, (0))))
return false;
switch (MCOperand_getReg(MCInst_getOperand(MI, 0))) {
default: return false;
case SP_G0: // jmp $addr | ret | retl
if (MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
switch(MCOperand_getReg(MCInst_getOperand(MI, 1))) {
default: break;
case SP_I7: SStream_concat0(O, "ret"); MCInst_setOpcodePub(MI, SPARC_INS_RET); return true;
case SP_O7: SStream_concat0(O, "retl"); MCInst_setOpcodePub(MI, SPARC_INS_RETL); return true;
}
}
SStream_concat0(O, "jmp\t");
MCInst_setOpcodePub(MI, SPARC_INS_JMP);
printMemOperand(MI, 1, O, NULL);
switch (MCOperand_getReg(MCInst_getOperand(MI, (0)))) {
default:
return false;
case Sparc_G0: // jmp $addr | ret | retl
if (MCOperand_isImm(MCInst_getOperand(MI, (2))) &&
MCOperand_getImm(MCInst_getOperand(MI, (2))) == 8) {
switch (MCOperand_getReg(
MCInst_getOperand(MI, (1)))) {
default:
break;
case Sparc_I7:
SStream_concat0(O, "\tret");
return true;
case SP_O7: // call $addr
SStream_concat0(O, "call ");
MCInst_setOpcodePub(MI, SPARC_INS_CALL);
printMemOperand(MI, 1, O, NULL);
case Sparc_O7:
SStream_concat0(O, "\tretl");
return true;
}
case SP_V9FCMPS:
case SP_V9FCMPD:
case SP_V9FCMPQ:
case SP_V9FCMPES:
case SP_V9FCMPED:
case SP_V9FCMPEQ:
if (MI->csh->mode & CS_MODE_V9 || (MCInst_getNumOperands(MI) != 3) ||
(!MCOperand_isReg(MCInst_getOperand(MI, 0))) ||
(MCOperand_getReg(MCInst_getOperand(MI, 0)) != SP_FCC0))
}
SStream_concat0(O, "\tjmp ");
printMemOperand(MI, 1, O);
return true;
case Sparc_O7: // call $addr
SStream_concat0(O, "\tcall ");
printMemOperand(MI, 1, O);
return true;
}
}
case Sparc_V9FCMPS:
case Sparc_V9FCMPD:
case Sparc_V9FCMPQ:
case Sparc_V9FCMPES:
case Sparc_V9FCMPED:
case Sparc_V9FCMPEQ: {
if (Sparc_getFeatureBits(MI->csh->mode, Sparc_FeatureV9) || (MCInst_getNumOperands(MI) != 3) ||
(!MCOperand_isReg(MCInst_getOperand(MI, (0)))) ||
(MCOperand_getReg(MCInst_getOperand(MI, (0))) != Sparc_FCC0))
return false;
// if V8, skip printing %fcc0.
switch (MCInst_getOpcode(MI)) {
default:
case SP_V9FCMPS: SStream_concat0(O, "fcmps\t"); MCInst_setOpcodePub(MI, SPARC_INS_FCMPS); break;
case SP_V9FCMPD: SStream_concat0(O, "fcmpd\t"); MCInst_setOpcodePub(MI, SPARC_INS_FCMPD); break;
case SP_V9FCMPQ: SStream_concat0(O, "fcmpq\t"); MCInst_setOpcodePub(MI, SPARC_INS_FCMPQ); break;
case SP_V9FCMPES: SStream_concat0(O, "fcmpes\t"); MCInst_setOpcodePub(MI, SPARC_INS_FCMPES); break;
case SP_V9FCMPED: SStream_concat0(O, "fcmped\t"); MCInst_setOpcodePub(MI, SPARC_INS_FCMPED); break;
case SP_V9FCMPEQ: SStream_concat0(O, "fcmpeq\t"); MCInst_setOpcodePub(MI, SPARC_INS_FCMPEQ); break;
case Sparc_V9FCMPS:
SStream_concat0(O, "\tfcmps ");
break;
case Sparc_V9FCMPD:
SStream_concat0(O, "\tfcmpd ");
break;
case Sparc_V9FCMPQ:
SStream_concat0(O, "\tfcmpq ");
break;
case Sparc_V9FCMPES:
SStream_concat0(O, "\tfcmpes ");
break;
case Sparc_V9FCMPED:
SStream_concat0(O, "\tfcmped ");
break;
case Sparc_V9FCMPEQ:
SStream_concat0(O, "\tfcmpeq ");
break;
}
printOperand(MI, 1, O);
SStream_concat0(O, ", ");
@@ -160,289 +167,174 @@ static bool printSparcAliasInstr(MCInst *MI, SStream *O)
return true;
}
}
}
static void printOperand(MCInst *MI, int opNum, SStream *O)
{
int64_t Imm;
unsigned reg;
MCOperand *MO = MCInst_getOperand(MI, opNum);
Sparc_add_cs_detail_0(MI, Sparc_OP_GROUP_Operand, opNum);
MCOperand *MO = MCInst_getOperand(MI, (opNum));
if (MCOperand_isReg(MO)) {
reg = MCOperand_getReg(MO);
printRegName(O, reg);
reg = Sparc_map_register(reg);
if (MI->csh->detail_opt) {
if (MI->csh->doing_mem) {
if (MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.base)
MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.index = (uint8_t)reg;
unsigned Reg = MCOperand_getReg(MO);
if (Sparc_getFeatureBits(MI->csh->mode, Sparc_FeatureV9))
printRegNameAlt(O, Reg, Sparc_RegNamesStateReg);
else
MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.base = (uint8_t)reg;
} else {
MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].type = SPARC_OP_REG;
MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].reg = reg;
MI->flat_insn->detail->sparc.op_count++;
}
}
printRegName(O, Reg);
return;
}
if (MCOperand_isImm(MO)) {
Imm = (int)MCOperand_getImm(MO);
// Conditional branches displacements needs to be signextended to be
// able to jump backwards.
//
// Displacements are measured as the number of instructions forward or
// backward, so they need to be multiplied by 4
switch (MI->Opcode) {
case SP_CALL:
// Imm = SignExtend32(Imm, 30);
Imm += MI->address;
break;
// Branch on integer condition with prediction (BPcc)
// Branch on floating point condition with prediction (FBPfcc)
case SP_BPICC:
case SP_BPICCA:
case SP_BPICCANT:
case SP_BPICCNT:
case SP_BPXCC:
case SP_BPXCCA:
case SP_BPXCCANT:
case SP_BPXCCNT:
case SP_BPFCC:
case SP_BPFCCA:
case SP_BPFCCANT:
case SP_BPFCCNT:
Imm = SignExtend32(Imm, 19);
Imm = MI->address + Imm * 4;
break;
// Branch on integer condition (Bicc)
// Branch on floating point condition (FBfcc)
case SP_BA:
case SP_BCOND:
case SP_BCONDA:
case SP_FBCOND:
case SP_FBCONDA:
Imm = SignExtend32(Imm, 22);
Imm = MI->address + Imm * 4;
break;
// Branch on integer register with prediction (BPr)
case SP_BPGEZapn:
case SP_BPGEZapt:
case SP_BPGEZnapn:
case SP_BPGEZnapt:
case SP_BPGZapn:
case SP_BPGZapt:
case SP_BPGZnapn:
case SP_BPGZnapt:
case SP_BPLEZapn:
case SP_BPLEZapt:
case SP_BPLEZnapn:
case SP_BPLEZnapt:
case SP_BPLZapn:
case SP_BPLZapt:
case SP_BPLZnapn:
case SP_BPLZnapt:
case SP_BPNZapn:
case SP_BPNZapt:
case SP_BPNZnapn:
case SP_BPNZnapt:
case SP_BPZapn:
case SP_BPZapt:
case SP_BPZnapn:
case SP_BPZnapt:
Imm = SignExtend32(Imm, 16);
Imm = MI->address + Imm * 4;
break;
}
printInt64(O, Imm);
if (MI->csh->detail_opt) {
if (MI->csh->doing_mem) {
MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.disp = Imm;
} else {
MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].type = SPARC_OP_IMM;
MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].imm = Imm;
MI->flat_insn->detail->sparc.op_count++;
}
}
}
return;
}
static void printMemOperand(MCInst *MI, int opNum, SStream *O, const char *Modifier)
{
MCOperand *MO;
set_mem_access(MI, true);
printOperand(MI, opNum, O);
// If this is an ADD operand, emit it like normal operands.
if (Modifier && !strcmp(Modifier, "arith")) {
SStream_concat0(O, ", ");
printOperand(MI, opNum + 1, O);
set_mem_access(MI, false);
return;
}
MO = MCInst_getOperand(MI, opNum + 1);
if (MCOperand_isReg(MO) && (MCOperand_getReg(MO) == SP_G0)) {
set_mem_access(MI, false);
return; // don't print "+%g0"
}
if (MCOperand_isImm(MO) && (MCOperand_getImm(MO) == 0)) {
set_mem_access(MI, false);
return; // don't print "+0"
}
SStream_concat0(O, "+"); // qq
printOperand(MI, opNum + 1, O);
set_mem_access(MI, false);
}
static void printCCOperand(MCInst *MI, int opNum, SStream *O)
{
int CC = (int)MCOperand_getImm(MCInst_getOperand(MI, opNum)) + 256;
switch (MCInst_getOpcode(MI)) {
default: break;
case SP_FBCOND:
case SP_FBCONDA:
case SP_BPFCC:
case SP_BPFCCA:
case SP_BPFCCNT:
case SP_BPFCCANT:
case SP_MOVFCCrr: case SP_V9MOVFCCrr:
case SP_MOVFCCri: case SP_V9MOVFCCri:
case SP_FMOVS_FCC: case SP_V9FMOVS_FCC:
case SP_FMOVD_FCC: case SP_V9FMOVD_FCC:
case SP_FMOVQ_FCC: case SP_V9FMOVQ_FCC:
default:
printInt32(O, (int)MCOperand_getImm(MO));
return;
case Sparc_TICCri: // Fall through
case Sparc_TICCrr: // Fall through
case Sparc_TRAPri: // Fall through
case Sparc_TRAPrr: // Fall through
case Sparc_TXCCri: // Fall through
case Sparc_TXCCrr: // Fall through
// Only seven-bit values up to 127.
printInt8(O, ((int)MCOperand_getImm(MO) & 0x7f));
return;
}
}
CS_ASSERT(MCOperand_isExpr(MO) &&
"Unknown operand kind in printOperand");
}
void printMemOperand(MCInst *MI, int opNum, SStream *O)
{
Sparc_add_cs_detail_0(MI, Sparc_OP_GROUP_MemOperand, opNum);
MCOperand *Op1 = MCInst_getOperand(MI, (opNum));
MCOperand *Op2 = MCInst_getOperand(MI, (opNum + 1));
bool PrintedFirstOperand = false;
if (MCOperand_isReg(Op1) && MCOperand_getReg(Op1) != Sparc_G0) {
printOperand(MI, opNum, O);
PrintedFirstOperand = true;
}
// Skip the second operand iff it adds nothing (literal 0 or %g0) and we've
// already printed the first one
const bool SkipSecondOperand =
PrintedFirstOperand &&
((MCOperand_isReg(Op2) && MCOperand_getReg(Op2) == Sparc_G0) ||
(MCOperand_isImm(Op2) && MCOperand_getImm(Op2) == 0));
if (!SkipSecondOperand) {
if (PrintedFirstOperand)
SStream_concat0(O, "+");
printOperand(MI, opNum + 1, O);
}
}
void printCCOperand(MCInst *MI, int opNum, SStream *O)
{
Sparc_add_cs_detail_0(MI, Sparc_OP_GROUP_CCOperand, opNum);
int CC = (int)MCOperand_getImm(MCInst_getOperand(MI, (opNum)));
switch (MCInst_getOpcode(MI)) {
default:
break;
case Sparc_FBCOND:
case Sparc_FBCONDA:
case Sparc_FBCOND_V9:
case Sparc_FBCONDA_V9:
case Sparc_BPFCC:
case Sparc_BPFCCA:
case Sparc_BPFCCNT:
case Sparc_BPFCCANT:
case Sparc_MOVFCCrr:
case Sparc_V9MOVFCCrr:
case Sparc_MOVFCCri:
case Sparc_V9MOVFCCri:
case Sparc_FMOVS_FCC:
case Sparc_V9FMOVS_FCC:
case Sparc_FMOVD_FCC:
case Sparc_V9FMOVD_FCC:
case Sparc_FMOVQ_FCC:
case Sparc_V9FMOVQ_FCC:
// Make sure CC is a fp conditional flag.
CC = (CC < 16+256) ? (CC + 16) : CC;
CC = (CC < SPARC_CC_FCC_BEGIN) ? (CC + SPARC_CC_FCC_BEGIN) : CC;
break;
case Sparc_CBCOND:
case Sparc_CBCONDA:
// Make sure CC is a cp conditional flag.
CC = (CC < SPARC_CC_CPCC_BEGIN) ? (CC + SPARC_CC_CPCC_BEGIN) : CC;
break;
case Sparc_BPR:
case Sparc_BPRA:
case Sparc_BPRNT:
case Sparc_BPRANT:
case Sparc_MOVRri:
case Sparc_MOVRrr:
case Sparc_FMOVRS:
case Sparc_FMOVRD:
case Sparc_FMOVRQ:
// Make sure CC is a register conditional flag.
CC = (CC < SPARC_CC_REG_BEGIN) ? (CC + SPARC_CC_REG_BEGIN) : CC;
break;
}
SStream_concat0(O, SPARCCondCodeToString((sparc_cc)CC));
if (MI->csh->detail_opt)
MI->flat_insn->detail->sparc.cc = (sparc_cc)CC; // NOLINT(clang-analyzer-optin.core.EnumCastOutOfRange)
}
static bool printGetPCX(MCInst *MI, unsigned opNum, SStream *O)
bool printGetPCX(MCInst *MI, unsigned opNum, SStream *O)
{
printf("FIXME: Implement SparcInstPrinter::printGetPCX.");
return true;
}
#define PRINT_ALIAS_INSTR
#include "SparcGenAsmWriter.inc"
void Sparc_printInst(MCInst *MI, SStream *O, void *Info)
void printMembarTag(MCInst *MI, int opNum, SStream *O)
{
char *mnem, *p;
char instr[64]; // Sparc has no instruction this long
Sparc_add_cs_detail_0(MI, Sparc_OP_GROUP_MembarTag, opNum);
static const char *const TagNames[] = { "#LoadLoad", "#StoreLoad",
"#LoadStore", "#StoreStore",
"#Lookaside", "#MemIssue",
"#Sync" };
mnem = printAliasInstr(MI, O, Info);
if (mnem) {
// fixup instruction id due to the change in alias instruction
unsigned cpy_len = sizeof(instr) - 1 < strlen(mnem) ? sizeof(instr) - 1 : strlen(mnem);
memcpy(instr, mnem, cpy_len);
instr[cpy_len] = '\0';
// does this contains hint with a coma?
p = strchr(instr, ',');
if (p)
*p = '\0'; // now instr only has instruction mnemonic
MCInst_setOpcodePub(MI, Sparc_map_insn(instr));
switch(MCInst_getOpcode(MI)) {
case SP_BCOND:
case SP_BCONDA:
case SP_BPICCANT:
case SP_BPICCNT:
case SP_BPXCCANT:
case SP_BPXCCNT:
case SP_TXCCri:
case SP_TXCCrr:
if (MI->csh->detail_opt) {
// skip 'b', 't'
MI->flat_insn->detail->sparc.cc = Sparc_map_ICC(instr + 1);
MI->flat_insn->detail->sparc.hint = Sparc_map_hint(mnem);
unsigned Imm = MCOperand_getImm(MCInst_getOperand(MI, (opNum)));
if (Imm > 127) {
printUInt32(O, Imm);
return;
}
break;
case SP_BPFCCANT:
case SP_BPFCCNT:
if (MI->csh->detail_opt) {
// skip 'fb'
MI->flat_insn->detail->sparc.cc = Sparc_map_FCC(instr + 2);
MI->flat_insn->detail->sparc.hint = Sparc_map_hint(mnem);
bool First = true;
for (unsigned i = 0; i < sizeof(TagNames); i++) {
if (Imm & (1ull << i)) {
SStream_concat(O, "%s", (First ? "" : " | "));
SStream_concat0(O, TagNames[i]);
First = false;
}
break;
case SP_FMOVD_ICC:
case SP_FMOVD_XCC:
case SP_FMOVQ_ICC:
case SP_FMOVQ_XCC:
case SP_FMOVS_ICC:
case SP_FMOVS_XCC:
if (MI->csh->detail_opt) {
// skip 'fmovd', 'fmovq', 'fmovs'
MI->flat_insn->detail->sparc.cc = Sparc_map_ICC(instr + 5);
MI->flat_insn->detail->sparc.hint = Sparc_map_hint(mnem);
}
break;
case SP_MOVICCri:
case SP_MOVICCrr:
case SP_MOVXCCri:
case SP_MOVXCCrr:
if (MI->csh->detail_opt) {
// skip 'mov'
MI->flat_insn->detail->sparc.cc = Sparc_map_ICC(instr + 3);
MI->flat_insn->detail->sparc.hint = Sparc_map_hint(mnem);
}
break;
case SP_V9FMOVD_FCC:
case SP_V9FMOVQ_FCC:
case SP_V9FMOVS_FCC:
if (MI->csh->detail_opt) {
// skip 'fmovd', 'fmovq', 'fmovs'
MI->flat_insn->detail->sparc.cc = Sparc_map_FCC(instr + 5);
MI->flat_insn->detail->sparc.hint = Sparc_map_hint(mnem);
}
break;
case SP_V9MOVFCCri:
case SP_V9MOVFCCrr:
if (MI->csh->detail_opt) {
// skip 'mov'
MI->flat_insn->detail->sparc.cc = Sparc_map_FCC(instr + 3);
MI->flat_insn->detail->sparc.hint = Sparc_map_hint(mnem);
}
break;
default:
break;
}
cs_mem_free(mnem);
} else {
if (!printSparcAliasInstr(MI, O))
printInstruction(MI, O, NULL);
}
}
void Sparc_addReg(MCInst *MI, int reg)
#define GET_ASITAG_IMPL
#include "SparcGenSystemOperands.inc"
void printASITag(MCInst *MI, int opNum, SStream *O)
{
if (MI->csh->detail_opt) {
MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].type = SPARC_OP_REG;
MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].reg = reg;
MI->flat_insn->detail->sparc.op_count++;
}
Sparc_add_cs_detail_0(MI, Sparc_OP_GROUP_ASITag, opNum);
unsigned Imm = MCOperand_getImm(MCInst_getOperand(MI, (opNum)));
const Sparc_ASITag_ASITag *ASITag = Sparc_ASITag_lookupASITagByEncoding(Imm);
if (Sparc_getFeatureBits(MI->csh->mode, Sparc_FeatureV9) && ASITag) {
SStream_concat1(O, '#');
SStream_concat0(O, ASITag->Name);
} else
printUInt32(O, Imm);
}
#endif
void Sparc_LLVM_printInst(MCInst *MI, uint64_t Address, const char *Annot,
SStream *O)
{
printInst(MI, Address, O);
}
const char *Sparc_LLVM_getRegisterName(unsigned RegNo, unsigned AltIdx)
{
return getRegisterName(RegNo, AltIdx);
}

52
external/capstone/arch/Sparc/SparcInstPrinter.h vendored
View File

@@ -1,17 +1,49 @@
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2023 */
/* Automatically translated source file from LLVM. */
#ifndef CS_SPARCINSTPRINTER_H
#define CS_SPARCINSTPRINTER_H
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
#include "../../MCInst.h"
#include "../../MCRegisterInfo.h"
#include "../../SStream.h"
/* Only small edits allowed. */
/* For multiple similar edits, please create a Patch for the translator. */
void Sparc_printInst(MCInst *MI, SStream *O, void *Info);
/* Capstone's C++ file translator: */
/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
void Sparc_post_printer(csh ud, cs_insn *insn, SStream *insn_asm, MCInst *mci);
//===-- SparcInstPrinter.h - Convert Sparc MCInst to assembly syntax ------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This class prints an Sparc MCInst to a .s file.
//
//===----------------------------------------------------------------------===//
void Sparc_addReg(MCInst *MI, int reg);
#ifndef LLVM_LIB_TARGET_SPARC_MCTARGETDESC_SPARCINSTPRINTER_H
#define LLVM_LIB_TARGET_SPARC_MCTARGETDESC_SPARCINSTPRINTER_H
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <capstone/platform.h>
#include "SparcMCTargetDesc.h"
#define CONCAT(a, b) CONCAT_(a, b)
#define CONCAT_(a, b) a##_##b
bool printSparcAliasInstr(MCInst *MI, SStream *OS);
void printMemOperand(MCInst *MI, int opNum, SStream *OS);
void printCCOperand(MCInst *MI, int opNum, SStream *OS);
bool printGetPCX(MCInst *MI, unsigned OpNo, SStream *OS);
void printMembarTag(MCInst *MI, int opNum, SStream *O);
void printASITag(MCInst *MI, int opNum, SStream *O);
;
// end namespace llvm
#endif

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