Fuck git

external/capstone/arch/ARC/ARCDisassembler.c

@@ -0,0 +1,473 @@
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically translated source file from LLVM. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Only small edits allowed. */
+/* For multiple similar edits, please create a Patch for the translator. */
+
+/* Capstone's C++ file translator: */
+/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
+
+//===- ARCDisassembler.cpp - Disassembler for ARC ---------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+///
+/// \file
+/// This file is part of the ARC Disassembler.
+///
+//===----------------------------------------------------------------------===//
+
+#ifdef CAPSTONE_HAS_ARC
+
+#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
+#include <capstone/platform.h>
+
+#include "../../MCInst.h"
+#include "../../SStream.h"
+#include "../../MCDisassembler.h"
+#include "../../MCFixedLenDisassembler.h"
+#include "../../MathExtras.h"
+#include "../../utils.h"
+#define CONCAT(a, b) CONCAT_(a, b)
+#define CONCAT_(a, b) a##_##b
+
+#define DEBUG_TYPE "arc-disassembler"
+
+/// A disassembler class for ARC.
+static DecodeStatus getInstruction(MCInst *Instr, uint64_t *Size, const uint8_t *Bytes,
+			    size_t BytesLen, uint64_t Address,
+			    SStream *CStream);
+
+// end anonymous namespace
+
+static bool readInstruction32(const uint8_t *Bytes, size_t BytesLen,
+			      uint64_t Address, uint64_t *Size, uint32_t *Insn)
+{
+	*Size = 4;
+	// Read 2 16-bit values, but swap hi/lo parts.
+	*Insn = (Bytes[0] << 16) | (Bytes[1] << 24) | (Bytes[2] << 0) |
+	       (Bytes[3] << 8);
+	return true;
+}
+
+static bool readInstruction64(const uint8_t *Bytes, size_t BytesLen,
+			      uint64_t Address, uint64_t *Size, uint64_t *Insn)
+{
+	*Size = 8;
+	*Insn = ((uint64_t)Bytes[0] << 16) | ((uint64_t)Bytes[1] << 24) |
+	       ((uint64_t)Bytes[2] << 0) | ((uint64_t)Bytes[3] << 8) |
+	       ((uint64_t)Bytes[4] << 48) | ((uint64_t)Bytes[5] << 56) |
+	       ((uint64_t)Bytes[6] << 32) | ((uint64_t)Bytes[7] << 40);
+	return true;
+}
+
+static bool readInstruction48(const uint8_t *Bytes, size_t BytesLen,
+			      uint64_t Address, uint64_t *Size, uint64_t *Insn)
+{
+	*Size = 6;
+	*Insn = ((uint64_t)Bytes[0] << 0) | ((uint64_t)Bytes[1] << 8) |
+	       ((uint64_t)Bytes[2] << 32) | ((uint64_t)Bytes[3] << 40) |
+	       ((uint64_t)Bytes[4] << 16) | ((uint64_t)Bytes[5] << 24);
+	return true;
+}
+
+static bool readInstruction16(const uint8_t *Bytes, size_t BytesLen,
+			      uint64_t Address, uint64_t *Size, uint32_t *Insn)
+{
+	*Size = 2;
+	*Insn = (Bytes[0] << 0) | (Bytes[1] << 8);
+	return true;
+}
+
+#define DECLARE_DecodeSignedOperand(B) \
+	static DecodeStatus CONCAT(DecodeSignedOperand, B)( \
+		MCInst * Inst, unsigned InsnS, uint64_t Address, \
+		const void *Decoder);
+DECLARE_DecodeSignedOperand(11);
+DECLARE_DecodeSignedOperand(9);
+DECLARE_DecodeSignedOperand(10);
+DECLARE_DecodeSignedOperand(12);
+
+#define DECLARE_DecodeFromCyclicRange(B) \
+	static DecodeStatus CONCAT(DecodeFromCyclicRange, B)( \
+		MCInst * Inst, unsigned InsnS, uint64_t Address, \
+		const void *Decoder);
+DECLARE_DecodeFromCyclicRange(3);
+
+#define DECLARE_DecodeBranchTargetS(B) \
+	static DecodeStatus CONCAT(DecodeBranchTargetS, \
+				   B)(MCInst * Inst, unsigned InsnS, \
+				      uint64_t Address, const void *Decoder);
+DECLARE_DecodeBranchTargetS(8);
+DECLARE_DecodeBranchTargetS(10);
+DECLARE_DecodeBranchTargetS(7);
+DECLARE_DecodeBranchTargetS(13);
+DECLARE_DecodeBranchTargetS(21);
+DECLARE_DecodeBranchTargetS(25);
+DECLARE_DecodeBranchTargetS(9);
+
+static DecodeStatus DecodeMEMrs9(MCInst *, unsigned, uint64_t,
+				 const void *);
+
+static DecodeStatus DecodeLdLImmInstruction(MCInst *, uint64_t, uint64_t,
+					    const void *);
+
+static DecodeStatus DecodeStLImmInstruction(MCInst *, uint64_t, uint64_t,
+					    const void *);
+
+static DecodeStatus DecodeLdRLImmInstruction(MCInst *, uint64_t, uint64_t,
+					     const void *);
+
+static DecodeStatus DecodeSOPwithRS12(MCInst *, uint64_t, uint64_t,
+				      const void *);
+
+static DecodeStatus DecodeSOPwithRU6(MCInst *, uint64_t, uint64_t,
+				     const void *);
+
+static DecodeStatus DecodeCCRU6Instruction(MCInst *, uint64_t, uint64_t,
+					   const void *);
+
+static DecodeStatus DecodeMoveHRegInstruction(MCInst *Inst, uint64_t, uint64_t,
+					      const void *);
+
+#define GET_REGINFO_ENUM
+#include "ARCGenRegisterInfo.inc"
+
+static const uint16_t GPR32DecoderTable[] = {
+	ARC_R0,	 ARC_R1,    ARC_R2,  ARC_R3,   ARC_R4,	ARC_R5,	 ARC_R6,
+	ARC_R7,	 ARC_R8,    ARC_R9,  ARC_R10,  ARC_R11, ARC_R12, ARC_R13,
+	ARC_R14, ARC_R15,   ARC_R16, ARC_R17,  ARC_R18, ARC_R19, ARC_R20,
+	ARC_R21, ARC_R22,   ARC_R23, ARC_R24,  ARC_R25, ARC_GP,	 ARC_FP,
+	ARC_SP,	 ARC_ILINK, ARC_R30, ARC_BLINK
+};
+
+static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, unsigned RegNo,
+					     uint64_t Address,
+					     const void *Decoder)
+{
+	if (RegNo >= 32) {
+		;
+		return MCDisassembler_Fail;
+	}
+
+	unsigned Reg = GPR32DecoderTable[RegNo];
+	MCOperand_CreateReg0(Inst, (Reg));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeGBR32ShortRegister(MCInst *Inst, unsigned RegNo,
+					     uint64_t Address,
+					     const void *Decoder)
+{
+	// Enumerates registers from ranges [r0-r3],[r12-r15].
+	if (RegNo > 3)
+		RegNo += 8; // 4 for r12, etc...
+
+	return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
+}
+
+#include "ARCGenDisassemblerTables.inc"
+
+static unsigned decodeCField(unsigned Insn)
+{
+	return fieldFromInstruction_4(Insn, 6, 6);
+}
+
+static unsigned decodeBField(unsigned Insn)
+{
+	return (fieldFromInstruction_4(Insn, 12, 3) << 3) |
+	       fieldFromInstruction_4(Insn, 24, 3);
+}
+
+static unsigned decodeAField(unsigned Insn)
+{
+	return fieldFromInstruction_4(Insn, 0, 6);
+}
+
+static DecodeStatus DecodeMEMrs9(MCInst *Inst, unsigned Insn, uint64_t Address,
+				 const void *Decoder)
+{
+	// We have the 9-bit immediate in the low bits, 6-bit register in high bits.
+	unsigned S9 = Insn & 0x1ff;
+	unsigned R = (Insn & (0x7fff & ~0x1ff)) >> 9;
+	if (DecodeGPR32RegisterClass(Inst, R, Address, Decoder) == MCDisassembler_Fail) {
+		return MCDisassembler_Fail;
+	}
+	MCOperand_CreateImm0(Inst, (SignExtend32((S9), 9)));
+	return MCDisassembler_Success;
+}
+
+static void DecodeSymbolicOperandOff(MCInst *Inst, uint64_t Address,
+				     uint64_t Offset, const void *Decoder)
+{
+	uint64_t NextAddress = Address + Offset;
+
+	MCOperand_CreateImm0(Inst, (NextAddress));
+}
+
+#define DEFINE_DecodeBranchTargetS(B) \
+	static DecodeStatus CONCAT(DecodeBranchTargetS, \
+				   B)(MCInst * Inst, unsigned InsnS, \
+				      uint64_t Address, const void *Decoder) \
+	{ \
+		CS_ASSERT(B > 0 && "field is empty"); \
+		DecodeSymbolicOperandOff(Inst, Address, \
+					 SignExtend32((InsnS), B), Decoder); \
+		return MCDisassembler_Success; \
+	}
+DEFINE_DecodeBranchTargetS(8);
+DEFINE_DecodeBranchTargetS(10);
+DEFINE_DecodeBranchTargetS(7);
+DEFINE_DecodeBranchTargetS(13);
+DEFINE_DecodeBranchTargetS(21);
+DEFINE_DecodeBranchTargetS(25);
+DEFINE_DecodeBranchTargetS(9);
+
+#define DEFINE_DecodeSignedOperand(B) \
+	static DecodeStatus CONCAT(DecodeSignedOperand, B)( \
+		MCInst * Inst, unsigned InsnS, uint64_t Address, \
+		const void * Decoder) \
+	{ \
+		CS_ASSERT(B > 0 && "field is empty"); \
+		MCOperand_CreateImm0( \
+			Inst, SignExtend32(maskTrailingOnes32(B) & \
+						    InsnS, B) \
+					    ); \
+		return MCDisassembler_Success; \
+	}
+DEFINE_DecodeSignedOperand(11);
+DEFINE_DecodeSignedOperand(9);
+DEFINE_DecodeSignedOperand(10);
+DEFINE_DecodeSignedOperand(12);
+
+#define DEFINE_DecodeFromCyclicRange(B) \
+	static DecodeStatus CONCAT(DecodeFromCyclicRange, B)( \
+		MCInst * Inst, unsigned InsnS, uint64_t Address, \
+		const void * Decoder) \
+	{ \
+		CS_ASSERT(B > 0 && "field is empty"); \
+		const unsigned max = (1u << B) - 1; \
+		MCOperand_CreateImm0(Inst, (InsnS < max ? (int)(InsnS) : -1)); \
+		return MCDisassembler_Success; \
+	}
+DEFINE_DecodeFromCyclicRange(3);
+
+static DecodeStatus DecodeStLImmInstruction(MCInst *Inst, uint64_t Insn,
+					    uint64_t Address,
+					    const void *Decoder)
+{
+	unsigned SrcC, DstB, LImm;
+	DstB = decodeBField(Insn);
+	if (DstB != 62) {
+		return MCDisassembler_Fail;
+	}
+	SrcC = decodeCField(Insn);
+	if (DecodeGPR32RegisterClass(Inst, SrcC, Address, Decoder) == MCDisassembler_Fail) {
+		return MCDisassembler_Fail;
+	}
+	LImm = (Insn >> 32);
+	MCOperand_CreateImm0(Inst, (LImm));
+	MCOperand_CreateImm0(Inst, (0));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeLdLImmInstruction(MCInst *Inst, uint64_t Insn,
+					    uint64_t Address,
+					    const void *Decoder)
+{
+	unsigned DstA, SrcB, LImm;
+	;
+	SrcB = decodeBField(Insn);
+	if (SrcB != 62) {
+		;
+		return MCDisassembler_Fail;
+	}
+	DstA = decodeAField(Insn);
+	if (DecodeGPR32RegisterClass(Inst, DstA, Address, Decoder) == MCDisassembler_Fail) {
+		return MCDisassembler_Fail;
+	}
+	LImm = (Insn >> 32);
+	MCOperand_CreateImm0(Inst, (LImm));
+	MCOperand_CreateImm0(Inst, (0));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeLdRLImmInstruction(MCInst *Inst, uint64_t Insn,
+					     uint64_t Address,
+					     const void *Decoder)
+{
+	unsigned DstA, SrcB;
+	;
+	DstA = decodeAField(Insn);
+	if (DecodeGPR32RegisterClass(Inst, DstA, Address, Decoder) == MCDisassembler_Fail) {
+		return MCDisassembler_Fail;
+	}
+	SrcB = decodeBField(Insn);
+	if (DecodeGPR32RegisterClass(Inst, SrcB, Address, Decoder) == MCDisassembler_Fail) {
+		return MCDisassembler_Fail;
+	}
+	if (decodeCField(Insn) != 62) {
+		;
+		return MCDisassembler_Fail;
+	}
+	MCOperand_CreateImm0(Inst, ((uint32_t)(Insn >> 32)));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeRegisterOrImm(MCInst *Inst, uint64_t Address, 
+						const void *Decoder, uint64_t RegNum, 
+						uint64_t Value) 
+{
+	if (30 == RegNum) {
+		MCOperand_CreateImm0(Inst, (Value));
+		return MCDisassembler_Success;
+	}
+	return DecodeGPR32RegisterClass(Inst, RegNum, Address, Decoder);
+}
+
+
+static DecodeStatus DecodeMoveHRegInstruction(MCInst *Inst, uint64_t Insn,
+					      uint64_t Address,
+					      const void *Decoder)
+{
+	;
+
+	uint64_t H = fieldFromInstruction_8(Insn, 5, 3) |
+		  (fieldFromInstruction_8(Insn, 0, 2) << 3);
+	uint64_t G = fieldFromInstruction_8(Insn, 8, 3) |
+		  (fieldFromInstruction_8(Insn, 3, 2) << 3);
+
+	if (MCDisassembler_Success != DecodeRegisterOrImm(Inst, Address, 
+									Decoder, G, 0))
+		return MCDisassembler_Fail;
+
+	return DecodeRegisterOrImm(Inst, Address, Decoder, H, Insn >> 16u);
+}
+
+static DecodeStatus DecodeCCRU6Instruction(MCInst *Inst, uint64_t Insn,
+					   uint64_t Address,
+					   const void *Decoder)
+{
+	unsigned DstB;
+	;
+	DstB = decodeBField(Insn);
+	if (DecodeGPR32RegisterClass(Inst, DstB, Address, Decoder) == MCDisassembler_Fail) {
+		return MCDisassembler_Fail;
+	}
+
+	uint64_t U6Field = fieldFromInstruction_8(Insn, 6, 6);
+	MCOperand_CreateImm0(Inst, (U6Field));
+	uint64_t CCField = fieldFromInstruction_8(Insn, 0, 4);
+	MCOperand_CreateImm0(Inst, (CCField));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeSOPwithRU6(MCInst *Inst, uint64_t Insn,
+				     uint64_t Address, const void *Decoder)
+{
+	unsigned DstB = decodeBField(Insn);
+	if (DecodeGPR32RegisterClass(Inst, DstB, Address, Decoder) == MCDisassembler_Fail) {
+		return MCDisassembler_Fail;
+	}
+
+	uint64_t U6 = fieldFromInstruction_8(Insn, 6, 6);
+	MCOperand_CreateImm0(Inst, (U6));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeSOPwithRS12(MCInst *Inst, uint64_t Insn,
+				      uint64_t Address, const void *Decoder)
+{
+	unsigned DstB = decodeBField(Insn);
+	if (DecodeGPR32RegisterClass(Inst, DstB, Address, Decoder) == MCDisassembler_Fail) {
+		return MCDisassembler_Fail;
+	}
+
+	uint64_t Lower = fieldFromInstruction_8(Insn, 6, 6);
+	uint64_t Upper = fieldFromInstruction_8(Insn, 0, 5);
+	uint64_t Sign = fieldFromInstruction_8(Insn, 5, 1) ? -1 : 1;
+	uint64_t Result = Sign * ((Upper << 6) + Lower);
+	MCOperand_CreateImm0(Inst, (Result));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus getInstruction(MCInst *Instr, uint64_t *Size, const uint8_t *Bytes,
+			    size_t BytesLen, uint64_t Address, SStream *cStream)
+{
+	DecodeStatus Result;
+	if (BytesLen < 2) {
+		*Size = 0;
+		return MCDisassembler_Fail;
+	}
+	uint8_t DecodeByte = (Bytes[1] & 0xF7) >> 3;
+	// 0x00 -> 0x07 are 32-bit instructions.
+	// 0x08 -> 0x1F are 16-bit instructions.
+	if (DecodeByte < 0x08) {
+		// 32-bit instruction.
+		if (BytesLen < 4) {
+			// Did we decode garbage?
+			*Size = 0;
+			return MCDisassembler_Fail;
+		}
+		if (BytesLen >= 8) {
+			// Attempt to decode 64-bit instruction.
+			uint64_t Insn64;
+			if (!readInstruction64(Bytes, BytesLen, Address, Size, &Insn64))
+				return MCDisassembler_Fail;
+			Result = decodeInstruction_8(DecoderTable64, Instr,
+						   Insn64, Address, NULL);
+			if (MCDisassembler_Success == Result) {
+				;
+				return Result;
+			};
+		}
+		uint32_t Insn32;
+		if (!readInstruction32(Bytes, BytesLen, Address, Size, &Insn32)) {
+			return MCDisassembler_Fail;
+		}
+		// Calling the auto-generated decoder function.
+		return decodeInstruction_4(DecoderTable32, Instr, Insn32,
+					   Address, NULL);
+	} else {
+		if (BytesLen >= 6) {
+			// Attempt to treat as instr. with limm data.
+			uint64_t Insn48;
+			if (!readInstruction48(Bytes, BytesLen, Address, Size, &Insn48))
+				return MCDisassembler_Fail;
+			Result = decodeInstruction_8(DecoderTable48, Instr,
+						   Insn48, Address, NULL);
+			if (MCDisassembler_Success == Result) {
+				;
+				return Result;
+			};
+		}
+
+		uint32_t Insn16;
+		if (!readInstruction16(Bytes, BytesLen, Address, Size, &Insn16))
+			return MCDisassembler_Fail;
+
+		// Calling the auto-generated decoder function.
+		return decodeInstruction_2(DecoderTable16, Instr, Insn16,
+					   Address, NULL);
+	}
+}
+
+DecodeStatus ARC_LLVM_getInstruction(MCInst *MI, uint64_t *Size,
+					   const uint8_t *Bytes,
+					   size_t BytesLen, uint64_t Address,
+					   SStream *CS)
+{
+	return getInstruction(MI, Size, Bytes, BytesLen, Address, CS);
+}
+
+#endif

external/capstone/arch/ARC/ARCGenCSInsnEnum.inc

@@ -0,0 +1,204 @@
+/* Capstone Disassembly Engine, https://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2024 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+  ARC_INS_INVALID,
+  ARC_INS_h,
+  ARC_INS_PBR,
+  ARC_INS_ERROR_FLS,
+  ARC_INS_ERROR_FFS,
+  ARC_INS_PLDFI,
+  ARC_INS_STB_FAR,
+  ARC_INS_STH_FAR,
+  ARC_INS_ST_FAR,
+  ARC_INS_ADC,
+  ARC_INS_ADC_F,
+  ARC_INS_ADD_S,
+  ARC_INS_ADD,
+  ARC_INS_ADD_F,
+  ARC_INS_AND,
+  ARC_INS_AND_F,
+  ARC_INS_ASL_S,
+  ARC_INS_ASL,
+  ARC_INS_ASL_F,
+  ARC_INS_ASR_S,
+  ARC_INS_ASR,
+  ARC_INS_ASR_F,
+  ARC_INS_BCLR_S,
+  ARC_INS_BEQ_S,
+  ARC_INS_BGE_S,
+  ARC_INS_BGT_S,
+  ARC_INS_BHI_S,
+  ARC_INS_BHS_S,
+  ARC_INS_BL,
+  ARC_INS_BLE_S,
+  ARC_INS_BLO_S,
+  ARC_INS_BLS_S,
+  ARC_INS_BLT_S,
+  ARC_INS_BL_S,
+  ARC_INS_BMSK_S,
+  ARC_INS_BNE_S,
+  ARC_INS_B,
+  ARC_INS_BREQ_S,
+  ARC_INS_BRNE_S,
+  ARC_INS_BR,
+  ARC_INS_BSET_S,
+  ARC_INS_BTST_S,
+  ARC_INS_B_S,
+  ARC_INS_CMP_S,
+  ARC_INS_CMP,
+  ARC_INS_LD_S,
+  ARC_INS_MOV_S,
+  ARC_INS_EI_S,
+  ARC_INS_ENTER_S,
+  ARC_INS_FFS_F,
+  ARC_INS_FFS,
+  ARC_INS_FLS_F,
+  ARC_INS_FLS,
+  ARC_INS_ABS_S,
+  ARC_INS_ADD1_S,
+  ARC_INS_ADD2_S,
+  ARC_INS_ADD3_S,
+  ARC_INS_AND_S,
+  ARC_INS_BIC_S,
+  ARC_INS_BRK_S,
+  ARC_INS_EXTB_S,
+  ARC_INS_EXTH_S,
+  ARC_INS_JEQ_S,
+  ARC_INS_JL_S,
+  ARC_INS_JL_S_D,
+  ARC_INS_JNE_S,
+  ARC_INS_J_S,
+  ARC_INS_J_S_D,
+  ARC_INS_LSR_S,
+  ARC_INS_MPYUW_S,
+  ARC_INS_MPYW_S,
+  ARC_INS_MPY_S,
+  ARC_INS_NEG_S,
+  ARC_INS_NOP_S,
+  ARC_INS_NOT_S,
+  ARC_INS_OR_S,
+  ARC_INS_SEXB_S,
+  ARC_INS_SEXH_S,
+  ARC_INS_SUB_S,
+  ARC_INS_SUB_S_NE,
+  ARC_INS_SWI_S,
+  ARC_INS_TRAP_S,
+  ARC_INS_TST_S,
+  ARC_INS_UNIMP_S,
+  ARC_INS_XOR_S,
+  ARC_INS_LDB_S,
+  ARC_INS_LDH_S,
+  ARC_INS_J,
+  ARC_INS_JL,
+  ARC_INS_JLI_S,
+  ARC_INS_LDB_AB,
+  ARC_INS_LDB_AW,
+  ARC_INS_LDB_DI_AB,
+  ARC_INS_LDB_DI_AW,
+  ARC_INS_LDB_DI,
+  ARC_INS_LDB_X_AB,
+  ARC_INS_LDB_X_AW,
+  ARC_INS_LDB_X_DI_AB,
+  ARC_INS_LDB_X_DI_AW,
+  ARC_INS_LDB_X_DI,
+  ARC_INS_LDB_X,
+  ARC_INS_LDB,
+  ARC_INS_LDH_AB,
+  ARC_INS_LDH_AW,
+  ARC_INS_LDH_DI_AB,
+  ARC_INS_LDH_DI_AW,
+  ARC_INS_LDH_DI,
+  ARC_INS_LDH_S_X,
+  ARC_INS_LDH_X_AB,
+  ARC_INS_LDH_X_AW,
+  ARC_INS_LDH_X_DI_AB,
+  ARC_INS_LDH_X_DI_AW,
+  ARC_INS_LDH_X_DI,
+  ARC_INS_LDH_X,
+  ARC_INS_LDH,
+  ARC_INS_LDI_S,
+  ARC_INS_LD_AB,
+  ARC_INS_LD_AW,
+  ARC_INS_LD_DI_AB,
+  ARC_INS_LD_DI_AW,
+  ARC_INS_LD_DI,
+  ARC_INS_LD_S_AS,
+  ARC_INS_LD,
+  ARC_INS_LEAVE_S,
+  ARC_INS_LR,
+  ARC_INS_LSR,
+  ARC_INS_LSR_F,
+  ARC_INS_MAX,
+  ARC_INS_MAX_F,
+  ARC_INS_MIN,
+  ARC_INS_MIN_F,
+  ARC_INS_MOV_S_NE,
+  ARC_INS_MOV,
+  ARC_INS_MOV_F,
+  ARC_INS_MPYMU,
+  ARC_INS_MPYMU_F,
+  ARC_INS_MPYM,
+  ARC_INS_MPYM_F,
+  ARC_INS_MPY,
+  ARC_INS_MPY_F,
+  ARC_INS_NORMH_F,
+  ARC_INS_NORMH,
+  ARC_INS_NORM_F,
+  ARC_INS_NORM,
+  ARC_INS_OR,
+  ARC_INS_OR_F,
+  ARC_INS_POP_S,
+  ARC_INS_PUSH_S,
+  ARC_INS_ROR,
+  ARC_INS_ROR_F,
+  ARC_INS_RSUB,
+  ARC_INS_RSUB_F,
+  ARC_INS_SBC,
+  ARC_INS_SBC_F,
+  ARC_INS_SETEQ,
+  ARC_INS_SETEQ_F,
+  ARC_INS_SEXB_F,
+  ARC_INS_SEXB,
+  ARC_INS_SEXH_F,
+  ARC_INS_SEXH,
+  ARC_INS_STB_S,
+  ARC_INS_ST_S,
+  ARC_INS_STB_AB,
+  ARC_INS_STB_AW,
+  ARC_INS_STB_DI_AB,
+  ARC_INS_STB_DI_AW,
+  ARC_INS_STB_DI,
+  ARC_INS_STB,
+  ARC_INS_STH_AB,
+  ARC_INS_STH_AW,
+  ARC_INS_STH_DI_AB,
+  ARC_INS_STH_DI_AW,
+  ARC_INS_STH_DI,
+  ARC_INS_STH_S,
+  ARC_INS_STH,
+  ARC_INS_ST_AB,
+  ARC_INS_ST_AW,
+  ARC_INS_ST_DI_AB,
+  ARC_INS_ST_DI_AW,
+  ARC_INS_ST_DI,
+  ARC_INS_ST,
+  ARC_INS_SUB1,
+  ARC_INS_SUB1_F,
+  ARC_INS_SUB2,
+  ARC_INS_SUB2_F,
+  ARC_INS_SUB3,
+  ARC_INS_SUB3_F,
+  ARC_INS_SUB,
+  ARC_INS_SUB_F,
+  ARC_INS_XOR,
+  ARC_INS_XOR_F,

external/capstone/arch/ARC/ARCGenCSMappingInsnName.inc

@@ -0,0 +1,204 @@
+/* Capstone Disassembly Engine, https://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2024 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+  "invalid", // ARC_INS_INVALID
+  "h", // ARC_INS_h
+  "pbr", // ARC_INS_PBR
+  "error_fls", // ARC_INS_ERROR_FLS
+  "error_ffs", // ARC_INS_ERROR_FFS
+  "pldfi", // ARC_INS_PLDFI
+  "STB_FAR", // ARC_INS_STB_FAR
+  "STH_FAR", // ARC_INS_STH_FAR
+  "ST_FAR", // ARC_INS_ST_FAR
+  "adc", // ARC_INS_ADC
+  "adc_f", // ARC_INS_ADC_F
+  "add_s", // ARC_INS_ADD_S
+  "add", // ARC_INS_ADD
+  "add_f", // ARC_INS_ADD_F
+  "and", // ARC_INS_AND
+  "and_f", // ARC_INS_AND_F
+  "asl_s", // ARC_INS_ASL_S
+  "asl", // ARC_INS_ASL
+  "asl_f", // ARC_INS_ASL_F
+  "asr_s", // ARC_INS_ASR_S
+  "asr", // ARC_INS_ASR
+  "asr_f", // ARC_INS_ASR_F
+  "bclr_s", // ARC_INS_BCLR_S
+  "beq_s", // ARC_INS_BEQ_S
+  "bge_s", // ARC_INS_BGE_S
+  "bgt_s", // ARC_INS_BGT_S
+  "bhi_s", // ARC_INS_BHI_S
+  "bhs_s", // ARC_INS_BHS_S
+  "bl", // ARC_INS_BL
+  "ble_s", // ARC_INS_BLE_S
+  "blo_s", // ARC_INS_BLO_S
+  "bls_s", // ARC_INS_BLS_S
+  "blt_s", // ARC_INS_BLT_S
+  "bl_s", // ARC_INS_BL_S
+  "bmsk_s", // ARC_INS_BMSK_S
+  "bne_s", // ARC_INS_BNE_S
+  "b", // ARC_INS_B
+  "breq_s", // ARC_INS_BREQ_S
+  "brne_s", // ARC_INS_BRNE_S
+  "br", // ARC_INS_BR
+  "bset_s", // ARC_INS_BSET_S
+  "btst_s", // ARC_INS_BTST_S
+  "b_s", // ARC_INS_B_S
+  "cmp_s", // ARC_INS_CMP_S
+  "cmp", // ARC_INS_CMP
+  "ld_s", // ARC_INS_LD_S
+  "mov_s", // ARC_INS_MOV_S
+  "ei_s", // ARC_INS_EI_S
+  "enter_s", // ARC_INS_ENTER_S
+  "ffs_f", // ARC_INS_FFS_F
+  "ffs", // ARC_INS_FFS
+  "fls_f", // ARC_INS_FLS_F
+  "fls", // ARC_INS_FLS
+  "abs_s", // ARC_INS_ABS_S
+  "add1_s", // ARC_INS_ADD1_S
+  "add2_s", // ARC_INS_ADD2_S
+  "add3_s", // ARC_INS_ADD3_S
+  "and_s", // ARC_INS_AND_S
+  "bic_s", // ARC_INS_BIC_S
+  "brk_s", // ARC_INS_BRK_S
+  "extb_s", // ARC_INS_EXTB_S
+  "exth_s", // ARC_INS_EXTH_S
+  "jeq_s", // ARC_INS_JEQ_S
+  "jl_s", // ARC_INS_JL_S
+  "jl_s_d", // ARC_INS_JL_S_D
+  "jne_s", // ARC_INS_JNE_S
+  "j_s", // ARC_INS_J_S
+  "j_s_d", // ARC_INS_J_S_D
+  "lsr_s", // ARC_INS_LSR_S
+  "mpyuw_s", // ARC_INS_MPYUW_S
+  "mpyw_s", // ARC_INS_MPYW_S
+  "mpy_s", // ARC_INS_MPY_S
+  "neg_s", // ARC_INS_NEG_S
+  "nop_s", // ARC_INS_NOP_S
+  "not_s", // ARC_INS_NOT_S
+  "or_s", // ARC_INS_OR_S
+  "sexb_s", // ARC_INS_SEXB_S
+  "sexh_s", // ARC_INS_SEXH_S
+  "sub_s", // ARC_INS_SUB_S
+  "sub_s_ne", // ARC_INS_SUB_S_NE
+  "swi_s", // ARC_INS_SWI_S
+  "trap_s", // ARC_INS_TRAP_S
+  "tst_s", // ARC_INS_TST_S
+  "unimp_s", // ARC_INS_UNIMP_S
+  "xor_s", // ARC_INS_XOR_S
+  "ldb_s", // ARC_INS_LDB_S
+  "ldh_s", // ARC_INS_LDH_S
+  "j", // ARC_INS_J
+  "jl", // ARC_INS_JL
+  "jli_s", // ARC_INS_JLI_S
+  "ldb_ab", // ARC_INS_LDB_AB
+  "ldb_aw", // ARC_INS_LDB_AW
+  "ldb_di_ab", // ARC_INS_LDB_DI_AB
+  "ldb_di_aw", // ARC_INS_LDB_DI_AW
+  "ldb_di", // ARC_INS_LDB_DI
+  "ldb_x_ab", // ARC_INS_LDB_X_AB
+  "ldb_x_aw", // ARC_INS_LDB_X_AW
+  "ldb_x_di_ab", // ARC_INS_LDB_X_DI_AB
+  "ldb_x_di_aw", // ARC_INS_LDB_X_DI_AW
+  "ldb_x_di", // ARC_INS_LDB_X_DI
+  "ldb_x", // ARC_INS_LDB_X
+  "ldb", // ARC_INS_LDB
+  "ldh_ab", // ARC_INS_LDH_AB
+  "ldh_aw", // ARC_INS_LDH_AW
+  "ldh_di_ab", // ARC_INS_LDH_DI_AB
+  "ldh_di_aw", // ARC_INS_LDH_DI_AW
+  "ldh_di", // ARC_INS_LDH_DI
+  "ldh_s_x", // ARC_INS_LDH_S_X
+  "ldh_x_ab", // ARC_INS_LDH_X_AB
+  "ldh_x_aw", // ARC_INS_LDH_X_AW
+  "ldh_x_di_ab", // ARC_INS_LDH_X_DI_AB
+  "ldh_x_di_aw", // ARC_INS_LDH_X_DI_AW
+  "ldh_x_di", // ARC_INS_LDH_X_DI
+  "ldh_x", // ARC_INS_LDH_X
+  "ldh", // ARC_INS_LDH
+  "ldi_s", // ARC_INS_LDI_S
+  "ld_ab", // ARC_INS_LD_AB
+  "ld_aw", // ARC_INS_LD_AW
+  "ld_di_ab", // ARC_INS_LD_DI_AB
+  "ld_di_aw", // ARC_INS_LD_DI_AW
+  "ld_di", // ARC_INS_LD_DI
+  "ld_s_as", // ARC_INS_LD_S_AS
+  "ld", // ARC_INS_LD
+  "leave_s", // ARC_INS_LEAVE_S
+  "lr", // ARC_INS_LR
+  "lsr", // ARC_INS_LSR
+  "lsr_f", // ARC_INS_LSR_F
+  "max", // ARC_INS_MAX
+  "max_f", // ARC_INS_MAX_F
+  "min", // ARC_INS_MIN
+  "min_f", // ARC_INS_MIN_F
+  "mov_s_ne", // ARC_INS_MOV_S_NE
+  "mov", // ARC_INS_MOV
+  "mov_f", // ARC_INS_MOV_F
+  "mpymu", // ARC_INS_MPYMU
+  "mpymu_f", // ARC_INS_MPYMU_F
+  "mpym", // ARC_INS_MPYM
+  "mpym_f", // ARC_INS_MPYM_F
+  "mpy", // ARC_INS_MPY
+  "mpy_f", // ARC_INS_MPY_F
+  "normh_f", // ARC_INS_NORMH_F
+  "normh", // ARC_INS_NORMH
+  "norm_f", // ARC_INS_NORM_F
+  "norm", // ARC_INS_NORM
+  "or", // ARC_INS_OR
+  "or_f", // ARC_INS_OR_F
+  "pop_s", // ARC_INS_POP_S
+  "push_s", // ARC_INS_PUSH_S
+  "ror", // ARC_INS_ROR
+  "ror_f", // ARC_INS_ROR_F
+  "rsub", // ARC_INS_RSUB
+  "rsub_f", // ARC_INS_RSUB_F
+  "sbc", // ARC_INS_SBC
+  "sbc_f", // ARC_INS_SBC_F
+  "seteq", // ARC_INS_SETEQ
+  "seteq_f", // ARC_INS_SETEQ_F
+  "sexb_f", // ARC_INS_SEXB_F
+  "sexb", // ARC_INS_SEXB
+  "sexh_f", // ARC_INS_SEXH_F
+  "sexh", // ARC_INS_SEXH
+  "stb_s", // ARC_INS_STB_S
+  "st_s", // ARC_INS_ST_S
+  "stb_ab", // ARC_INS_STB_AB
+  "stb_aw", // ARC_INS_STB_AW
+  "stb_di_ab", // ARC_INS_STB_DI_AB
+  "stb_di_aw", // ARC_INS_STB_DI_AW
+  "stb_di", // ARC_INS_STB_DI
+  "stb", // ARC_INS_STB
+  "sth_ab", // ARC_INS_STH_AB
+  "sth_aw", // ARC_INS_STH_AW
+  "sth_di_ab", // ARC_INS_STH_DI_AB
+  "sth_di_aw", // ARC_INS_STH_DI_AW
+  "sth_di", // ARC_INS_STH_DI
+  "sth_s", // ARC_INS_STH_S
+  "sth", // ARC_INS_STH
+  "st_ab", // ARC_INS_ST_AB
+  "st_aw", // ARC_INS_ST_AW
+  "st_di_ab", // ARC_INS_ST_DI_AB
+  "st_di_aw", // ARC_INS_ST_DI_AW
+  "st_di", // ARC_INS_ST_DI
+  "st", // ARC_INS_ST
+  "sub1", // ARC_INS_SUB1
+  "sub1_f", // ARC_INS_SUB1_F
+  "sub2", // ARC_INS_SUB2
+  "sub2_f", // ARC_INS_SUB2_F
+  "sub3", // ARC_INS_SUB3
+  "sub3_f", // ARC_INS_SUB3_F
+  "sub", // ARC_INS_SUB
+  "sub_f", // ARC_INS_SUB_F
+  "xor", // ARC_INS_XOR
+  "xor_f", // ARC_INS_XOR_F

external/capstone/arch/ARC/ARCGenCSOpGroup.inc

@@ -0,0 +1,19 @@
+/* Capstone Disassembly Engine, https://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2024 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+  ARC_OP_GROUP_Operand = 0,
+  ARC_OP_GROUP_PredicateOperand = 1,
+  ARC_OP_GROUP_MemOperandRI = 2,
+  ARC_OP_GROUP_BRCCPredicateOperand = 3,
+  ARC_OP_GROUP_CCOperand = 4,
+  ARC_OP_GROUP_U6 = 5,

external/capstone/arch/ARC/ARCGenCSRegEnum.inc

@@ -0,0 +1,80 @@
+/* Capstone Disassembly Engine, https://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2024 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+	ARC_REG_INVALID = 0,
+	ARC_REG_BLINK = 1,
+	ARC_REG_FP = 2,
+	ARC_REG_GP = 3,
+	ARC_REG_ILINK = 4,
+	ARC_REG_SP = 5,
+	ARC_REG_R0 = 6,
+	ARC_REG_R1 = 7,
+	ARC_REG_R2 = 8,
+	ARC_REG_R3 = 9,
+	ARC_REG_R4 = 10,
+	ARC_REG_R5 = 11,
+	ARC_REG_R6 = 12,
+	ARC_REG_R7 = 13,
+	ARC_REG_R8 = 14,
+	ARC_REG_R9 = 15,
+	ARC_REG_R10 = 16,
+	ARC_REG_R11 = 17,
+	ARC_REG_R12 = 18,
+	ARC_REG_R13 = 19,
+	ARC_REG_R14 = 20,
+	ARC_REG_R15 = 21,
+	ARC_REG_R16 = 22,
+	ARC_REG_R17 = 23,
+	ARC_REG_R18 = 24,
+	ARC_REG_R19 = 25,
+	ARC_REG_R20 = 26,
+	ARC_REG_R21 = 27,
+	ARC_REG_R22 = 28,
+	ARC_REG_R23 = 29,
+	ARC_REG_R24 = 30,
+	ARC_REG_R25 = 31,
+	ARC_REG_R30 = 32,
+	ARC_REG_R32 = 33,
+	ARC_REG_R33 = 34,
+	ARC_REG_R34 = 35,
+	ARC_REG_R35 = 36,
+	ARC_REG_R36 = 37,
+	ARC_REG_R37 = 38,
+	ARC_REG_R38 = 39,
+	ARC_REG_R39 = 40,
+	ARC_REG_R40 = 41,
+	ARC_REG_R41 = 42,
+	ARC_REG_R42 = 43,
+	ARC_REG_R43 = 44,
+	ARC_REG_R44 = 45,
+	ARC_REG_R45 = 46,
+	ARC_REG_R46 = 47,
+	ARC_REG_R47 = 48,
+	ARC_REG_R48 = 49,
+	ARC_REG_R49 = 50,
+	ARC_REG_R50 = 51,
+	ARC_REG_R51 = 52,
+	ARC_REG_R52 = 53,
+	ARC_REG_R53 = 54,
+	ARC_REG_R54 = 55,
+	ARC_REG_R55 = 56,
+	ARC_REG_R56 = 57,
+	ARC_REG_R57 = 58,
+	ARC_REG_R58 = 59,
+	ARC_REG_R59 = 60,
+	ARC_REG_R60 = 61,
+	ARC_REG_R61 = 62,
+	ARC_REG_R62 = 63,
+	ARC_REG_R63 = 64,
+	ARC_REG_STATUS32 = 65,
+	ARC_REG_ENDING, // 66

external/capstone/arch/ARC/ARCGenRegisterInfo.inc

@@ -0,0 +1,296 @@
+#ifdef GET_REGINFO_ENUM
+#undef GET_REGINFO_ENUM
+
+enum {
+  ARC_NoRegister,
+  ARC_BLINK = 1,
+  ARC_FP = 2,
+  ARC_GP = 3,
+  ARC_ILINK = 4,
+  ARC_SP = 5,
+  ARC_R0 = 6,
+  ARC_R1 = 7,
+  ARC_R2 = 8,
+  ARC_R3 = 9,
+  ARC_R4 = 10,
+  ARC_R5 = 11,
+  ARC_R6 = 12,
+  ARC_R7 = 13,
+  ARC_R8 = 14,
+  ARC_R9 = 15,
+  ARC_R10 = 16,
+  ARC_R11 = 17,
+  ARC_R12 = 18,
+  ARC_R13 = 19,
+  ARC_R14 = 20,
+  ARC_R15 = 21,
+  ARC_R16 = 22,
+  ARC_R17 = 23,
+  ARC_R18 = 24,
+  ARC_R19 = 25,
+  ARC_R20 = 26,
+  ARC_R21 = 27,
+  ARC_R22 = 28,
+  ARC_R23 = 29,
+  ARC_R24 = 30,
+  ARC_R25 = 31,
+  ARC_R30 = 32,
+  ARC_R32 = 33,
+  ARC_R33 = 34,
+  ARC_R34 = 35,
+  ARC_R35 = 36,
+  ARC_R36 = 37,
+  ARC_R37 = 38,
+  ARC_R38 = 39,
+  ARC_R39 = 40,
+  ARC_R40 = 41,
+  ARC_R41 = 42,
+  ARC_R42 = 43,
+  ARC_R43 = 44,
+  ARC_R44 = 45,
+  ARC_R45 = 46,
+  ARC_R46 = 47,
+  ARC_R47 = 48,
+  ARC_R48 = 49,
+  ARC_R49 = 50,
+  ARC_R50 = 51,
+  ARC_R51 = 52,
+  ARC_R52 = 53,
+  ARC_R53 = 54,
+  ARC_R54 = 55,
+  ARC_R55 = 56,
+  ARC_R56 = 57,
+  ARC_R57 = 58,
+  ARC_R58 = 59,
+  ARC_R59 = 60,
+  ARC_R60 = 61,
+  ARC_R61 = 62,
+  ARC_R62 = 63,
+  ARC_R63 = 64,
+  ARC_STATUS32 = 65,
+  NUM_TARGET_REGS // 66
+};
+
+// Register classes
+
+enum {
+  ARC_SREGRegClassID = 0,
+  ARC_GPR_SRegClassID = 1,
+  ARC_GPR32RegClassID = 2,
+  ARC_GPR32_and_GPR_SRegClassID = 3,
+
+};
+#endif // GET_REGINFO_ENUM
+
+/* Capstone Disassembly Engine, https://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2024 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+#ifdef GET_REGINFO_MC_DESC
+#undef GET_REGINFO_MC_DESC
+
+static const MCPhysReg ARCRegDiffLists[] = {
+  /* 0 */ 0,
+};
+
+static const uint16_t ARCSubRegIdxLists[] = {
+  /* 0 */ 0,
+};
+
+static const MCRegisterDesc ARCRegDesc[] = { // Descriptors
+  { 3, 0, 0, 0, 0, 0 },
+  { 235, 0, 0, 0, 0, 0 },
+  { 247, 0, 0, 0, 1, 0 },
+  { 250, 0, 0, 0, 2, 0 },
+  { 241, 0, 0, 0, 3, 0 },
+  { 253, 0, 0, 0, 4, 0 },
+  { 24, 0, 0, 0, 5, 0 },
+  { 47, 0, 0, 0, 6, 0 },
+  { 83, 0, 0, 0, 7, 0 },
+  { 110, 0, 0, 0, 8, 0 },
+  { 133, 0, 0, 0, 9, 0 },
+  { 156, 0, 0, 0, 10, 0 },
+  { 175, 0, 0, 0, 11, 0 },
+  { 194, 0, 0, 0, 12, 0 },
+  { 213, 0, 0, 0, 13, 0 },
+  { 232, 0, 0, 0, 14, 0 },
+  { 0, 0, 0, 0, 15, 0 },
+  { 27, 0, 0, 0, 16, 0 },
+  { 50, 0, 0, 0, 17, 0 },
+  { 86, 0, 0, 0, 18, 0 },
+  { 113, 0, 0, 0, 19, 0 },
+  { 136, 0, 0, 0, 20, 0 },
+  { 159, 0, 0, 0, 21, 0 },
+  { 178, 0, 0, 0, 22, 0 },
+  { 197, 0, 0, 0, 23, 0 },
+  { 216, 0, 0, 0, 24, 0 },
+  { 4, 0, 0, 0, 25, 0 },
+  { 31, 0, 0, 0, 26, 0 },
+  { 54, 0, 0, 0, 27, 0 },
+  { 90, 0, 0, 0, 28, 0 },
+  { 117, 0, 0, 0, 29, 0 },
+  { 140, 0, 0, 0, 30, 0 },
+  { 8, 0, 0, 0, 31, 0 },
+  { 58, 0, 0, 0, 32, 0 },
+  { 94, 0, 0, 0, 33, 0 },
+  { 121, 0, 0, 0, 34, 0 },
+  { 144, 0, 0, 0, 35, 0 },
+  { 163, 0, 0, 0, 36, 0 },
+  { 182, 0, 0, 0, 37, 0 },
+  { 201, 0, 0, 0, 38, 0 },
+  { 220, 0, 0, 0, 39, 0 },
+  { 12, 0, 0, 0, 40, 0 },
+  { 35, 0, 0, 0, 41, 0 },
+  { 71, 0, 0, 0, 42, 0 },
+  { 98, 0, 0, 0, 43, 0 },
+  { 125, 0, 0, 0, 44, 0 },
+  { 148, 0, 0, 0, 45, 0 },
+  { 167, 0, 0, 0, 46, 0 },
+  { 186, 0, 0, 0, 47, 0 },
+  { 205, 0, 0, 0, 48, 0 },
+  { 224, 0, 0, 0, 49, 0 },
+  { 16, 0, 0, 0, 50, 0 },
+  { 39, 0, 0, 0, 51, 0 },
+  { 75, 0, 0, 0, 52, 0 },
+  { 102, 0, 0, 0, 53, 0 },
+  { 129, 0, 0, 0, 54, 0 },
+  { 152, 0, 0, 0, 55, 0 },
+  { 171, 0, 0, 0, 56, 0 },
+  { 190, 0, 0, 0, 57, 0 },
+  { 209, 0, 0, 0, 58, 0 },
+  { 228, 0, 0, 0, 59, 0 },
+  { 20, 0, 0, 0, 60, 0 },
+  { 43, 0, 0, 0, 61, 0 },
+  { 79, 0, 0, 0, 62, 0 },
+  { 106, 0, 0, 0, 63, 0 },
+  { 62, 0, 0, 0, 64, 0 },
+};
+
+  // SREG Register Class...
+  static const MCPhysReg SREG[] = {
+    ARC_STATUS32, 
+  };
+
+  // SREG Bit set.
+  static const uint8_t SREGBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 
+  };
+
+  // GPR_S Register Class...
+  static const MCPhysReg GPR_S[] = {
+    ARC_R0, ARC_R1, ARC_R2, ARC_R3, ARC_R12, ARC_R13, ARC_R14, ARC_R15, 
+  };
+
+  // GPR_S Bit set.
+  static const uint8_t GPR_SBits[] = {
+    0xc0, 0x03, 0x3c, 
+  };
+
+  // GPR32 Register Class...
+  static const MCPhysReg GPR32[] = {
+    ARC_R0, ARC_R1, ARC_R2, ARC_R3, ARC_R4, ARC_R5, ARC_R6, ARC_R7, ARC_R8, ARC_R9, ARC_R10, ARC_R11, ARC_R12, ARC_R13, ARC_R14, ARC_R15, ARC_R16, ARC_R17, ARC_R18, ARC_R19, ARC_R20, ARC_R21, ARC_R22, ARC_R23, ARC_R24, ARC_R25, ARC_GP, ARC_FP, ARC_SP, ARC_ILINK, ARC_R30, ARC_BLINK, ARC_R32, ARC_R33, ARC_R34, ARC_R35, ARC_R36, ARC_R37, ARC_R38, ARC_R39, ARC_R40, ARC_R41, ARC_R42, ARC_R43, ARC_R44, ARC_R45, ARC_R46, ARC_R47, ARC_R48, ARC_R49, ARC_R50, ARC_R51, ARC_R52, ARC_R53, ARC_R54, ARC_R55, ARC_R56, ARC_R57, ARC_R58, ARC_R59, ARC_R60, ARC_R61, ARC_R62, ARC_R63, 
+  };
+
+  // GPR32 Bit set.
+  static const uint8_t GPR32Bits[] = {
+    0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01, 
+  };
+
+  // GPR32_and_GPR_S Register Class...
+  static const MCPhysReg GPR32_and_GPR_S[] = {
+    ARC_R0, ARC_R1, ARC_R2, ARC_R3, ARC_R12, ARC_R13, ARC_R14, ARC_R15, 
+  };
+
+  // GPR32_and_GPR_S Bit set.
+  static const uint8_t GPR32_and_GPR_SBits[] = {
+    0xc0, 0x03, 0x3c, 
+  };
+
+static const MCRegisterClass ARCMCRegisterClasses[] = {
+  { SREG, SREGBits, sizeof(SREGBits) },
+  { GPR_S, GPR_SBits, sizeof(GPR_SBits) },
+  { GPR32, GPR32Bits, sizeof(GPR32Bits) },
+  { GPR32_and_GPR_S, GPR32_and_GPR_SBits, sizeof(GPR32_and_GPR_SBits) },
+};
+
+static const uint16_t ARCRegEncodingTable[] = {
+  0,
+  31,
+  27,
+  26,
+  29,
+  28,
+  0,
+  1,
+  2,
+  3,
+  4,
+  5,
+  6,
+  7,
+  8,
+  9,
+  10,
+  11,
+  12,
+  13,
+  14,
+  15,
+  16,
+  17,
+  18,
+  19,
+  20,
+  21,
+  22,
+  23,
+  24,
+  25,
+  30,
+  32,
+  33,
+  34,
+  35,
+  36,
+  37,
+  38,
+  39,
+  40,
+  41,
+  42,
+  43,
+  44,
+  45,
+  46,
+  47,
+  48,
+  49,
+  50,
+  51,
+  52,
+  53,
+  54,
+  55,
+  56,
+  57,
+  58,
+  59,
+  60,
+  61,
+  62,
+  63,
+  10,
+};
+#endif // GET_REGINFO_MC_DESC
+
+
+

external/capstone/arch/ARC/ARCGenSubtargetInfo.inc

@@ -0,0 +1,24 @@
+/* Capstone Disassembly Engine, https://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2024 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+#ifdef GET_SUBTARGETINFO_ENUM
+#undef GET_SUBTARGETINFO_ENUM
+
+enum {
+  ARC_FeatureNORM = 0,
+  ARC_NumSubtargetFeatures = 1
+};
+#endif // GET_SUBTARGETINFO_ENUM
+
+
+

external/capstone/arch/ARC/ARCInfo.h

@@ -0,0 +1,72 @@
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically translated source file from LLVM. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Only small edits allowed. */
+/* For multiple similar edits, please create a Patch for the translator. */
+
+/* Capstone's C++ file translator: */
+/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
+
+//===- ARCInfo.h - Additional ARC Info --------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains small standalone helper functions and enum definitions for
+// the ARC target useful for the compiler back-end and the MC libraries.
+// As such, it deliberately does not include references to LLVM core
+// code gen types, passes, etc..
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_ARC_MCTARGETDESC_ARCINFO_H
+#define LLVM_LIB_TARGET_ARC_MCTARGETDESC_ARCINFO_H
+
+// Enums corresponding to ARC condition codes
+// CS namespace begin: ARCCC
+
+typedef enum ARCCondCode {
+	ARCCC_AL = 0x0,
+	ARCCC_EQ = 0x1,
+	ARCCC_NE = 0x2,
+	ARCCC_P = 0x3,
+	ARCCC_N = 0x4,
+	ARCCC_LO = 0x5,
+	ARCCC_HS = 0x6,
+	ARCCC_VS = 0x7,
+	ARCCC_VC = 0x8,
+	ARCCC_GT = 0x9,
+	ARCCC_GE = 0xa,
+	ARCCC_LT = 0xb,
+	ARCCC_LE = 0xc,
+	ARCCC_HI = 0xd,
+	ARCCC_LS = 0xe,
+	ARCCC_PNZ = 0xf,
+	ARCCC_Z = 0x11, // Low 4-bits = EQ
+	ARCCC_NZ = 0x12 // Low 4-bits = NE
+} ARCCC_CondCode;
+
+typedef enum BRCondCode {
+	ARCCC_BREQ = 0x0,
+	ARCCC_BRNE = 0x1,
+	ARCCC_BRLT = 0x2,
+	ARCCC_BRGE = 0x3,
+	ARCCC_BRLO = 0x4,
+	ARCCC_BRHS = 0x5
+} ARCCC_BRCondCode;
+
+// CS namespace end: ARCCC
+
+// end namespace ARCCC
+
+// end namespace llvm
+
+#endif

external/capstone/arch/ARC/ARCInstPrinter.c

@@ -0,0 +1,210 @@
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically translated source file from LLVM. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Only small edits allowed. */
+/* For multiple similar edits, please create a Patch for the translator. */
+
+/* Capstone's C++ file translator: */
+/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
+
+//===- ARCInstPrinter.cpp - ARC MCInst to assembly syntax -------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This class prints an ARC MCInst to a .s file.
+//
+//===----------------------------------------------------------------------===//
+
+#ifdef CAPSTONE_HAS_ARC
+
+#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
+#include <capstone/platform.h>
+
+#include "../../SStream.h"
+#include "../../MCInst.h"
+#include "../../MCInstPrinter.h"
+
+#include "ARCInfo.h"
+#include "ARCInstPrinter.h"
+#include "ARCLinkage.h"
+#include "ARCMapping.h"
+
+#define CONCAT(a, b) CONCAT_(a, b)
+#define CONCAT_(a, b) a##_##b
+
+#define DEBUG_TYPE "asm-printer"
+
+#include "ARCGenAsmWriter.inc"
+
+static const char *ARCBRCondCodeToString(ARCCC_BRCondCode BRCC)
+{
+	switch (BRCC) {
+	case ARCCC_BREQ:
+		return "eq";
+	case ARCCC_BRNE:
+		return "ne";
+	case ARCCC_BRLT:
+		return "lt";
+	case ARCCC_BRGE:
+		return "ge";
+	case ARCCC_BRLO:
+		return "lo";
+	case ARCCC_BRHS:
+		return "hs";
+	}
+	// CS_ASSERT(0 && "Unknown condition code passed");
+	return "";
+}
+
+static const char *ARCCondCodeToString(ARCCC_CondCode CC)
+{
+	switch (CC) {
+	case ARCCC_EQ:
+		return "eq";
+	case ARCCC_NE:
+		return "ne";
+	case ARCCC_P:
+		return "p";
+	case ARCCC_N:
+		return "n";
+	case ARCCC_HS:
+		return "hs";
+	case ARCCC_LO:
+		return "lo";
+	case ARCCC_GT:
+		return "gt";
+	case ARCCC_GE:
+		return "ge";
+	case ARCCC_VS:
+		return "vs";
+	case ARCCC_VC:
+		return "vc";
+	case ARCCC_LT:
+		return "lt";
+	case ARCCC_LE:
+		return "le";
+	case ARCCC_HI:
+		return "hi";
+	case ARCCC_LS:
+		return "ls";
+	case ARCCC_PNZ:
+		return "pnz";
+	case ARCCC_AL:
+		return "al";
+	case ARCCC_NZ:
+		return "nz";
+	case ARCCC_Z:
+		return "z";
+	}
+	// CS_ASSERT(0 && "Unknown condition code passed");
+	return "";
+}
+
+static void printRegName(SStream *OS, MCRegister Reg)
+{
+	SStream_concat0(OS, getRegisterName(Reg));
+}
+
+static void printInst(MCInst *MI, uint64_t Address, const char *Annot, SStream *O)
+{
+	printInstruction(MI, Address, O);
+}
+
+static void printOperand(MCInst *MI, unsigned OpNum, SStream *O)
+{
+	add_cs_detail(MI, ARC_OP_GROUP_Operand, OpNum);
+	MCOperand *Op = MCInst_getOperand(MI, (OpNum));
+	if (MCOperand_isReg(Op)) {
+		printRegName(O, MCOperand_getReg(Op));
+	} else if (MCOperand_isImm(Op)) {
+		SStream_concat(O, "%" PRId64, MCOperand_getImm(Op));
+	} else if (MCOperand_isExpr(Op)) {
+		printExpr(O, MCOperand_getExpr(Op));
+	}
+}
+
+static void printOperandAddr(MCInst *MI, uint64_t Address, unsigned OpNum, SStream *O)
+{
+	printOperand(MI, OpNum, O);
+}
+
+static void printMemOperandRI(MCInst *MI, unsigned OpNum, SStream *O)
+{
+	add_cs_detail(MI, ARC_OP_GROUP_MemOperandRI, OpNum);
+	MCOperand *base = MCInst_getOperand(MI, (OpNum));
+	MCOperand *offset = MCInst_getOperand(MI, (OpNum + 1));
+	CS_ASSERT((MCOperand_isReg(base) && "Base should be register."));
+	CS_ASSERT((MCOperand_isImm(offset) && "Offset should be immediate."));
+	printRegName(O, MCOperand_getReg(base));
+	SStream_concat(O, "%s", ",");
+	printInt64(O, MCOperand_getImm(offset));
+}
+
+static void printPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O)
+{
+	add_cs_detail(MI, ARC_OP_GROUP_PredicateOperand, OpNum);
+
+	MCOperand *Op = MCInst_getOperand(MI, (OpNum));
+	CS_ASSERT((MCOperand_isImm(Op) && "Predicate operand is immediate."));
+	SStream_concat0(
+		O, ARCCondCodeToString((ARCCC_CondCode)MCOperand_getImm(Op)));
+}
+
+static void printBRCCPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O)
+{
+	add_cs_detail(MI, ARC_OP_GROUP_BRCCPredicateOperand, OpNum);
+	MCOperand *Op = MCInst_getOperand(MI, (OpNum));
+	CS_ASSERT((MCOperand_isImm(Op) && "Predicate operand is immediate."));
+	SStream_concat0(O, ARCBRCondCodeToString(
+				   (ARCCC_BRCondCode)MCOperand_getImm(Op)));
+}
+
+static void printCCOperand(MCInst *MI, int OpNum, SStream *O)
+{
+	add_cs_detail(MI, ARC_OP_GROUP_CCOperand, OpNum);
+	SStream_concat0(O, ARCCondCodeToString((ARCCC_CondCode)MCOperand_getImm(
+				   MCInst_getOperand(MI, (OpNum)))));
+}
+
+static void printU6ShiftedBy(unsigned ShiftBy, MCInst *MI, int OpNum, SStream *O)
+{
+	MCOperand *MO = MCInst_getOperand(MI, (OpNum));
+	if (MCOperand_isImm(MO)) {
+		unsigned Value = MCOperand_getImm(MO);
+		unsigned Value2 = Value >> ShiftBy;
+		if (Value2 > 0x3F || (Value2 << ShiftBy != Value)) {
+			CS_ASSERT((false && "instruction has wrong format"));
+		}
+	}
+	printOperand(MI, OpNum, O);
+}
+
+static void printU6(MCInst *MI, int OpNum, SStream *O)
+{
+	add_cs_detail(MI, ARC_OP_GROUP_U6, OpNum);
+	printU6ShiftedBy(0, MI, OpNum, O);
+}
+
+void ARC_LLVM_printInst(MCInst *MI, uint64_t Address, const char *Annot,
+			      SStream *O)
+{
+	printInst(MI, Address, Annot, O);
+}
+
+const char *ARC_LLVM_getRegisterName(unsigned RegNo)
+{
+	return getRegisterName(RegNo);
+}
+
+#endif

external/capstone/arch/ARC/ARCInstPrinter.h

@@ -0,0 +1,58 @@
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically translated source file from LLVM. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Only small edits allowed. */
+/* For multiple similar edits, please create a Patch for the translator. */
+
+/* Capstone's C++ file translator: */
+/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
+
+//===- ARCInstPrinter.h - Convert ARC MCInst to assembly syntax -*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+///
+/// \file
+/// This file contains the declaration of the ARCInstPrinter class,
+/// which is used to print ARC MCInst to a .s file.
+///
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_ARC_INSTPRINTER_ARCINSTPRINTER_H
+#define LLVM_LIB_TARGET_ARC_INSTPRINTER_ARCINSTPRINTER_H
+
+#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
+#include <capstone/platform.h>
+
+#include "../../SStream.h"
+#include "../../MCInst.h"
+
+#define CONCAT(a, b) CONCAT_(a, b)
+#define CONCAT_(a, b) a##_##b
+
+// Autogenerated by tblgen.
+static void printInstruction(MCInst *MI, uint64_t Address, SStream *O);
+static void printRegName(SStream *OS, MCRegister Reg);
+static void printInst(MCInst *MI, uint64_t Address, const char *Annot, SStream *O);
+static void printCCOperand(MCInst *MI, int OpNum, SStream *O);
+static void printU6(MCInst *MI, int OpNum, SStream *O);
+static void printMemOperandRI(MCInst *MI, unsigned OpNum, SStream *O);
+static void printOperand(MCInst *MI, unsigned OpNum, SStream *O);
+static void printOperandAddr(MCInst *MI, uint64_t Address, unsigned OpNum, SStream *O);
+static void printPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O);
+static void printBRCCPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O);
+static void printU6ShiftedBy(unsigned ShiftBy, MCInst *MI, int OpNum, SStream *O);
+;
+// end namespace llvm
+
+#endif // LLVM_LIB_TARGET_ARC_INSTPRINTER_ARCINSTPRINTER_H

external/capstone/arch/ARC/ARCLinkage.h

@@ -0,0 +1,23 @@
+/* Capstone Disassembly Engine */
+/* By Dmitry Sibirtsev <sibirtsevdl@gmail.com>, 2024 */
+
+#ifndef CS_ARC_LINKAGE_H
+#define CS_ARC_LINKAGE_H
+
+// Function definitions to call static LLVM functions.
+
+#include "../../MCDisassembler.h"
+#include "../../MCInst.h"
+#include "../../MCRegisterInfo.h"
+#include "../../SStream.h"
+#include "capstone/capstone.h"
+
+const char *ARC_LLVM_getRegisterName(unsigned RegNo);
+void ARC_LLVM_printInst(MCInst *MI, uint64_t Address, const char *Annot,
+			      SStream *O);
+DecodeStatus ARC_LLVM_getInstruction(MCInst *MI, uint64_t *Size,
+					   const uint8_t *Bytes,
+					   size_t BytesLen, uint64_t Address,
+					   SStream *CS);
+
+#endif // CS_ARC_LINKAGE_H

external/capstone/arch/ARC/ARCMapping.c

@@ -0,0 +1,290 @@
+/* Capstone Disassembly Engine */
+/* By Dmitry Sibirtsev <sibirtsevdl@gmail.com>, 2024 */
+
+#ifdef CAPSTONE_HAS_ARC
+
+#include <stdio.h>
+#include <string.h>
+
+#include <capstone/capstone.h>
+#include <capstone/arc.h>
+
+#include "../../Mapping.h"
+#include "../../MCDisassembler.h"
+#include "../../cs_priv.h"
+#include "../../cs_simple_types.h"
+
+#include "ARCMapping.h"
+#include "ARCLinkage.h"
+
+#define GET_REGINFO_ENUM
+#define GET_REGINFO_MC_DESC
+#include "ARCGenRegisterInfo.inc"
+
+#define GET_INSTRINFO_ENUM
+#include "ARCGenInstrInfo.inc"
+
+void ARC_init_mri(MCRegisterInfo *MRI)
+{
+	MCRegisterInfo_InitMCRegisterInfo(MRI, ARCRegDesc,
+					  sizeof(ARCRegDesc), 0, 0,
+					  ARCMCRegisterClasses,
+					  ARR_SIZE(ARCMCRegisterClasses),
+					  0, 0, ARCRegDiffLists, 0,
+					  ARCSubRegIdxLists,
+					  ARR_SIZE(ARCSubRegIdxLists), 0);
+}
+
+const char *ARC_reg_name(csh handle, unsigned int reg)
+{
+	return ARC_LLVM_getRegisterName(reg);
+}
+
+void ARC_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
+{
+	// Not used by ARC. Information is set after disassembly.
+}
+
+static const char *const insn_name_maps[] = {
+#include "ARCGenCSMappingInsnName.inc"
+};
+
+const char *ARC_insn_name(csh handle, unsigned int id)
+{
+#ifndef CAPSTONE_DIET
+	if (id < ARR_SIZE(insn_name_maps))
+		return insn_name_maps[id];
+	// not found
+	return NULL;
+#else
+	return NULL;
+#endif
+}
+
+#ifndef CAPSTONE_DIET
+static const name_map group_name_maps[] = {
+	{ ARC_GRP_INVALID, NULL },
+
+	{ ARC_GRP_JUMP, "jump" },
+	{ ARC_GRP_CALL, "call" },
+	{ ARC_GRP_RET, "return" },
+	{ ARC_GRP_BRANCH_RELATIVE, "branch_relative" },
+
+};
+#endif
+
+const char *ARC_group_name(csh handle, unsigned int id)
+{
+#ifndef CAPSTONE_DIET
+	return id2name(group_name_maps, ARR_SIZE(group_name_maps), id);
+#else
+	return NULL;
+#endif
+}
+
+void ARC_reg_access(const cs_insn *insn, cs_regs regs_read,
+			  uint8_t *regs_read_count, cs_regs regs_write,
+			  uint8_t *regs_write_count)
+{
+	uint8_t i;
+	uint8_t read_count, write_count;
+	cs_arc *arc = &(insn->detail->arc);
+
+	read_count = insn->detail->regs_read_count;
+	write_count = insn->detail->regs_write_count;
+
+	// implicit registers
+	memcpy(regs_read, insn->detail->regs_read,
+	       read_count * sizeof(insn->detail->regs_read[0]));
+	memcpy(regs_write, insn->detail->regs_write,
+	       write_count * sizeof(insn->detail->regs_write[0]));
+
+	// explicit registers
+	for (i = 0; i < arc->op_count; i++) {
+		cs_arc_op *op = &(arc->operands[i]);
+		switch ((int)op->type) {
+		case ARC_OP_REG:
+			if ((op->access & CS_AC_READ) &&
+			    !arr_exist(regs_read, read_count, op->reg)) {
+				regs_read[read_count] = (uint16_t)op->reg;
+				read_count++;
+			}
+			if ((op->access & CS_AC_WRITE) &&
+			    !arr_exist(regs_write, write_count, op->reg)) {
+				regs_write[write_count] = (uint16_t)op->reg;
+				write_count++;
+			}
+			break;
+		default:
+			break;
+		}
+	}
+
+	*regs_read_count = read_count;
+	*regs_write_count = write_count;
+}
+
+const insn_map arc_insns[] = {
+#include "ARCGenCSMappingInsn.inc"
+};
+
+void ARC_set_instr_map_data(MCInst *MI)
+{
+	map_cs_id(MI, arc_insns, ARR_SIZE(arc_insns));
+	map_implicit_reads(MI, arc_insns);
+	map_implicit_writes(MI, arc_insns);
+	map_groups(MI, arc_insns);
+}
+
+bool ARC_getInstruction(csh handle, const uint8_t *code, size_t code_len,
+			      MCInst *instr, uint16_t *size, uint64_t address,
+			      void *info)
+{
+	uint64_t temp_size;
+	ARC_init_cs_detail(instr);
+	DecodeStatus Result = ARC_LLVM_getInstruction(instr, &temp_size, code,
+						    code_len, address, info);
+	ARC_set_instr_map_data(instr);
+	*size = temp_size;
+	if (Result == MCDisassembler_SoftFail) {
+		MCInst_setSoftFail(instr);
+	}
+	return Result != MCDisassembler_Fail;
+}
+
+void ARC_printer(MCInst *MI, SStream *O,
+		       void * /* MCRegisterInfo* */ info)
+{
+	MCRegisterInfo *MRI = (MCRegisterInfo *)info;
+	MI->MRI = MRI;
+
+	ARC_LLVM_printInst(MI, MI->address, "", O);
+}
+
+void ARC_setup_op(cs_arc_op *op)
+{
+	memset(op, 0, sizeof(cs_arc_op));
+	op->type = ARC_OP_INVALID;
+}
+
+void ARC_init_cs_detail(MCInst *MI)
+{
+	if (!detail_is_set(MI)) {
+		return;
+	}
+	unsigned int i;
+
+	memset(get_detail(MI), 0,
+			offsetof(cs_detail, arc) + sizeof(cs_arc));
+
+	for (i = 0; i < ARR_SIZE(ARC_get_detail(MI)->operands);
+			i++)
+		ARC_setup_op(
+			&ARC_get_detail(MI)->operands[i]);
+}
+
+static const map_insn_ops insn_operands[] = {
+#include "ARCGenCSMappingInsnOp.inc"
+};
+
+void ARC_set_detail_op_imm(MCInst *MI, unsigned OpNum,
+				 arc_op_type ImmType, int64_t Imm)
+{
+	if (!detail_is_set(MI))
+		return;
+	ARC_check_safe_inc(MI);
+	CS_ASSERT((map_get_op_type(MI, OpNum) & ~CS_OP_MEM) == CS_OP_IMM);
+	CS_ASSERT(ImmType == ARC_OP_IMM);
+
+	ARC_get_detail_op(MI, 0)->type = ImmType;
+	ARC_get_detail_op(MI, 0)->imm = Imm;
+	ARC_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum);
+	ARC_inc_op_count(MI);
+}
+
+void ARC_set_detail_op_reg(MCInst *MI, unsigned OpNum, arc_reg Reg)
+{
+	if (!detail_is_set(MI))
+		return;
+	ARC_check_safe_inc(MI);
+	CS_ASSERT((map_get_op_type(MI, OpNum) & ~CS_OP_MEM) == CS_OP_REG);
+
+	ARC_get_detail_op(MI, 0)->type = ARC_OP_REG;
+	ARC_get_detail_op(MI, 0)->reg = Reg;
+	ARC_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum);
+	ARC_inc_op_count(MI);
+}
+
+void ARC_add_cs_detail(MCInst *MI, int op_group,
+			     va_list args)
+{
+	if (!detail_is_set(MI))
+		return;
+
+	unsigned OpNum = va_arg(args, unsigned);
+	cs_op_type op_type = map_get_op_type(MI, OpNum);
+	cs_op_type base_op_type = op_type;
+	cs_op_type offset_op_type;
+	// Fill cs_detail
+	switch (op_group) {
+	default:
+		printf("ERROR: Operand group %d not handled!\n", op_group);
+		CS_ASSERT_RET(0);
+	case ARC_OP_GROUP_Operand:
+		if (op_type == CS_OP_IMM) {
+			ARC_set_detail_op_imm(MI, OpNum, ARC_OP_IMM,
+						    MCInst_getOpVal(MI, OpNum));
+		} else if (op_type == CS_OP_REG) {
+			ARC_set_detail_op_reg(MI, OpNum,
+						    MCInst_getOpVal(MI, OpNum));
+		} else {
+			// Expression
+			ARC_set_detail_op_imm(MI, OpNum, ARC_OP_IMM,
+						    MCOperand_getImm(MCInst_getOperand(MI, OpNum)));
+		}
+		break;
+	case ARC_OP_GROUP_PredicateOperand:
+		if (op_type == CS_OP_IMM) {
+			ARC_set_detail_op_imm(MI, OpNum, ARC_OP_IMM,
+						    MCInst_getOpVal(MI, OpNum));
+		} else
+			CS_ASSERT(0 && "Op type not handled.");
+		break;
+	case ARC_OP_GROUP_MemOperandRI:
+		if (base_op_type == CS_OP_REG) {
+			ARC_set_detail_op_reg(MI, OpNum,
+						    MCInst_getOpVal(MI, OpNum));
+		} else
+			CS_ASSERT(0 && "Op type not handled.");
+		offset_op_type = map_get_op_type(MI, OpNum+1);
+		if (offset_op_type == CS_OP_IMM) {
+			ARC_set_detail_op_imm(MI, OpNum+1, ARC_OP_IMM,
+						    MCInst_getOpVal(MI, OpNum+1));
+		} else
+			CS_ASSERT(0 && "Op type not handled.");
+		break;
+	case ARC_OP_GROUP_BRCCPredicateOperand:
+		if (op_type == CS_OP_IMM) {
+			ARC_set_detail_op_imm(MI, OpNum, ARC_OP_IMM,
+						    MCInst_getOpVal(MI, OpNum));
+		} else
+			CS_ASSERT(0 && "Op type not handled.");
+		break;
+	case ARC_OP_GROUP_CCOperand:
+		if (op_type == CS_OP_IMM) {
+			ARC_set_detail_op_imm(MI, OpNum, ARC_OP_IMM,
+						    MCInst_getOpVal(MI, OpNum));
+		} else
+			CS_ASSERT(0 && "Op type not handled.");
+		break;
+	case ARC_OP_GROUP_U6:
+		if (op_type == CS_OP_IMM) {
+			ARC_set_detail_op_imm(MI, OpNum, ARC_OP_IMM,
+						    MCInst_getOpVal(MI, OpNum));
+		} else
+			CS_ASSERT(0 && "Op type not handled.");
+		break;		
+	}
+}
+
+#endif

external/capstone/arch/ARC/ARCMapping.h

@@ -0,0 +1,55 @@
+/* Capstone Disassembly Engine */
+/* By Dmitry Sibirtsev <sibirtsevdl@gmail.com>, 2024 */
+
+#ifndef CS_ARC_MAP_H
+#define CS_ARC_MAP_H
+
+#include "../../Mapping.h"
+#include "../../include/capstone/capstone.h"
+#include "../../utils.h"
+
+typedef enum {
+#include "ARCGenCSOpGroup.inc"
+} arc_op_group;
+
+void ARC_init_mri(MCRegisterInfo *MRI);
+
+// return name of register in friendly string
+const char *ARC_reg_name(csh handle, unsigned int reg);
+
+void ARC_printer(MCInst *MI, SStream *O,
+		       void * /* MCRegisterInfo* */ info);
+
+// given internal insn id, return public instruction ID
+void ARC_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
+
+const char *ARC_insn_name(csh handle, unsigned int id);
+
+const char *ARC_group_name(csh handle, unsigned int id);
+
+void ARC_reg_access(const cs_insn *insn, cs_regs regs_read,
+			  uint8_t *regs_read_count, cs_regs regs_write,
+			  uint8_t *regs_write_count);
+
+bool ARC_getInstruction(csh handle, const uint8_t *code, size_t code_len,
+			      MCInst *instr, uint16_t *size, uint64_t address,
+			      void *info);
+
+// cs_detail related functions
+void ARC_init_cs_detail(MCInst *MI);
+void ARC_set_detail_op_imm(MCInst *MI, unsigned OpNum,
+				 arc_op_type ImmType, int64_t Imm);
+void ARC_add_cs_detail(MCInst *MI, int /* arc_op_group */ op_group,
+			     va_list args);
+static inline void add_cs_detail(MCInst *MI,
+				 int /* arc_op_group */ op_group, ...)
+{
+	if (!detail_is_set(MI))
+		return;
+	va_list args;
+	va_start(args, op_group);
+	ARC_add_cs_detail(MI, op_group, args);
+	va_end(args);
+}
+
+#endif

external/capstone/arch/ARC/ARCModule.c

@@ -0,0 +1,52 @@
+/* Capstone Disassembly Engine */
+/* By Dmitry Sibirtsev <sibirtsevdl@gmail.com>, 2024 */
+
+#ifdef CAPSTONE_HAS_ARC
+
+#include <capstone/capstone.h>
+
+#include "ARCModule.h"
+#include "../../MCRegisterInfo.h"
+#include "../../cs_priv.h"
+#include "ARCMapping.h"
+
+cs_err ARC_global_init(cs_struct *ud)
+{
+	MCRegisterInfo *mri;
+	mri = cs_mem_malloc(sizeof(*mri));
+
+	ARC_init_mri(mri);
+
+	ud->printer = ARC_printer;
+	ud->printer_info = mri;
+	ud->reg_name = ARC_reg_name;
+	ud->insn_id = ARC_get_insn_id;
+	ud->insn_name = ARC_insn_name;
+	ud->group_name = ARC_group_name;
+	ud->post_printer = NULL;
+#ifndef CAPSTONE_DIET
+	ud->reg_access = ARC_reg_access;
+#endif
+
+	ud->disasm = ARC_getInstruction;
+
+	return CS_ERR_OK;
+}
+
+cs_err ARC_option(cs_struct *handle, cs_opt_type type, size_t value)
+{
+	switch (type) {
+	case CS_OPT_MODE:
+		handle->mode = (cs_mode)value;
+		break;
+	case CS_OPT_SYNTAX:
+		handle->syntax |= (int)value;
+		break;
+	default:
+		break;
+	}
+
+	return CS_ERR_OK;
+}
+
+#endif

external/capstone/arch/ARC/ARCModule.h

@@ -0,0 +1,12 @@
+/* Capstone Disassembly Engine */
+/* By Dmitry Sibirtsev <sibirtsevdl@gmail.com>, 2024 */
+
+#ifndef CS_ARC_MODULE_H
+#define CS_ARC_MODULE_H
+
+#include "../../utils.h"
+
+cs_err ARC_global_init(cs_struct *ud);
+cs_err ARC_option(cs_struct *handle, cs_opt_type type, size_t value);
+
+#endif