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external/capstone/arch/ARM/ARMAddressingModes.h

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+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically translated source file from LLVM. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Only small edits allowed. */
+/* For multiple similar edits, please create a Patch for the translator. */
+
+/* Capstone's C++ file translator: */
+/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
+
+//===-- ARMAddressingModes.h - ARM Addressing Modes -------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains the ARM addressing mode implementation stuff.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef CS_ARM_ADDRESSINGMODES_H
+#define CS_ARM_ADDRESSINGMODES_H
+
+#include "../../cs_priv.h"
+#include <capstone/platform.h>
+
+#include <assert.h>
+#include "../../MathExtras.h"
+
+#define CONCAT(a, b) CONCAT_(a, b)
+#define CONCAT_(a, b) a##_##b
+
+/// ARM_AM - ARM Addressing Mode Stuff
+// CS namespace begin: ARM_AM
+
+typedef enum ShiftOpc {
+	ARM_AM_no_shift = 0,
+	ARM_AM_asr,
+	ARM_AM_lsl,
+	ARM_AM_lsr,
+	ARM_AM_ror,
+	ARM_AM_rrx,
+	ARM_AM_uxtw
+} ARM_AM_ShiftOpc;
+
+typedef enum AddrOpc { ARM_AM_sub = 0, ARM_AM_add } ARM_AM_AddrOpc;
+
+static inline const char *ARM_AM_getAddrOpcStr(ARM_AM_AddrOpc Op)
+{
+	return Op == ARM_AM_sub ? "-" : "";
+}
+
+static inline const char *ARM_AM_getShiftOpcStr(ARM_AM_ShiftOpc Op)
+{
+	switch (Op) {
+	default:
+		CS_ASSERT_RET_VAL(0 && "Unknown shift opc!", NULL);
+	case ARM_AM_asr:
+		return "asr";
+	case ARM_AM_lsl:
+		return "lsl";
+	case ARM_AM_lsr:
+		return "lsr";
+	case ARM_AM_ror:
+		return "ror";
+	case ARM_AM_rrx:
+		return "rrx";
+	case ARM_AM_uxtw:
+		return "uxtw";
+	}
+}
+
+static inline unsigned ARM_AM_getShiftOpcEncoding(ARM_AM_ShiftOpc Op)
+{
+	switch (Op) {
+	default:
+		CS_ASSERT_RET_VAL(0 && "Unknown shift opc!", 0);
+	case ARM_AM_asr:
+		return 2;
+	case ARM_AM_lsl:
+		return 0;
+	case ARM_AM_lsr:
+		return 1;
+	case ARM_AM_ror:
+		return 3;
+	}
+}
+
+typedef enum AMSubMode {
+	ARM_AM_bad_am_submode = 0,
+	ARM_AM_ia,
+	ARM_AM_ib,
+	ARM_AM_da,
+	ARM_AM_db
+} ARM_AM_SubMode;
+
+static inline const char *ARM_AM_getAMSubModeStr(ARM_AM_SubMode Mode)
+{
+	switch (Mode) {
+	default:
+		CS_ASSERT_RET_VAL(0 && "Unknown addressing sub-mode!", NULL);
+	case ARM_AM_ia:
+		return "ia";
+	case ARM_AM_ib:
+		return "ib";
+	case ARM_AM_da:
+		return "da";
+	case ARM_AM_db:
+		return "db";
+	}
+}
+
+//===--------------------------------------------------------------------===//
+// Addressing Mode #1: shift_operand with registers
+//===--------------------------------------------------------------------===//
+//
+// This 'addressing mode' is used for arithmetic instructions.  It can
+// represent things like:
+//   reg
+//   reg [asr|lsl|lsr|ror|rrx] reg
+//   reg [asr|lsl|lsr|ror|rrx] imm
+//
+// This is stored three operands [rega, regb, opc].  The first is the base
+// reg, the second is the shift amount (or reg0 if not present or imm).  The
+// third operand encodes the shift opcode and the imm if a reg isn't present.
+static inline unsigned ARM_AM_rotr32(unsigned Val, unsigned Amt)
+{
+	CS_ASSERT(Amt <= 32);
+	if (Amt == 32) {
+		return Val;
+	}
+	return (Val >> Amt) |
+	       (Val << ((32 - Amt) &
+			31)); // NOLINT(clang-analyzer-core.BitwiseShift)
+}
+
+static inline unsigned ARM_AM_rotl32(unsigned Val, unsigned Amt)
+{
+	return (Val << Amt) | (Val >> ((32 - Amt) & 31));
+}
+
+static inline unsigned ARM_AM_getSORegOpc(ARM_AM_ShiftOpc ShOp, unsigned Imm)
+{
+	return ShOp | (Imm << 3);
+}
+
+static inline unsigned ARM_AM_getSORegOffset(unsigned Op)
+{
+	return Op >> 3;
+}
+
+static inline ARM_AM_ShiftOpc ARM_AM_getSORegShOp(unsigned Op)
+{
+	return (ARM_AM_ShiftOpc)(Op & 7);
+}
+
+/// getSOImmValImm - Given an encoded imm field for the reg/imm form, return
+/// the 8-bit imm value.
+static inline unsigned ARM_AM_getSOImmValImm(unsigned Imm)
+{
+	return Imm & 0xFF;
+}
+
+/// getSOImmValRot - Given an encoded imm field for the reg/imm form, return
+/// the rotate amount.
+static inline unsigned ARM_AM_getSOImmValRot(unsigned Imm)
+{
+	return (Imm >> 8) * 2;
+}
+
+/// getSOImmValRotate - Try to handle Imm with an immediate shifter operand,
+/// computing the rotate amount to use.  If this immediate value cannot be
+/// handled with a single shifter-op, determine a good rotate amount that will
+/// take a maximal chunk of bits out of the immediate.
+static inline unsigned ARM_AM_getSOImmValRotate(unsigned Imm)
+{
+	// 8-bit (or less) immediates are trivially shifter_operands with a rotate
+	// of zero.
+	if ((Imm & ~255U) == 0)
+		return 0;
+
+	// Use CTZ to compute the rotate amount.
+	unsigned TZ = CountTrailingZeros_32(Imm);
+
+	// Rotate amount must be even.  Something like 0x200 must be rotated 8 bits,
+	// not 9.
+	unsigned RotAmt = TZ & ~1;
+
+	// If we can handle this spread, return it.
+	if ((ARM_AM_rotr32(Imm, RotAmt) & ~255U) == 0)
+		return (32 - RotAmt) & 31; // HW rotates right, not left.
+
+	// For values like 0xF000000F, we should ignore the low 6 bits, then
+	// retry the hunt.
+	if (Imm & 63U) {
+		unsigned TZ2 = CountTrailingZeros_32(Imm & ~63U);
+		unsigned RotAmt2 = TZ2 & ~1;
+		if ((ARM_AM_rotr32(Imm, RotAmt2) & ~255U) == 0)
+			return (32 - RotAmt2) &
+			       31; // HW rotates right, not left.
+	}
+
+	// Otherwise, we have no way to cover this span of bits with a single
+	// shifter_op immediate.  Return a chunk of bits that will be useful to
+	// handle.
+	return (32 - RotAmt) & 31; // HW rotates right, not left.
+}
+
+/// getSOImmVal - Given a 32-bit immediate, if it is something that can fit
+/// into an shifter_operand immediate operand, return the 12-bit encoding for
+/// it.  If not, return -1.
+static inline int ARM_AM_getSOImmVal(unsigned Arg)
+{
+	// 8-bit (or less) immediates are trivially shifter_operands with a rotate
+	// of zero.
+	if ((Arg & ~255U) == 0)
+		return Arg;
+
+	unsigned RotAmt = ARM_AM_getSOImmValRotate(Arg);
+
+	// If this cannot be handled with a single shifter_op, bail out.
+	if (ARM_AM_rotr32(~255U, RotAmt) & Arg)
+		return -1;
+
+	// Encode this correctly.
+	return ARM_AM_rotl32(Arg, RotAmt) | ((RotAmt >> 1) << 8);
+}
+
+/// isSOImmTwoPartVal - Return true if the specified value can be obtained by
+/// or'ing together two SOImmVal's.
+static inline bool ARM_AM_isSOImmTwoPartVal(unsigned V)
+{
+	// If this can be handled with a single shifter_op, bail out.
+	V = ARM_AM_rotr32(~255U, ARM_AM_getSOImmValRotate(V)) & V;
+	if (V == 0)
+		return false;
+
+	// If this can be handled with two shifter_op's, accept.
+	V = ARM_AM_rotr32(~255U, ARM_AM_getSOImmValRotate(V)) & V;
+	return V == 0;
+}
+
+/// getSOImmTwoPartFirst - If V is a value that satisfies isSOImmTwoPartVal,
+/// return the first chunk of it.
+static inline unsigned ARM_AM_getSOImmTwoPartFirst(unsigned V)
+{
+	return ARM_AM_rotr32(255U, ARM_AM_getSOImmValRotate(V)) & V;
+}
+
+/// getSOImmTwoPartSecond - If V is a value that satisfies isSOImmTwoPartVal,
+/// return the second chunk of it.
+static inline unsigned ARM_AM_getSOImmTwoPartSecond(unsigned V)
+{
+	// Mask out the first hunk.
+	V = ARM_AM_rotr32(~255U, ARM_AM_getSOImmValRotate(V)) & V;
+
+	// Take what's left.
+
+	return V;
+}
+
+/// isSOImmTwoPartValNeg - Return true if the specified value can be obtained
+/// by two SOImmVal, that -V = First + Second.
+/// "R+V" can be optimized to (sub (sub R, First), Second).
+/// "R=V" can be optimized to (sub (mvn R, ~(-First)), Second).
+static inline bool ARM_AM_isSOImmTwoPartValNeg(unsigned V)
+{
+	unsigned First;
+	if (!ARM_AM_isSOImmTwoPartVal(-V))
+		return false;
+	// Return false if ~(-First) is not a SoImmval.
+	First = ARM_AM_getSOImmTwoPartFirst(-V);
+	First = ~(-First);
+	return !(ARM_AM_rotr32(~255U, ARM_AM_getSOImmValRotate(First)) & First);
+}
+
+/// getThumbImmValShift - Try to handle Imm with a 8-bit immediate followed
+/// by a left shift. Returns the shift amount to use.
+static inline unsigned ARM_AM_getThumbImmValShift(unsigned Imm)
+{
+	// 8-bit (or less) immediates are trivially immediate operand with a shift
+	// of zero.
+	if ((Imm & ~255U) == 0)
+		return 0;
+
+	// Use CTZ to compute the shift amount.
+	return CountTrailingZeros_32(Imm);
+}
+
+/// isThumbImmShiftedVal - Return true if the specified value can be obtained
+/// by left shifting a 8-bit immediate.
+static inline bool ARM_AM_isThumbImmShiftedVal(unsigned V)
+{
+	// If this can be handled with
+	V = (~255U << ARM_AM_getThumbImmValShift(V)) & V;
+	return V == 0;
+}
+
+/// getThumbImm16ValShift - Try to handle Imm with a 16-bit immediate followed
+/// by a left shift. Returns the shift amount to use.
+static inline unsigned ARM_AM_getThumbImm16ValShift(unsigned Imm)
+{
+	// 16-bit (or less) immediates are trivially immediate operand with a shift
+	// of zero.
+	if ((Imm & ~65535U) == 0)
+		return 0;
+
+	// Use CTZ to compute the shift amount.
+	return CountTrailingZeros_32(Imm);
+}
+
+/// isThumbImm16ShiftedVal - Return true if the specified value can be
+/// obtained by left shifting a 16-bit immediate.
+static inline bool ARM_AM_isThumbImm16ShiftedVal(unsigned V)
+{
+	// If this can be handled with
+	V = (~65535U << ARM_AM_getThumbImm16ValShift(V)) & V;
+	return V == 0;
+}
+
+/// getThumbImmNonShiftedVal - If V is a value that satisfies
+/// isThumbImmShiftedVal, return the non-shiftd value.
+static inline unsigned ARM_AM_getThumbImmNonShiftedVal(unsigned V)
+{
+	return V >> ARM_AM_getThumbImmValShift(V);
+}
+
+/// getT2SOImmValSplat - Return the 12-bit encoded representation
+/// if the specified value can be obtained by splatting the low 8 bits
+/// into every other byte or every byte of a 32-bit value. i.e.,
+///     00000000 00000000 00000000 abcdefgh    control = 0
+///     00000000 abcdefgh 00000000 abcdefgh    control = 1
+///     abcdefgh 00000000 abcdefgh 00000000    control = 2
+///     abcdefgh abcdefgh abcdefgh abcdefgh    control = 3
+/// Return -1 if none of the above apply.
+/// See ARM Reference Manual A6.3.2.
+static inline int ARM_AM_getT2SOImmValSplatVal(unsigned V)
+{
+	unsigned u, Vs, Imm;
+	// control = 0
+	if ((V & 0xffffff00) == 0)
+		return V;
+
+	// If the value is zeroes in the first byte, just shift those off
+	Vs = ((V & 0xff) == 0) ? V >> 8 : V;
+	// Any passing value only has 8 bits of payload, splatted across the word
+	Imm = Vs & 0xff;
+	// Likewise, any passing values have the payload splatted into the 3rd byte
+	u = Imm | (Imm << 16);
+
+	// control = 1 or 2
+	if (Vs == u)
+		return (((Vs == V) ? 1 : 2) << 8) | Imm;
+
+	// control = 3
+	if (Vs == (u | (u << 8)))
+		return (3 << 8) | Imm;
+
+	return -1;
+}
+
+/// getT2SOImmValRotateVal - Return the 12-bit encoded representation if the
+/// specified value is a rotated 8-bit value. Return -1 if no rotation
+/// encoding is possible.
+/// See ARM Reference Manual A6.3.2.
+static inline int ARM_AM_getT2SOImmValRotateVal(unsigned V)
+{
+	unsigned RotAmt = CountLeadingZeros_32(V);
+	if (RotAmt >= 24)
+		return -1;
+
+	// If 'Arg' can be handled with a single shifter_op return the value.
+	if ((ARM_AM_rotr32(0xff000000U, RotAmt) & V) == V)
+		return (ARM_AM_rotr32(V, 24 - RotAmt) & 0x7f) |
+		       ((RotAmt + 8) << 7);
+
+	return -1;
+}
+
+/// getT2SOImmVal - Given a 32-bit immediate, if it is something that can fit
+/// into a Thumb-2 shifter_operand immediate operand, return the 12-bit
+/// encoding for it.  If not, return -1.
+/// See ARM Reference Manual A6.3.2.
+static inline int ARM_AM_getT2SOImmVal(unsigned Arg)
+{
+	// If 'Arg' is an 8-bit splat, then get the encoded value.
+	int Splat = ARM_AM_getT2SOImmValSplatVal(Arg);
+	if (Splat != -1)
+		return Splat;
+
+	// If 'Arg' can be handled with a single shifter_op return the value.
+	int Rot = ARM_AM_getT2SOImmValRotateVal(Arg);
+	if (Rot != -1)
+		return Rot;
+
+	return -1;
+}
+
+static inline unsigned ARM_AM_getT2SOImmValRotate(unsigned V)
+{
+	if ((V & ~255U) == 0)
+		return 0;
+	// Use CTZ to compute the rotate amount.
+	unsigned RotAmt = CountTrailingZeros_32(V);
+	return (32 - RotAmt) & 31;
+}
+
+static inline bool ARM_AM_isT2SOImmTwoPartVal(unsigned Imm)
+{
+	unsigned V = Imm;
+	// Passing values can be any combination of splat values and shifter
+	// values. If this can be handled with a single shifter or splat, bail
+	// out. Those should be handled directly, not with a two-part val.
+	if (ARM_AM_getT2SOImmValSplatVal(V) != -1)
+		return false;
+	V = ARM_AM_rotr32(~255U, ARM_AM_getT2SOImmValRotate(V)) & V;
+	if (V == 0)
+		return false;
+
+	// If this can be handled as an immediate, accept.
+	if (ARM_AM_getT2SOImmVal(V) != -1)
+		return true;
+
+	// Likewise, try masking out a splat value first.
+	V = Imm;
+	if (ARM_AM_getT2SOImmValSplatVal(V & 0xff00ff00U) != -1)
+		V &= ~0xff00ff00U;
+	else if (ARM_AM_getT2SOImmValSplatVal(V & 0x00ff00ffU) != -1)
+		V &= ~0x00ff00ffU;
+	// If what's left can be handled as an immediate, accept.
+	if (ARM_AM_getT2SOImmVal(V) != -1)
+		return true;
+
+	// Otherwise, do not accept.
+	return false;
+}
+
+static inline unsigned ARM_AM_getT2SOImmTwoPartFirst(unsigned Imm)
+{
+	CS_ASSERT(ARM_AM_isT2SOImmTwoPartVal(Imm) &&
+		  "Immedate cannot be encoded as two part immediate!");
+	// Try a shifter operand as one part
+	unsigned V = ARM_AM_rotr32(~255, ARM_AM_getT2SOImmValRotate(Imm)) & Imm;
+	// If the rest is encodable as an immediate, then return it.
+	if (ARM_AM_getT2SOImmVal(V) != -1)
+		return V;
+
+	// Try masking out a splat value first.
+	if (ARM_AM_getT2SOImmValSplatVal(Imm & 0xff00ff00U) != -1)
+		return Imm & 0xff00ff00U;
+
+	// The other splat is all that's left as an option.
+	CS_ASSERT(ARM_AM_getT2SOImmValSplatVal(Imm & 0x00ff00ffU) != -1);
+	return Imm & 0x00ff00ffU;
+}
+
+static inline unsigned ARM_AM_getT2SOImmTwoPartSecond(unsigned Imm)
+{
+	// Mask out the first hunk
+	Imm ^= ARM_AM_getT2SOImmTwoPartFirst(Imm);
+	// Return what's left
+	CS_ASSERT(ARM_AM_getT2SOImmVal(Imm) != -1 &&
+		  "Unable to encode second part of T2 two part SO immediate");
+	return Imm;
+}
+
+//===--------------------------------------------------------------------===//
+// Addressing Mode #2
+//===--------------------------------------------------------------------===//
+//
+// This is used for most simple load/store instructions.
+//
+// addrmode2 := reg +/- reg shop imm
+// addrmode2 := reg +/- imm12
+//
+// The first operand is always a Reg.  The second operand is a reg if in
+// reg/reg form, otherwise it's reg#0.  The third field encodes the operation
+// in bit 12, the immediate in bits 0-11, and the shift op in 13-15. The
+// fourth operand 16-17 encodes the index mode.
+//
+// If this addressing mode is a frame index (before prolog/epilog insertion
+// and code rewriting), this operand will have the form:  FI#, reg0, <offs>
+// with no shift amount for the frame offset.
+//
+static inline unsigned ARM_AM_getAM2Opc(ARM_AM_AddrOpc Opc, unsigned Imm12,
+					ARM_AM_ShiftOpc SO, unsigned IdxMode)
+{
+	CS_ASSERT(Imm12 < (1 << 12) && "Imm too large!");
+	bool isSub = Opc == ARM_AM_sub;
+	return Imm12 | ((int)isSub << 12) | (SO << 13) | (IdxMode << 16);
+}
+
+static inline unsigned ARM_AM_getAM2Offset(unsigned AM2Opc)
+{
+	return AM2Opc & ((1 << 12) - 1);
+}
+
+static inline ARM_AM_AddrOpc ARM_AM_getAM2Op(unsigned AM2Opc)
+{
+	return ((AM2Opc >> 12) & 1) ? ARM_AM_sub : ARM_AM_add;
+}
+
+static inline ARM_AM_ShiftOpc ARM_AM_getAM2ShiftOpc(unsigned AM2Opc)
+{
+	return (ARM_AM_ShiftOpc)((AM2Opc >> 13) & 7);
+}
+
+static inline unsigned ARM_AM_getAM2IdxMode(unsigned AM2Opc)
+{
+	return (AM2Opc >> 16);
+}
+
+//===--------------------------------------------------------------------===//
+// Addressing Mode #3
+//===--------------------------------------------------------------------===//
+//
+// This is used for sign-extending loads, and load/store-pair instructions.
+//
+// addrmode3 := reg +/- reg
+// addrmode3 := reg +/- imm8
+//
+// The first operand is always a Reg.  The second operand is a reg if in
+// reg/reg form, otherwise it's reg#0.  The third field encodes the operation
+// in bit 8, the immediate in bits 0-7. The fourth operand 9-10 encodes the
+// index mode.
+/// getAM3Opc - This function encodes the addrmode3 opc field.
+static inline unsigned ARM_AM_getAM3Opc(ARM_AM_AddrOpc Opc,
+					unsigned char Offset, unsigned IdxMode)
+{
+	bool isSub = Opc == ARM_AM_sub;
+	return ((int)isSub << 8) | Offset | (IdxMode << 9);
+}
+
+static inline unsigned char ARM_AM_getAM3Offset(unsigned AM3Opc)
+{
+	return AM3Opc & 0xFF;
+}
+
+static inline ARM_AM_AddrOpc ARM_AM_getAM3Op(unsigned AM3Opc)
+{
+	return ((AM3Opc >> 8) & 1) ? ARM_AM_sub : ARM_AM_add;
+}
+
+static inline unsigned ARM_AM_getAM3IdxMode(unsigned AM3Opc)
+{
+	return (AM3Opc >> 9);
+}
+
+//===--------------------------------------------------------------------===//
+// Addressing Mode #4
+//===--------------------------------------------------------------------===//
+//
+// This is used for load / store multiple instructions.
+//
+// addrmode4 := reg, <mode>
+//
+// The four modes are:
+//    IA - Increment after
+//    IB - Increment before
+//    DA - Decrement after
+//    DB - Decrement before
+// For VFP instructions, only the IA and DB modes are valid.
+static inline ARM_AM_SubMode ARM_AM_getAM4SubMode(unsigned Mode)
+{
+	return (ARM_AM_SubMode)(Mode & 0x7);
+}
+
+static inline unsigned ARM_AM_getAM4ModeImm(ARM_AM_SubMode SubMode)
+{
+	return (int)SubMode;
+}
+
+//===--------------------------------------------------------------------===//
+// Addressing Mode #5
+//===--------------------------------------------------------------------===//
+//
+// This is used for coprocessor instructions, such as FP load/stores.
+//
+// addrmode5 := reg +/- imm8*4
+//
+// The first operand is always a Reg.  The second operand encodes the
+// operation (add or subtract) in bit 8 and the immediate in bits 0-7.
+/// getAM5Opc - This function encodes the addrmode5 opc field.
+static inline unsigned ARM_AM_getAM5Opc(ARM_AM_AddrOpc Opc,
+					unsigned char Offset)
+{
+	bool isSub = Opc == ARM_AM_sub;
+	return ((int)isSub << 8) | Offset;
+}
+
+static inline unsigned char ARM_AM_getAM5Offset(unsigned AM5Opc)
+{
+	return AM5Opc & 0xFF;
+}
+
+static inline ARM_AM_AddrOpc ARM_AM_getAM5Op(unsigned AM5Opc)
+{
+	return ((AM5Opc >> 8) & 1) ? ARM_AM_sub : ARM_AM_add;
+}
+
+//===--------------------------------------------------------------------===//
+// Addressing Mode #5 FP16
+//===--------------------------------------------------------------------===//
+//
+// This is used for coprocessor instructions, such as 16-bit FP load/stores.
+//
+// addrmode5fp16 := reg +/- imm8*2
+//
+// The first operand is always a Reg.  The second operand encodes the
+// operation (add or subtract) in bit 8 and the immediate in bits 0-7.
+/// getAM5FP16Opc - This function encodes the addrmode5fp16 opc field.
+static inline unsigned ARM_AM_getAM5FP16Opc(ARM_AM_AddrOpc Opc,
+					    unsigned char Offset)
+{
+	bool isSub = Opc == ARM_AM_sub;
+	return ((int)isSub << 8) | Offset;
+}
+
+static inline unsigned char ARM_AM_getAM5FP16Offset(unsigned AM5Opc)
+{
+	return AM5Opc & 0xFF;
+}
+
+static inline ARM_AM_AddrOpc ARM_AM_getAM5FP16Op(unsigned AM5Opc)
+{
+	return ((AM5Opc >> 8) & 1) ? ARM_AM_sub : ARM_AM_add;
+}
+
+//===--------------------------------------------------------------------===//
+// Addressing Mode #6
+//===--------------------------------------------------------------------===//
+//
+// This is used for NEON load / store instructions.
+//
+// addrmode6 := reg with optional alignment
+//
+// This is stored in two operands [regaddr, align].  The first is the
+// address register.  The second operand is the value of the alignment
+// specifier in bytes or zero if no explicit alignment.
+// Valid alignments depend on the specific instruction.
+//===--------------------------------------------------------------------===//
+// NEON/MVE Modified Immediates
+//===--------------------------------------------------------------------===//
+//
+// Several NEON and MVE instructions (e.g., VMOV) take a "modified immediate"
+// vector operand, where a small immediate encoded in the instruction
+// specifies a full NEON vector value.  These modified immediates are
+// represented here as encoded integers.  The low 8 bits hold the immediate
+// value; bit 12 holds the "Op" field of the instruction, and bits 11-8 hold
+// the "Cmode" field of the instruction.  The interfaces below treat the
+// Op and Cmode values as a single 5-bit value.
+static inline unsigned ARM_AM_createVMOVModImm(unsigned OpCmode, unsigned Val)
+{
+	return (OpCmode << 8) | Val;
+}
+
+static inline unsigned ARM_AM_getVMOVModImmOpCmode(unsigned ModImm)
+{
+	return (ModImm >> 8) & 0x1f;
+}
+
+static inline unsigned ARM_AM_getVMOVModImmVal(unsigned ModImm)
+{
+	return ModImm & 0xff;
+}
+
+/// decodeVMOVModImm - Decode a NEON/MVE modified immediate value into the
+/// element value and the element size in bits.  (If the element size is
+/// smaller than the vector, it is splatted into all the elements.)
+static inline uint64_t ARM_AM_decodeVMOVModImm(unsigned ModImm,
+					       unsigned *EltBits)
+{
+	unsigned OpCmode = ARM_AM_getVMOVModImmOpCmode(ModImm);
+	unsigned Imm8 = ARM_AM_getVMOVModImmVal(ModImm);
+	uint64_t Val = 0;
+
+	if (OpCmode == 0xe) {
+		// 8-bit vector elements
+		Val = Imm8;
+		*EltBits = 8;
+	} else if ((OpCmode & 0xc) == 0x8) {
+		// 16-bit vector elements
+		unsigned ByteNum = (OpCmode & 0x6) >> 1;
+		Val = Imm8 << (8 * ByteNum);
+		*EltBits = 16;
+	} else if ((OpCmode & 0x8) == 0) {
+		// 32-bit vector elements, zero with one byte set
+		unsigned ByteNum = (OpCmode & 0x6) >> 1;
+		Val = Imm8 << (8 * ByteNum);
+		*EltBits = 32;
+	} else if ((OpCmode & 0xe) == 0xc) {
+		// 32-bit vector elements, one byte with low bits set
+		unsigned ByteNum = 1 + (OpCmode & 0x1);
+		Val = (Imm8 << (8 * ByteNum)) | (0xffff >> (8 * (2 - ByteNum)));
+		*EltBits = 32;
+	} else if (OpCmode == 0x1e) {
+		// 64-bit vector elements
+		for (unsigned ByteNum = 0; ByteNum < 8; ++ByteNum) {
+			if ((ModImm >> ByteNum) & 1)
+				Val |= (uint64_t)0xff << (8 * ByteNum);
+		}
+		*EltBits = 64;
+	} else {
+		CS_ASSERT_RET_VAL(0 && "Unsupported VMOV immediate", 0);
+	}
+	return Val;
+}
+
+// Generic validation for single-byte immediate (0X00, 00X0, etc).
+static inline bool ARM_AM_isNEONBytesplat(unsigned Value, unsigned Size)
+{
+	CS_ASSERT(Size >= 1 && Size <= 4 && "Invalid size");
+	unsigned count = 0;
+	for (unsigned i = 0; i < Size; ++i) {
+		if (Value & 0xff)
+			count++;
+		Value >>= 8;
+	}
+	return count == 1;
+}
+
+/// Checks if Value is a correct immediate for instructions like VBIC/VORR.
+static inline bool ARM_AM_isNEONi16splat(unsigned Value)
+{
+	if (Value > 0xffff)
+		return false;
+	// i16 value with set bits only in one byte X0 or 0X.
+	return Value == 0 || ARM_AM_isNEONBytesplat(Value, 2);
+}
+
+// Encode NEON 16 bits Splat immediate for instructions like VBIC/VORR
+static inline unsigned ARM_AM_encodeNEONi16splat(unsigned Value)
+{
+	CS_ASSERT(ARM_AM_isNEONi16splat(Value) && "Invalid NEON splat value");
+	if (Value >= 0x100)
+		Value = (Value >> 8) | 0xa00;
+	else
+		Value |= 0x800;
+	return Value;
+}
+
+/// Checks if Value is a correct immediate for instructions like VBIC/VORR.
+static inline bool ARM_AM_isNEONi32splat(unsigned Value)
+{
+	// i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X.
+	return Value == 0 || ARM_AM_isNEONBytesplat(Value, 4);
+}
+
+/// Encode NEON 32 bits Splat immediate for instructions like VBIC/VORR.
+static inline unsigned ARM_AM_encodeNEONi32splat(unsigned Value)
+{
+	CS_ASSERT(ARM_AM_isNEONi32splat(Value) && "Invalid NEON splat value");
+	if (Value >= 0x100 && Value <= 0xff00)
+		Value = (Value >> 8) | 0x200;
+	else if (Value > 0xffff && Value <= 0xff0000)
+		Value = (Value >> 16) | 0x400;
+	else if (Value > 0xffffff)
+		Value = (Value >> 24) | 0x600;
+	return Value;
+}
+
+//===--------------------------------------------------------------------===//
+// Floating-point Immediates
+//
+static inline float ARM_AM_getFPImmFloat(unsigned Imm)
+{
+	// We expect an 8-bit binary encoding of a floating-point number here.
+
+	uint32_t Sign = (Imm >> 7) & 0x1;
+	uint32_t Exp = (Imm >> 4) & 0x7;
+	uint32_t Mantissa = Imm & 0xf;
+
+	//   8-bit FP    IEEE Float Encoding
+	//   abcd efgh   aBbbbbbc defgh000 00000000 00000000
+	//
+	// where B = NOT(b);
+	uint32_t I = 0;
+	I |= Sign << 31;
+	I |= ((Exp & 0x4) != 0 ? 0 : 1) << 30;
+	I |= ((Exp & 0x4) != 0 ? 0x1f : 0) << 25;
+	I |= (Exp & 0x3) << 23;
+	I |= Mantissa << 19;
+	return BitsToFloat(I);
+}
+
+#endif // CS_ARM_ADDRESSINGMODES_H

external/capstone/arch/ARM/ARMBaseInfo.c

@@ -0,0 +1,101 @@
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically translated source file from LLVM. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Only small edits allowed. */
+/* For multiple similar edits, please create a Patch for the translator. */
+
+/* Capstone's C++ file translator: */
+/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
+
+//===-- ARMBaseInfo.cpp - ARM Base encoding information------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file provides basic encoding and assembly information for ARM.
+//
+//===----------------------------------------------------------------------===//
+
+#include <capstone/platform.h>
+
+#include "ARMBaseInfo.h"
+#include "../../utils.h"
+
+#define CONCAT(a, b) CONCAT_(a, b)
+#define CONCAT_(a, b) a##_##b
+
+// CS namespace begin: ARMSysReg
+
+// lookup system register using 12-bit SYSm value.
+// Note: the search is uniqued using M1 mask
+const char *get_pred_mask(ARM_PredBlockMask pred_mask)
+{
+	switch (pred_mask) {
+	default:
+		CS_ASSERT_RET_VAL(0 && "pred_mask not handled.", NULL);
+	case ARM_T:
+		return "T";
+	case ARM_TT:
+		return "TT";
+	case ARM_TE:
+		return "TE";
+	case ARM_TTT:
+		return "TTT";
+	case ARM_TTE:
+		return "TTE";
+	case ARM_TEE:
+		return "TEE";
+	case ARM_TET:
+		return "TET";
+	case ARM_TTTT:
+		return "TTTT";
+	case ARM_TTTE:
+		return "TTTE";
+	case ARM_TTEE:
+		return "TTEE";
+	case ARM_TTET:
+		return "TTET";
+	case ARM_TEEE:
+		return "TEEE";
+	case ARM_TEET:
+		return "TEET";
+	case ARM_TETT:
+		return "TETT";
+	case ARM_TETE:
+		return "TETE";
+	}
+}
+
+#define GET_MCLASSSYSREG_IMPL
+#include "ARMGenSystemRegister.inc"
+
+const ARMSysReg_MClassSysReg *
+ARMSysReg_lookupMClassSysRegBy12bitSYSmValue(unsigned SYSm)
+{
+	return ARMSysReg_lookupMClassSysRegByM1Encoding12(SYSm);
+}
+
+// returns APSR with _<bits> qualifier.
+// Note: ARMv7-M deprecates using MSR APSR without a _<bits> qualifier
+const ARMSysReg_MClassSysReg *
+ARMSysReg_lookupMClassSysRegAPSRNonDeprecated(unsigned SYSm)
+{
+	return ARMSysReg_lookupMClassSysRegByM2M3Encoding8((1 << 9) |
+							   (SYSm & 0xFF));
+}
+
+// lookup system registers using 8-bit SYSm value
+const ARMSysReg_MClassSysReg *
+ARMSysReg_lookupMClassSysRegBy8bitSYSmValue(unsigned SYSm)
+{
+	return ARMSysReg_lookupMClassSysRegByM2M3Encoding8((1 << 8) |
+							   (SYSm & 0xFF));
+}

external/capstone/arch/ARM/ARMBaseInfo.h

@@ -0,0 +1,570 @@
+//===-- ARMBaseInfo.h - Top level definitions for ARM ---*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains small standalone helper functions and enum definitions for
+// the ARM target useful for the compiler back-end and the MC libraries.
+// As such, it deliberately does not include references to LLVM core
+// code gen types, passes, etc..
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef CS_ARM_BASEINFO_H
+#define CS_ARM_BASEINFO_H
+
+#include <assert.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <string.h>
+
+#include "../../MCInstPrinter.h"
+#include "../../cs_priv.h"
+#include "capstone/arm.h"
+
+#define GET_INSTRINFO_ENUM
+#include "ARMGenInstrInfo.inc"
+
+// System Registers
+typedef struct MClassSysReg {
+	const char *Name;
+	arm_sysop_reg sysreg;
+	uint16_t M1Encoding12;
+	uint16_t M2M3Encoding8;
+	uint16_t Encoding;
+	int FeaturesRequired[2];
+} ARMSysReg_MClassSysReg;
+
+// return true if FeaturesRequired are all present in ActiveFeatures
+static inline bool hasRequiredFeatures(const ARMSysReg_MClassSysReg *TheReg,
+				       int ActiveFeatures)
+{
+	return (TheReg->FeaturesRequired[0] == ActiveFeatures ||
+		TheReg->FeaturesRequired[1] == ActiveFeatures);
+}
+
+// returns true if TestFeatures are all present in FeaturesRequired
+static inline bool
+MClassSysReg_isInRequiredFeatures(const ARMSysReg_MClassSysReg *TheReg,
+				  int TestFeatures)
+{
+	return (TheReg->FeaturesRequired[0] == TestFeatures ||
+		TheReg->FeaturesRequired[1] == TestFeatures);
+}
+
+#define GET_SUBTARGETINFO_ENUM
+#include "ARMGenSubtargetInfo.inc"
+
+// lookup system register using 12-bit SYSm value.
+// Note: the search is uniqued using M1 mask
+const ARMSysReg_MClassSysReg *
+ARMSysReg_lookupMClassSysRegBy12bitSYSmValue(unsigned SYSm);
+// returns APSR with _<bits> qualifier.
+// Note: ARMv7-M deprecates using MSR APSR without a _<bits> qualifier
+const ARMSysReg_MClassSysReg *
+ARMSysReg_lookupMClassSysRegAPSRNonDeprecated(unsigned SYSm);
+// lookup system registers using 8-bit SYSm value
+const ARMSysReg_MClassSysReg *
+ARMSysReg_lookupMClassSysRegBy8bitSYSmValue(unsigned SYSm);
+// end namespace ARMSysReg
+
+// Banked Registers
+typedef struct BankedReg {
+	const char *Name;
+	arm_sysop_reg sysreg;
+	uint16_t Encoding;
+} ARMBankedReg_BankedReg;
+
+#define GET_BANKEDREG_DECL
+#define GET_MCLASSSYSREG_DECL
+#include "ARMGenSystemRegister.inc"
+
+typedef enum IMod { ARM_PROC_IE = 2, ARM_PROC_ID = 3 } ARM_PROC_IMod;
+
+typedef enum IFlags {
+	ARM_PROC_F = 1,
+	ARM_PROC_I = 2,
+	ARM_PROC_A = 4
+} ARM_PROC_IFlags;
+
+inline static const char *ARM_PROC_IFlagsToString(unsigned val)
+{
+	switch (val) {
+	default:
+		// llvm_unreachable("Unknown iflags operand");
+	case ARM_PROC_F:
+		return "f";
+	case ARM_PROC_I:
+		return "i";
+	case ARM_PROC_A:
+		return "a";
+	}
+}
+
+inline static const char *ARM_PROC_IModToString(unsigned val)
+{
+	switch (val) {
+	default:
+		CS_ASSERT_RET_VAL("Unknown imod operand", NULL);
+	case ARM_PROC_IE:
+		return "ie";
+	case ARM_PROC_ID:
+		return "id";
+	}
+}
+
+inline static const char *ARM_MB_MemBOptToString(unsigned val, bool HasV8)
+{
+	switch (val) {
+	default:
+		CS_ASSERT_RET_VAL("Unknown memory operation", NULL);
+	case ARM_MB_SY:
+		return "sy";
+	case ARM_MB_ST:
+		return "st";
+	case ARM_MB_LD:
+		return HasV8 ? "ld" : "#0xd";
+	case ARM_MB_RESERVED_12:
+		return "#0xc";
+	case ARM_MB_ISH:
+		return "ish";
+	case ARM_MB_ISHST:
+		return "ishst";
+	case ARM_MB_ISHLD:
+		return HasV8 ? "ishld" : "#0x9";
+	case ARM_MB_RESERVED_8:
+		return "#0x8";
+	case ARM_MB_NSH:
+		return "nsh";
+	case ARM_MB_NSHST:
+		return "nshst";
+	case ARM_MB_NSHLD:
+		return HasV8 ? "nshld" : "#0x5";
+	case ARM_MB_RESERVED_4:
+		return "#0x4";
+	case ARM_MB_OSH:
+		return "osh";
+	case ARM_MB_OSHST:
+		return "oshst";
+	case ARM_MB_OSHLD:
+		return HasV8 ? "oshld" : "#0x1";
+	case ARM_MB_RESERVED_0:
+		return "#0x0";
+	}
+}
+
+typedef enum TraceSyncBOpt { ARM_TSB_CSYNC = 0 } ARM_TSB_TraceSyncBOpt;
+
+inline static const char *ARM_TSB_TraceSyncBOptToString(unsigned val)
+{
+	switch (val) {
+	default:
+		CS_ASSERT_RET_VAL("Unknown trace synchronization barrier operation", NULL);
+	case ARM_TSB_CSYNC:
+		return "csync";
+	}
+}
+
+typedef enum InstSyncBOpt {
+	ARM_ISB_RESERVED_0 = 0,
+	ARM_ISB_RESERVED_1 = 1,
+	ARM_ISB_RESERVED_2 = 2,
+	ARM_ISB_RESERVED_3 = 3,
+	ARM_ISB_RESERVED_4 = 4,
+	ARM_ISB_RESERVED_5 = 5,
+	ARM_ISB_RESERVED_6 = 6,
+	ARM_ISB_RESERVED_7 = 7,
+	ARM_ISB_RESERVED_8 = 8,
+	ARM_ISB_RESERVED_9 = 9,
+	ARM_ISB_RESERVED_10 = 10,
+	ARM_ISB_RESERVED_11 = 11,
+	ARM_ISB_RESERVED_12 = 12,
+	ARM_ISB_RESERVED_13 = 13,
+	ARM_ISB_RESERVED_14 = 14,
+	ARM_ISB_SY = 15
+} ARM_ISB_InstSyncBOpt;
+
+inline static const char *ARM_ISB_InstSyncBOptToString(unsigned val)
+{
+	switch (val) {
+	default:
+		CS_ASSERT_RET_VAL("Unknown memory operation", NULL);
+	case ARM_ISB_RESERVED_0:
+		return "#0x0";
+	case ARM_ISB_RESERVED_1:
+		return "#0x1";
+	case ARM_ISB_RESERVED_2:
+		return "#0x2";
+	case ARM_ISB_RESERVED_3:
+		return "#0x3";
+	case ARM_ISB_RESERVED_4:
+		return "#0x4";
+	case ARM_ISB_RESERVED_5:
+		return "#0x5";
+	case ARM_ISB_RESERVED_6:
+		return "#0x6";
+	case ARM_ISB_RESERVED_7:
+		return "#0x7";
+	case ARM_ISB_RESERVED_8:
+		return "#0x8";
+	case ARM_ISB_RESERVED_9:
+		return "#0x9";
+	case ARM_ISB_RESERVED_10:
+		return "#0xa";
+	case ARM_ISB_RESERVED_11:
+		return "#0xb";
+	case ARM_ISB_RESERVED_12:
+		return "#0xc";
+	case ARM_ISB_RESERVED_13:
+		return "#0xd";
+	case ARM_ISB_RESERVED_14:
+		return "#0xe";
+	case ARM_ISB_SY:
+		return "sy";
+	}
+}
+
+#define GET_REGINFO_ENUM
+#include "ARMGenRegisterInfo.inc"
+
+/// isARMLowRegister - Returns true if the register is a low register (r0-r7).
+///
+static inline bool isARMLowRegister(unsigned Reg)
+{
+	switch (Reg) {
+	case ARM_R0:
+	case ARM_R1:
+	case ARM_R2:
+	case ARM_R3:
+	case ARM_R4:
+	case ARM_R5:
+	case ARM_R6:
+	case ARM_R7:
+		return true;
+	default:
+		return false;
+	}
+}
+
+/// ARMII - This namespace holds all of the target specific flags that
+/// instruction info tracks.
+///
+/// ARM Index Modes
+typedef enum IndexMode {
+	ARMII_IndexModeNone = 0,
+	ARMII_IndexModePre = 1,
+	ARMII_IndexModePost = 2,
+	ARMII_IndexModeUpd = 3
+} ARMII_IndexMode;
+
+/// ARM Addressing Modes
+typedef enum AddrMode {
+	ARMII_AddrModeNone = 0,
+	ARMII_AddrMode1 = 1,
+	ARMII_AddrMode2 = 2,
+	ARMII_AddrMode3 = 3,
+	ARMII_AddrMode4 = 4,
+	ARMII_AddrMode5 = 5,
+	ARMII_AddrMode6 = 6,
+	ARMII_AddrModeT1_1 = 7,
+	ARMII_AddrModeT1_2 = 8,
+	ARMII_AddrModeT1_4 = 9,
+	ARMII_AddrModeT1_s = 10,     // i8 * 4 for pc and sp relative data
+	ARMII_AddrModeT2_i12 = 11,
+	ARMII_AddrModeT2_i8 = 12,    // +/- i8
+	ARMII_AddrModeT2_i8pos = 13, // + i8
+	ARMII_AddrModeT2_i8neg = 14, // - i8
+	ARMII_AddrModeT2_so = 15,
+	ARMII_AddrModeT2_pc = 16,    // +/- i12 for pc relative data
+	ARMII_AddrModeT2_i8s4 = 17,  // i8 * 4
+	ARMII_AddrMode_i12 = 18,
+	ARMII_AddrMode5FP16 = 19,    // i8 * 2
+	ARMII_AddrModeT2_ldrex = 20, // i8 * 4, with unscaled offset in MCInst
+	ARMII_AddrModeT2_i7s4 = 21,  // i7 * 4
+	ARMII_AddrModeT2_i7s2 = 22,  // i7 * 2
+	ARMII_AddrModeT2_i7 = 23,    // i7 * 1
+} ARMII_AddrMode;
+
+inline static const char *ARMII_AddrModeToString(ARMII_AddrMode addrmode)
+{
+	switch (addrmode) {
+	case ARMII_AddrModeNone:
+		return "AddrModeNone";
+	case ARMII_AddrMode1:
+		return "AddrMode1";
+	case ARMII_AddrMode2:
+		return "AddrMode2";
+	case ARMII_AddrMode3:
+		return "AddrMode3";
+	case ARMII_AddrMode4:
+		return "AddrMode4";
+	case ARMII_AddrMode5:
+		return "AddrMode5";
+	case ARMII_AddrMode5FP16:
+		return "AddrMode5FP16";
+	case ARMII_AddrMode6:
+		return "AddrMode6";
+	case ARMII_AddrModeT1_1:
+		return "AddrModeT1_1";
+	case ARMII_AddrModeT1_2:
+		return "AddrModeT1_2";
+	case ARMII_AddrModeT1_4:
+		return "AddrModeT1_4";
+	case ARMII_AddrModeT1_s:
+		return "AddrModeT1_s";
+	case ARMII_AddrModeT2_i12:
+		return "AddrModeT2_i12";
+	case ARMII_AddrModeT2_i8:
+		return "AddrModeT2_i8";
+	case ARMII_AddrModeT2_i8pos:
+		return "AddrModeT2_i8pos";
+	case ARMII_AddrModeT2_i8neg:
+		return "AddrModeT2_i8neg";
+	case ARMII_AddrModeT2_so:
+		return "AddrModeT2_so";
+	case ARMII_AddrModeT2_pc:
+		return "AddrModeT2_pc";
+	case ARMII_AddrModeT2_i8s4:
+		return "AddrModeT2_i8s4";
+	case ARMII_AddrMode_i12:
+		return "AddrMode_i12";
+	case ARMII_AddrModeT2_ldrex:
+		return "AddrModeT2_ldrex";
+	case ARMII_AddrModeT2_i7s4:
+		return "AddrModeT2_i7s4";
+	case ARMII_AddrModeT2_i7s2:
+		return "AddrModeT2_i7s2";
+	case ARMII_AddrModeT2_i7:
+		return "AddrModeT2_i7";
+	}
+}
+
+/// Target Operand Flag enum.
+typedef enum TOF {
+	//===------------------------------------------------------------------===//
+	// ARM Specific MachineOperand flags.
+
+	ARMII_MO_NO_FLAG = 0,
+
+	/// MO_LO16 - On a symbol operand, this represents a relocation containing
+	/// lower 16 bit of the address. Used only via movw instruction.
+	ARMII_MO_LO16 = 0x1,
+
+	/// MO_HI16 - On a symbol operand, this represents a relocation containing
+	/// higher 16 bit of the address. Used only via movt instruction.
+	ARMII_MO_HI16 = 0x2,
+
+	/// MO_OPTION_MASK - Most flags are mutually exclusive; this mask selects
+	/// just that part of the flag set.
+	ARMII_MO_OPTION_MASK = 0x3,
+
+	/// MO_COFFSTUB - On a symbol operand "FOO", this indicates that the
+	/// reference is actually to the ".refptr.FOO" symbol.  This is used for
+	/// stub symbols on windows.
+	ARMII_MO_COFFSTUB = 0x4,
+
+	/// MO_GOT - On a symbol operand, this represents a GOT relative relocation.
+	ARMII_MO_GOT = 0x8,
+
+	/// MO_SBREL - On a symbol operand, this represents a static base relative
+	/// relocation. Used in movw and movt instructions.
+	ARMII_MO_SBREL = 0x10,
+
+	/// MO_DLLIMPORT - On a symbol operand, this represents that the reference
+	/// to the symbol is for an import stub.  This is used for DLL import
+	/// storage class indication on Windows.
+	ARMII_MO_DLLIMPORT = 0x20,
+
+	/// MO_SECREL - On a symbol operand this indicates that the immediate is
+	/// the offset from beginning of section.
+	///
+	/// This is the TLS offset for the COFF/Windows TLS mechanism.
+	ARMII_MO_SECREL = 0x40,
+
+	/// MO_NONLAZY - This is an independent flag, on a symbol operand "FOO" it
+	/// represents a symbol which, if indirect, will get special Darwin mangling
+	/// as a non-lazy-ptr indirect symbol (i.e. "L_FOO$non_lazy_ptr"). Can be
+	/// combined with MO_LO16, MO_HI16 or MO_NO_FLAG (in a constant-pool, for
+	/// example).
+	ARMII_MO_NONLAZY = 0x80,
+
+	// It's undefined behaviour if an enum overflows the range between its
+	// smallest and largest values, but since these are |ed together, it can
+	// happen. Put a sentinel in (values of this enum are stored as "unsigned
+	// char").
+	ARMII_MO_UNUSED_MAXIMUM = 0xff
+} ARMII_TOF;
+
+enum {
+	//===------------------------------------------------------------------===//
+	// Instruction Flags.
+
+	//===------------------------------------------------------------------===//
+	// This four-bit field describes the addressing mode used.
+	ARMII_AddrModeMask =
+		0x1f, // The AddrMode enums are declared in ARMBaseInfo.h
+
+	// IndexMode - Unindex, pre-indexed, or post-indexed are valid for load
+	// and store ops only.  Generic "updating" flag is used for ld/st multiple.
+	// The index mode enums are declared in ARMBaseInfo.h
+	ARMII_IndexModeShift = 5,
+	ARMII_IndexModeMask = 3 << ARMII_IndexModeShift,
+
+	//===------------------------------------------------------------------===//
+	// Instruction encoding formats.
+	//
+	ARMII_FormShift = 7,
+	ARMII_FormMask = 0x3f << ARMII_FormShift,
+
+	// Pseudo instructions
+	ARMII_Pseudo = 0 << ARMII_FormShift,
+
+	// Multiply instructions
+	ARMII_MulFrm = 1 << ARMII_FormShift,
+
+	// Branch instructions
+	ARMII_BrFrm = 2 << ARMII_FormShift,
+	ARMII_BrMiscFrm = 3 << ARMII_FormShift,
+
+	// Data Processing instructions
+	ARMII_DPFrm = 4 << ARMII_FormShift,
+	ARMII_DPSoRegFrm = 5 << ARMII_FormShift,
+
+	// Load and Store
+	ARMII_LdFrm = 6 << ARMII_FormShift,
+	ARMII_StFrm = 7 << ARMII_FormShift,
+	ARMII_LdMiscFrm = 8 << ARMII_FormShift,
+	ARMII_StMiscFrm = 9 << ARMII_FormShift,
+	ARMII_LdStMulFrm = 10 << ARMII_FormShift,
+
+	ARMII_LdStExFrm = 11 << ARMII_FormShift,
+
+	// Miscellaneous arithmetic instructions
+	ARMII_ArithMiscFrm = 12 << ARMII_FormShift,
+	ARMII_SatFrm = 13 << ARMII_FormShift,
+
+	// Extend instructions
+	ARMII_ExtFrm = 14 << ARMII_FormShift,
+
+	// VFP formats
+	ARMII_VFPUnaryFrm = 15 << ARMII_FormShift,
+	ARMII_VFPBinaryFrm = 16 << ARMII_FormShift,
+	ARMII_VFPConv1Frm = 17 << ARMII_FormShift,
+	ARMII_VFPConv2Frm = 18 << ARMII_FormShift,
+	ARMII_VFPConv3Frm = 19 << ARMII_FormShift,
+	ARMII_VFPConv4Frm = 20 << ARMII_FormShift,
+	ARMII_VFPConv5Frm = 21 << ARMII_FormShift,
+	ARMII_VFPLdStFrm = 22 << ARMII_FormShift,
+	ARMII_VFPLdStMulFrm = 23 << ARMII_FormShift,
+	ARMII_VFPMiscFrm = 24 << ARMII_FormShift,
+
+	// Thumb format
+	ARMII_ThumbFrm = 25 << ARMII_FormShift,
+
+	// Miscelleaneous format
+	ARMII_MiscFrm = 26 << ARMII_FormShift,
+
+	// NEON formats
+	ARMII_NGetLnFrm = 27 << ARMII_FormShift,
+	ARMII_NSetLnFrm = 28 << ARMII_FormShift,
+	ARMII_NDupFrm = 29 << ARMII_FormShift,
+	ARMII_NLdStFrm = 30 << ARMII_FormShift,
+	ARMII_N1RegModImmFrm = 31 << ARMII_FormShift,
+	ARMII_N2RegFrm = 32 << ARMII_FormShift,
+	ARMII_NVCVTFrm = 33 << ARMII_FormShift,
+	ARMII_NVDupLnFrm = 34 << ARMII_FormShift,
+	ARMII_N2RegVShLFrm = 35 << ARMII_FormShift,
+	ARMII_N2RegVShRFrm = 36 << ARMII_FormShift,
+	ARMII_N3RegFrm = 37 << ARMII_FormShift,
+	ARMII_N3RegVShFrm = 38 << ARMII_FormShift,
+	ARMII_NVExtFrm = 39 << ARMII_FormShift,
+	ARMII_NVMulSLFrm = 40 << ARMII_FormShift,
+	ARMII_NVTBLFrm = 41 << ARMII_FormShift,
+	ARMII_N3RegCplxFrm = 43 << ARMII_FormShift,
+
+	//===------------------------------------------------------------------===//
+	// Misc flags.
+
+	// UnaryDP - Indicates this is a unary data processing instruction, i.e.
+	// it doesn't have a Rn operand.
+	ARMII_UnaryDP = 1 << 13,
+
+	// Xform16Bit - Indicates this Thumb2 instruction may be transformed into
+	// a 16-bit Thumb instruction if certain conditions are met.
+	ARMII_Xform16Bit = 1 << 14,
+
+	// ThumbArithFlagSetting - The instruction is a 16-bit flag setting Thumb
+	// instruction. Used by the parser to determine whether to require the 'S'
+	// suffix on the mnemonic (when not in an IT block) or preclude it (when
+	// in an IT block).
+	ARMII_ThumbArithFlagSetting = 1 << 19,
+
+	// Whether an instruction can be included in an MVE tail-predicated loop,
+	// though extra validity checks may need to be performed too.
+	ARMII_ValidForTailPredication = 1 << 20,
+
+	// Whether an instruction writes to the top/bottom half of a vector element
+	// and leaves the other half untouched.
+	ARMII_RetainsPreviousHalfElement = 1 << 21,
+
+	// Whether the instruction produces a scalar result from vector operands.
+	ARMII_HorizontalReduction = 1 << 22,
+
+	// Whether this instruction produces a vector result that is larger than
+	// its input, typically reading from the top/bottom halves of the input(s).
+	ARMII_DoubleWidthResult = 1 << 23,
+
+	// The vector element size for MVE instructions. 00 = i8, 01 = i16, 10 = i32
+	// and 11 = i64. This is the largest type if multiple are present, so a
+	// MVE_VMOVLs8bh is ize 01=i16, as it extends from a i8 to a i16. There are
+	// some caveats so cannot be used blindly, such as exchanging VMLADAVA's and
+	// complex instructions, which may use different input lanes.
+	ARMII_VecSizeShift = 24,
+	ARMII_VecSize = 3 << ARMII_VecSizeShift,
+
+	//===------------------------------------------------------------------===//
+	// Code domain.
+	ARMII_DomainShift = 15,
+	ARMII_DomainMask = 15 << ARMII_DomainShift,
+	ARMII_DomainGeneral = 0 << ARMII_DomainShift,
+	ARMII_DomainVFP = 1 << ARMII_DomainShift,
+	ARMII_DomainNEON = 2 << ARMII_DomainShift,
+	ARMII_DomainNEONA8 = 4 << ARMII_DomainShift,
+	ARMII_DomainMVE = 8 << ARMII_DomainShift,
+
+	//===------------------------------------------------------------------===//
+	// Field shifts - such shifts are used to set field while generating
+	// machine instructions.
+	//
+	// FIXME: This list will need adjusting/fixing as the MC code emitter
+	// takes shape and the ARMCodeEmitter.cpp bits go away.
+	ARMII_ShiftTypeShift = 4,
+
+	ARMII_M_BitShift = 5,
+	ARMII_ShiftImmShift = 5,
+	ARMII_ShiftShift = 7,
+	ARMII_N_BitShift = 7,
+	ARMII_ImmHiShift = 8,
+	ARMII_SoRotImmShift = 8,
+	ARMII_RegRsShift = 8,
+	ARMII_ExtRotImmShift = 10,
+	ARMII_RegRdLoShift = 12,
+	ARMII_RegRdShift = 12,
+	ARMII_RegRdHiShift = 16,
+	ARMII_RegRnShift = 16,
+	ARMII_S_BitShift = 20,
+	ARMII_W_BitShift = 21,
+	ARMII_AM3_I_BitShift = 22,
+	ARMII_D_BitShift = 22,
+	ARMII_U_BitShift = 23,
+	ARMII_P_BitShift = 24,
+	ARMII_I_BitShift = 25,
+	ARMII_CondShift = 28
+};
+
+const char *get_pred_mask(ARM_PredBlockMask pred_mask);
+
+#endif // CS_ARM_BASEINFO_H

external/capstone/arch/ARM/ARMDisassemblerExtension.c

@@ -0,0 +1,219 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
+/*    Rot127 <unisono@quyllur.org>, 2022-2023 */
+
+#include "ARMDisassemblerExtension.h"
+#include "ARMBaseInfo.h"
+
+bool ITBlock_push_back(ARM_ITBlock *it, char v)
+{
+	if (it->size >= sizeof(it->ITStates)) {
+		// TODO: consider warning user.
+		it->size = 0;
+	}
+	it->ITStates[it->size] = v;
+	it->size++;
+
+	return true;
+}
+
+// Returns true if the current instruction is in an IT block
+bool ITBlock_instrInITBlock(ARM_ITBlock *it)
+{
+	return (it->size > 0);
+}
+
+// Returns true if current instruction is the last instruction in an IT block
+bool ITBlock_instrLastInITBlock(ARM_ITBlock *it)
+{
+	return (it->size == 1);
+}
+
+// Returns the condition code for instruction in IT block
+unsigned ITBlock_getITCC(ARM_ITBlock *it)
+{
+	unsigned CC = ARMCC_AL;
+
+	if (ITBlock_instrInITBlock(it))
+		CC = it->ITStates[it->size - 1];
+
+	return CC;
+}
+
+// Advances the IT block state to the next T or E
+void ITBlock_advanceITState(ARM_ITBlock *it)
+{
+	it->size--;
+}
+
+// Called when decoding an IT instruction. Sets the IT state for the following
+// instructions that for the IT block. Firstcond and Mask correspond to the
+// fields in the IT instruction encoding.
+void ITBlock_setITState(ARM_ITBlock *it, char Firstcond, char Mask)
+{
+	// (3 - the number of trailing zeros) is the number of then / else.
+	unsigned NumTZ = CountTrailingZeros_8(Mask);
+	unsigned char CCBits = (unsigned char)(Firstcond & 0xf);
+	CS_ASSERT_RET(NumTZ <= 3 && "Invalid IT mask!");
+	// push condition codes onto the stack the correct order for the pops
+	for (unsigned Pos = NumTZ + 1; Pos <= 3; ++Pos) {
+		unsigned Else = (Mask >> Pos) & 1;
+		ITBlock_push_back(it, CCBits ^ Else);
+	}
+	ITBlock_push_back(it, CCBits);
+}
+
+bool VPTBlock_push_back(ARM_VPTBlock *it, char v)
+{
+	if (it->size >= sizeof(it->VPTStates)) {
+		// TODO: consider warning user.
+		it->size = 0;
+	}
+	it->VPTStates[it->size] = v;
+	it->size++;
+
+	return true;
+}
+
+bool VPTBlock_instrInVPTBlock(ARM_VPTBlock *VPT)
+{
+	return VPT->size > 0;
+}
+
+unsigned VPTBlock_getVPTPred(ARM_VPTBlock *VPT)
+{
+	unsigned Pred = ARMVCC_None;
+	if (VPTBlock_instrInVPTBlock(VPT))
+		Pred = VPT->VPTStates[VPT->size - 1];
+	return Pred;
+}
+
+void VPTBlock_advanceVPTState(ARM_VPTBlock *VPT)
+{
+	VPT->size--;
+}
+
+void VPTBlock_setVPTState(ARM_VPTBlock *VPT, char Mask)
+{
+	// (3 - the number of trailing zeros) is the number of then / else.
+	unsigned NumTZ = CountTrailingZeros_8(Mask);
+	CS_ASSERT_RET(NumTZ <= 3 && "Invalid VPT mask!");
+	// push predicates onto the stack the correct order for the pops
+	for (unsigned Pos = NumTZ + 1; Pos <= 3; ++Pos) {
+		bool T = ((Mask >> Pos) & 1) == 0;
+		if (T)
+			VPTBlock_push_back(VPT, ARMVCC_Then);
+		else
+			VPTBlock_push_back(VPT, ARMVCC_Else);
+	}
+	VPTBlock_push_back(VPT, ARMVCC_Then);
+}
+
+// Imported from ARMBaseInstrInfo.h
+//
+/// isValidCoprocessorNumber - decide whether an explicit coprocessor
+/// number is legal in generic instructions like CDP. The answer can
+/// vary with the subtarget.
+bool isValidCoprocessorNumber(MCInst *Inst, unsigned Num)
+{
+	// In Armv7 and Armv8-M CP10 and CP11 clash with VFP/NEON, however, the
+	// coprocessor is still valid for CDP/MCR/MRC and friends. Allowing it is
+	// useful for code which is shared with older architectures which do not
+	// know the new VFP/NEON mnemonics.
+
+	// Armv8-A disallows everything *other* than 111x (CP14 and CP15).
+	if (ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops) &&
+	    (Num & 0xE) != 0xE)
+		return false;
+
+	// Armv8.1-M disallows 100x (CP8,CP9) and 111x (CP14,CP15)
+	// which clash with MVE.
+	if (ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8_1MMainlineOps) &&
+	    ((Num & 0xE) == 0x8 || (Num & 0xE) == 0xE))
+		return false;
+
+	return true;
+}
+
+// Imported from ARMMCTargetDesc.h
+bool ARM_isVpred(arm_op_type op)
+{
+	return op == ARM_OP_VPRED_R || op == ARM_OP_VPRED_N;
+}
+
+// Imported from ARMBaseInstrInfo.h
+//
+// This table shows the VPT instruction variants, i.e. the different
+// mask field encodings, see also B5.6. Predication/conditional execution in
+// the ArmARM.
+bool isVPTOpcode(int Opc)
+{
+	return Opc == ARM_MVE_VPTv16i8 || Opc == ARM_MVE_VPTv16u8 ||
+	       Opc == ARM_MVE_VPTv16s8 || Opc == ARM_MVE_VPTv8i16 ||
+	       Opc == ARM_MVE_VPTv8u16 || Opc == ARM_MVE_VPTv8s16 ||
+	       Opc == ARM_MVE_VPTv4i32 || Opc == ARM_MVE_VPTv4u32 ||
+	       Opc == ARM_MVE_VPTv4s32 || Opc == ARM_MVE_VPTv4f32 ||
+	       Opc == ARM_MVE_VPTv8f16 || Opc == ARM_MVE_VPTv16i8r ||
+	       Opc == ARM_MVE_VPTv16u8r || Opc == ARM_MVE_VPTv16s8r ||
+	       Opc == ARM_MVE_VPTv8i16r || Opc == ARM_MVE_VPTv8u16r ||
+	       Opc == ARM_MVE_VPTv8s16r || Opc == ARM_MVE_VPTv4i32r ||
+	       Opc == ARM_MVE_VPTv4u32r || Opc == ARM_MVE_VPTv4s32r ||
+	       Opc == ARM_MVE_VPTv4f32r || Opc == ARM_MVE_VPTv8f16r ||
+	       Opc == ARM_MVE_VPST;
+}
+
+// Imported from ARMMCTargetDesc.cpp
+bool ARM_isCDECoproc(size_t Coproc, const MCInst *MI)
+{
+	// Unfortunately we don't have ARMTargetInfo in the disassembler, so we have
+	// to rely on feature bits.
+	if (Coproc >= 8)
+		return false;
+
+	return ARM_getFeatureBits(MI->csh->mode,
+				  ARM_FeatureCoprocCDE0 + Coproc);
+}
+
+// Hacky: enable all features for disassembler
+bool ARM_getFeatureBits(unsigned int mode, unsigned int feature)
+{
+	if (feature == ARM_ModeThumb) {
+		if (mode & CS_MODE_THUMB)
+			return true;
+		return false;
+	}
+
+	if (feature == ARM_FeatureDFB)
+		return false;
+
+	if (feature == ARM_FeatureRAS)
+		return false;
+
+	if (feature == ARM_FeatureMClass && (mode & CS_MODE_MCLASS) == 0)
+		return false;
+
+	if ((feature == ARM_HasMVEIntegerOps || feature == ARM_HasMVEFloatOps ||
+	     feature == ARM_FeatureMVEVectorCostFactor1 ||
+	     feature == ARM_FeatureMVEVectorCostFactor2 ||
+	     feature == ARM_FeatureMVEVectorCostFactor4) &&
+	    (mode & CS_MODE_MCLASS) == 0)
+		return false;
+
+	if ((feature == ARM_HasV8Ops || feature == ARM_HasV8_1MMainlineOps ||
+	     feature == ARM_HasV8_1aOps || feature == ARM_HasV8_2aOps ||
+	     feature == ARM_HasV8_3aOps || feature == ARM_HasV8_4aOps ||
+	     feature == ARM_HasV8_5aOps || feature == ARM_HasV8_6aOps ||
+	     feature == ARM_HasV8_7aOps || feature == ARM_HasV8_8aOps ||
+	     feature == ARM_HasV8_9aOps) &&
+	    (mode & CS_MODE_V8) == 0)
+		return false;
+
+	if (feature >= ARM_FeatureCoprocCDE0 &&
+	    feature <= ARM_FeatureCoprocCDE7)
+		// We currently have no way to detect CDE (Custom-Datapath-Extension)
+		// coprocessors.
+		return false;
+
+	// we support everything
+	return true;
+}

external/capstone/arch/ARM/ARMDisassemblerExtension.h

@@ -0,0 +1,49 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
+/*    Rot127 <unisono@quyllur.org>, 2022-2023 */
+
+#ifndef CS_ARM_DISASSEMBLER_EXTENSION_H
+#define CS_ARM_DISASSEMBLER_EXTENSION_H
+
+#include "../../MCDisassembler.h"
+#include "../../MCRegisterInfo.h"
+#include "../../MathExtras.h"
+#include "../../cs_priv.h"
+#include "ARMAddressingModes.h"
+#include "capstone/capstone.h"
+
+unsigned ARM_AM_getAM5FP16Opc(ARM_AM_AddrOpc Opc, unsigned char Offset);
+
+bool ITBlock_push_back(ARM_ITBlock *it, char v);
+
+bool ITBlock_instrInITBlock(ARM_ITBlock *it);
+
+bool ITBlock_instrLastInITBlock(ARM_ITBlock *it);
+
+unsigned ITBlock_getITCC(ARM_ITBlock *it);
+
+void ITBlock_advanceITState(ARM_ITBlock *it);
+
+void ITBlock_setITState(ARM_ITBlock *it, char Firstcond, char Mask);
+
+bool isValidCoprocessorNumber(MCInst *Inst, unsigned Num);
+
+bool ARM_isVpred(arm_op_type op);
+
+bool isVPTOpcode(int Opc);
+
+bool ARM_isCDECoproc(size_t Coproc, const MCInst *MI);
+
+bool VPTBlock_push_back(ARM_VPTBlock *it, char v);
+
+bool VPTBlock_instrInVPTBlock(ARM_VPTBlock *VPT);
+
+unsigned VPTBlock_getVPTPred(ARM_VPTBlock *VPT);
+
+void VPTBlock_advanceVPTState(ARM_VPTBlock *VPT);
+
+void VPTBlock_setVPTState(ARM_VPTBlock *VPT, char Mask);
+
+bool ARM_getFeatureBits(unsigned int mode, unsigned int feature);
+
+#endif // CS_ARM_DISASSEMBLER_EXTENSION_H

external/capstone/arch/ARM/ARMFeatureEnum.inc

@@ -0,0 +1,22 @@
+ARM_FEATURE_IsThumb = 128, ARM_FEATURE_IsARM, ARM_FEATURE_UseNegativeImmediates,
+	ARM_FEATURE_IsThumb2, ARM_FEATURE_HasV8, ARM_FEATURE_HasAES,
+	ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, ARM_FEATURE_HasV7,
+	ARM_FEATURE_IsMClass, ARM_FEATURE_HasPACBTI, ARM_FEATURE_HasV8MBaseline,
+	ARM_FEATURE_HasLOB, ARM_FEATURE_HasV6T2, ARM_FEATURE_HasV5T,
+	ARM_FEATURE_IsNotMClass, ARM_FEATURE_Has8MSecExt, ARM_FEATURE_HasV4T,
+	ARM_FEATURE_PreV8, ARM_FEATURE_HasCLRBHB, ARM_FEATURE_HasV6K,
+	ARM_FEATURE_HasV7Clrex, ARM_FEATURE_HasCRC, ARM_FEATURE_HasCDE,
+	ARM_FEATURE_HasDFB, ARM_FEATURE_HasDB, ARM_FEATURE_HasVirtualization,
+	ARM_FEATURE_HasRAS, ARM_FEATURE_HasVFP2, ARM_FEATURE_HasDPVFP,
+	ARM_FEATURE_HasVFP3, ARM_FEATURE_HasFPRegs, ARM_FEATURE_HasV6M,
+	ARM_FEATURE_HasV6, ARM_FEATURE_HasAcquireRelease, ARM_FEATURE_HasV5TE,
+	ARM_FEATURE_HasDSP, ARM_FEATURE_HasMP, ARM_FEATURE_HasSB,
+	ARM_FEATURE_HasDivideInThumb, ARM_FEATURE_HasDivideInARM,
+	ARM_FEATURE_HasV8_1a, ARM_FEATURE_HasSHA2, ARM_FEATURE_HasTrustZone,
+	ARM_FEATURE_UseNaClTrap, ARM_FEATURE_HasV8_4a, ARM_FEATURE_HasNEON,
+	ARM_FEATURE_HasFullFP16, ARM_FEATURE_HasMVEFloat, ARM_FEATURE_HasV8_3a,
+	ARM_FEATURE_HasFP16, ARM_FEATURE_HasBF16, ARM_FEATURE_HasFPARMv8,
+	ARM_FEATURE_HasVFP4, ARM_FEATURE_HasFP16FML, ARM_FEATURE_HasFPRegs16,
+	ARM_FEATURE_HasV8MMainline, ARM_FEATURE_HasFPRegs64,
+	ARM_FEATURE_HasFPRegsV8_1M, ARM_FEATURE_HasDotProd,
+	ARM_FEATURE_HasMatMulInt8,

external/capstone/arch/ARM/ARMGenCSAliasMnemMap.inc

@@ -0,0 +1,48 @@
+/* Capstone Disassembly Engine, https://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2024 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+	{ ARM_INS_ALIAS_VMOV, "vmov" },
+	{ ARM_INS_ALIAS_NOP, "nop" },
+	{ ARM_INS_ALIAS_YIELD, "yield" },
+	{ ARM_INS_ALIAS_WFE, "wfe" },
+	{ ARM_INS_ALIAS_WFI, "wfi" },
+	{ ARM_INS_ALIAS_SEV, "sev" },
+	{ ARM_INS_ALIAS_SEVL, "sevl" },
+	{ ARM_INS_ALIAS_ESB, "esb" },
+	{ ARM_INS_ALIAS_CSDB, "csdb" },
+	{ ARM_INS_ALIAS_CLRBHB, "clrbhb" },
+	{ ARM_INS_ALIAS_PACBTI, "pacbti" },
+	{ ARM_INS_ALIAS_BTI, "bti" },
+	{ ARM_INS_ALIAS_PAC, "pac" },
+	{ ARM_INS_ALIAS_AUT, "aut" },
+	{ ARM_INS_ALIAS_SSBB, "ssbb" },
+	{ ARM_INS_ALIAS_PSSBB, "pssbb" },
+	{ ARM_INS_ALIAS_DFB, "dfb" },
+	{ ARM_INS_ALIAS_CSETM, "csetm" },
+	{ ARM_INS_ALIAS_CSET, "cset" },
+	{ ARM_INS_ALIAS_CINC, "cinc" },
+	{ ARM_INS_ALIAS_CINV, "cinv" },
+	{ ARM_INS_ALIAS_CNEG, "cneg" },
+	{ ARM_INS_ALIAS_VMLAV, "vmlav" },
+	{ ARM_INS_ALIAS_VMLAVA, "vmlava" },
+	{ ARM_INS_ALIAS_VRMLALVH, "vrmlalvh" },
+	{ ARM_INS_ALIAS_VRMLALVHA, "vrmlalvha" },
+	{ ARM_INS_ALIAS_VMLALV, "vmlalv" },
+	{ ARM_INS_ALIAS_VMLALVA, "vmlalva" },
+	{ ARM_INS_ALIAS_VBIC, "vbic" },
+	{ ARM_INS_ALIAS_VEOR, "veor" },
+	{ ARM_INS_ALIAS_VORN, "vorn" },
+	{ ARM_INS_ALIAS_VORR, "vorr" },
+	{ ARM_INS_ALIAS_VAND, "vand" },
+	{ ARM_INS_ALIAS_VPSEL, "vpsel" },
+	{ ARM_INS_ALIAS_ERET, "eret" },

external/capstone/arch/ARM/ARMGenCSFeatureName.inc

@@ -0,0 +1,80 @@
+/* Capstone Disassembly Engine, https://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2024 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+{ ARM_FEATURE_HASV4T, "HasV4T" },
+{ ARM_FEATURE_HASV5T, "HasV5T" },
+{ ARM_FEATURE_HASV5TE, "HasV5TE" },
+{ ARM_FEATURE_HASV6, "HasV6" },
+{ ARM_FEATURE_HASV6M, "HasV6M" },
+{ ARM_FEATURE_HASV8MBASELINE, "HasV8MBaseline" },
+{ ARM_FEATURE_HASV8MMAINLINE, "HasV8MMainline" },
+{ ARM_FEATURE_HASV8_1MMAINLINE, "HasV8_1MMainline" },
+{ ARM_FEATURE_HASMVEINT, "HasMVEInt" },
+{ ARM_FEATURE_HASMVEFLOAT, "HasMVEFloat" },
+{ ARM_FEATURE_HASCDE, "HasCDE" },
+{ ARM_FEATURE_HASFPREGS, "HasFPRegs" },
+{ ARM_FEATURE_HASFPREGS16, "HasFPRegs16" },
+{ ARM_FEATURE_HASNOFPREGS16, "HasNoFPRegs16" },
+{ ARM_FEATURE_HASFPREGS64, "HasFPRegs64" },
+{ ARM_FEATURE_HASFPREGSV8_1M, "HasFPRegsV8_1M" },
+{ ARM_FEATURE_HASV6T2, "HasV6T2" },
+{ ARM_FEATURE_HASV6K, "HasV6K" },
+{ ARM_FEATURE_HASV7, "HasV7" },
+{ ARM_FEATURE_HASV8, "HasV8" },
+{ ARM_FEATURE_PREV8, "PreV8" },
+{ ARM_FEATURE_HASV8_1A, "HasV8_1a" },
+{ ARM_FEATURE_HASV8_2A, "HasV8_2a" },
+{ ARM_FEATURE_HASV8_3A, "HasV8_3a" },
+{ ARM_FEATURE_HASV8_4A, "HasV8_4a" },
+{ ARM_FEATURE_HASV8_5A, "HasV8_5a" },
+{ ARM_FEATURE_HASV8_6A, "HasV8_6a" },
+{ ARM_FEATURE_HASV8_7A, "HasV8_7a" },
+{ ARM_FEATURE_HASVFP2, "HasVFP2" },
+{ ARM_FEATURE_HASVFP3, "HasVFP3" },
+{ ARM_FEATURE_HASVFP4, "HasVFP4" },
+{ ARM_FEATURE_HASDPVFP, "HasDPVFP" },
+{ ARM_FEATURE_HASFPARMV8, "HasFPARMv8" },
+{ ARM_FEATURE_HASNEON, "HasNEON" },
+{ ARM_FEATURE_HASSHA2, "HasSHA2" },
+{ ARM_FEATURE_HASAES, "HasAES" },
+{ ARM_FEATURE_HASCRYPTO, "HasCrypto" },
+{ ARM_FEATURE_HASDOTPROD, "HasDotProd" },
+{ ARM_FEATURE_HASCRC, "HasCRC" },
+{ ARM_FEATURE_HASRAS, "HasRAS" },
+{ ARM_FEATURE_HASLOB, "HasLOB" },
+{ ARM_FEATURE_HASPACBTI, "HasPACBTI" },
+{ ARM_FEATURE_HASFP16, "HasFP16" },
+{ ARM_FEATURE_HASFULLFP16, "HasFullFP16" },
+{ ARM_FEATURE_HASFP16FML, "HasFP16FML" },
+{ ARM_FEATURE_HASBF16, "HasBF16" },
+{ ARM_FEATURE_HASMATMULINT8, "HasMatMulInt8" },
+{ ARM_FEATURE_HASDIVIDEINTHUMB, "HasDivideInThumb" },
+{ ARM_FEATURE_HASDIVIDEINARM, "HasDivideInARM" },
+{ ARM_FEATURE_HASDSP, "HasDSP" },
+{ ARM_FEATURE_HASDB, "HasDB" },
+{ ARM_FEATURE_HASDFB, "HasDFB" },
+{ ARM_FEATURE_HASV7CLREX, "HasV7Clrex" },
+{ ARM_FEATURE_HASACQUIRERELEASE, "HasAcquireRelease" },
+{ ARM_FEATURE_HASMP, "HasMP" },
+{ ARM_FEATURE_HASVIRTUALIZATION, "HasVirtualization" },
+{ ARM_FEATURE_HASTRUSTZONE, "HasTrustZone" },
+{ ARM_FEATURE_HAS8MSECEXT, "Has8MSecExt" },
+{ ARM_FEATURE_ISTHUMB, "IsThumb" },
+{ ARM_FEATURE_ISTHUMB2, "IsThumb2" },
+{ ARM_FEATURE_ISMCLASS, "IsMClass" },
+{ ARM_FEATURE_ISNOTMCLASS, "IsNotMClass" },
+{ ARM_FEATURE_ISARM, "IsARM" },
+{ ARM_FEATURE_USENACLTRAP, "UseNaClTrap" },
+{ ARM_FEATURE_USENEGATIVEIMMEDIATES, "UseNegativeImmediates" },
+{ ARM_FEATURE_HASSB, "HasSB" },
+{ ARM_FEATURE_HASCLRBHB, "HasCLRBHB" },

external/capstone/arch/ARM/ARMGenCSMappingInsnName.inc

@@ -0,0 +1,650 @@
+/* Capstone Disassembly Engine, https://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2024 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+  "invalid", // ARM_INS_INVALID
+  "asr", // ARM_INS_ASR
+  "it", // ARM_INS_IT
+  "ldrbt", // ARM_INS_LDRBT
+  "ldr", // ARM_INS_LDR
+  "ldrht", // ARM_INS_LDRHT
+  "ldrsbt", // ARM_INS_LDRSBT
+  "ldrsht", // ARM_INS_LDRSHT
+  "ldrt", // ARM_INS_LDRT
+  "lsl", // ARM_INS_LSL
+  "lsr", // ARM_INS_LSR
+  "ror", // ARM_INS_ROR
+  "rrx", // ARM_INS_RRX
+  "strbt", // ARM_INS_STRBT
+  "strt", // ARM_INS_STRT
+  "vld1", // ARM_INS_VLD1
+  "vld2", // ARM_INS_VLD2
+  "vld3", // ARM_INS_VLD3
+  "vld4", // ARM_INS_VLD4
+  "vst1", // ARM_INS_VST1
+  "vst2", // ARM_INS_VST2
+  "vst3", // ARM_INS_VST3
+  "vst4", // ARM_INS_VST4
+  "ldrb", // ARM_INS_LDRB
+  "ldrh", // ARM_INS_LDRH
+  "ldrsb", // ARM_INS_LDRSB
+  "ldrsh", // ARM_INS_LDRSH
+  "movs", // ARM_INS_MOVS
+  "mov", // ARM_INS_MOV
+  "strb", // ARM_INS_STRB
+  "strh", // ARM_INS_STRH
+  "str", // ARM_INS_STR
+  "adc", // ARM_INS_ADC
+  "add", // ARM_INS_ADD
+  "adr", // ARM_INS_ADR
+  "aesd", // ARM_INS_AESD
+  "aese", // ARM_INS_AESE
+  "aesimc", // ARM_INS_AESIMC
+  "aesmc", // ARM_INS_AESMC
+  "and", // ARM_INS_AND
+  "vdot", // ARM_INS_VDOT
+  "vcvt", // ARM_INS_VCVT
+  "vcvtb", // ARM_INS_VCVTB
+  "vcvtt", // ARM_INS_VCVTT
+  "bfc", // ARM_INS_BFC
+  "bfi", // ARM_INS_BFI
+  "bic", // ARM_INS_BIC
+  "bkpt", // ARM_INS_BKPT
+  "bl", // ARM_INS_BL
+  "blx", // ARM_INS_BLX
+  "bx", // ARM_INS_BX
+  "bxj", // ARM_INS_BXJ
+  "b", // ARM_INS_B
+  "cx1", // ARM_INS_CX1
+  "cx1a", // ARM_INS_CX1A
+  "cx1d", // ARM_INS_CX1D
+  "cx1da", // ARM_INS_CX1DA
+  "cx2", // ARM_INS_CX2
+  "cx2a", // ARM_INS_CX2A
+  "cx2d", // ARM_INS_CX2D
+  "cx2da", // ARM_INS_CX2DA
+  "cx3", // ARM_INS_CX3
+  "cx3a", // ARM_INS_CX3A
+  "cx3d", // ARM_INS_CX3D
+  "cx3da", // ARM_INS_CX3DA
+  "vcx1a", // ARM_INS_VCX1A
+  "vcx1", // ARM_INS_VCX1
+  "vcx2a", // ARM_INS_VCX2A
+  "vcx2", // ARM_INS_VCX2
+  "vcx3a", // ARM_INS_VCX3A
+  "vcx3", // ARM_INS_VCX3
+  "cdp", // ARM_INS_CDP
+  "cdp2", // ARM_INS_CDP2
+  "clrex", // ARM_INS_CLREX
+  "clz", // ARM_INS_CLZ
+  "cmn", // ARM_INS_CMN
+  "cmp", // ARM_INS_CMP
+  "cps", // ARM_INS_CPS
+  "crc32b", // ARM_INS_CRC32B
+  "crc32cb", // ARM_INS_CRC32CB
+  "crc32ch", // ARM_INS_CRC32CH
+  "crc32cw", // ARM_INS_CRC32CW
+  "crc32h", // ARM_INS_CRC32H
+  "crc32w", // ARM_INS_CRC32W
+  "dbg", // ARM_INS_DBG
+  "dmb", // ARM_INS_DMB
+  "dsb", // ARM_INS_DSB
+  "eor", // ARM_INS_EOR
+  "eret", // ARM_INS_ERET
+  "vmov", // ARM_INS_VMOV
+  "fldmdbx", // ARM_INS_FLDMDBX
+  "fldmiax", // ARM_INS_FLDMIAX
+  "vmrs", // ARM_INS_VMRS
+  "fstmdbx", // ARM_INS_FSTMDBX
+  "fstmiax", // ARM_INS_FSTMIAX
+  "hint", // ARM_INS_HINT
+  "hlt", // ARM_INS_HLT
+  "hvc", // ARM_INS_HVC
+  "isb", // ARM_INS_ISB
+  "lda", // ARM_INS_LDA
+  "ldab", // ARM_INS_LDAB
+  "ldaex", // ARM_INS_LDAEX
+  "ldaexb", // ARM_INS_LDAEXB
+  "ldaexd", // ARM_INS_LDAEXD
+  "ldaexh", // ARM_INS_LDAEXH
+  "ldah", // ARM_INS_LDAH
+  "ldc2l", // ARM_INS_LDC2L
+  "ldc2", // ARM_INS_LDC2
+  "ldcl", // ARM_INS_LDCL
+  "ldc", // ARM_INS_LDC
+  "ldmda", // ARM_INS_LDMDA
+  "ldmdb", // ARM_INS_LDMDB
+  "ldm", // ARM_INS_LDM
+  "ldmib", // ARM_INS_LDMIB
+  "ldrd", // ARM_INS_LDRD
+  "ldrex", // ARM_INS_LDREX
+  "ldrexb", // ARM_INS_LDREXB
+  "ldrexd", // ARM_INS_LDREXD
+  "ldrexh", // ARM_INS_LDREXH
+  "mcr", // ARM_INS_MCR
+  "mcr2", // ARM_INS_MCR2
+  "mcrr", // ARM_INS_MCRR
+  "mcrr2", // ARM_INS_MCRR2
+  "mla", // ARM_INS_MLA
+  "mls", // ARM_INS_MLS
+  "movt", // ARM_INS_MOVT
+  "movw", // ARM_INS_MOVW
+  "mrc", // ARM_INS_MRC
+  "mrc2", // ARM_INS_MRC2
+  "mrrc", // ARM_INS_MRRC
+  "mrrc2", // ARM_INS_MRRC2
+  "mrs", // ARM_INS_MRS
+  "msr", // ARM_INS_MSR
+  "mul", // ARM_INS_MUL
+  "asrl", // ARM_INS_ASRL
+  "dlstp", // ARM_INS_DLSTP
+  "lctp", // ARM_INS_LCTP
+  "letp", // ARM_INS_LETP
+  "lsll", // ARM_INS_LSLL
+  "lsrl", // ARM_INS_LSRL
+  "sqrshr", // ARM_INS_SQRSHR
+  "sqrshrl", // ARM_INS_SQRSHRL
+  "sqshl", // ARM_INS_SQSHL
+  "sqshll", // ARM_INS_SQSHLL
+  "srshr", // ARM_INS_SRSHR
+  "srshrl", // ARM_INS_SRSHRL
+  "uqrshl", // ARM_INS_UQRSHL
+  "uqrshll", // ARM_INS_UQRSHLL
+  "uqshl", // ARM_INS_UQSHL
+  "uqshll", // ARM_INS_UQSHLL
+  "urshr", // ARM_INS_URSHR
+  "urshrl", // ARM_INS_URSHRL
+  "vabav", // ARM_INS_VABAV
+  "vabd", // ARM_INS_VABD
+  "vabs", // ARM_INS_VABS
+  "vadc", // ARM_INS_VADC
+  "vadci", // ARM_INS_VADCI
+  "vaddlva", // ARM_INS_VADDLVA
+  "vaddlv", // ARM_INS_VADDLV
+  "vaddva", // ARM_INS_VADDVA
+  "vaddv", // ARM_INS_VADDV
+  "vadd", // ARM_INS_VADD
+  "vand", // ARM_INS_VAND
+  "vbic", // ARM_INS_VBIC
+  "vbrsr", // ARM_INS_VBRSR
+  "vcadd", // ARM_INS_VCADD
+  "vcls", // ARM_INS_VCLS
+  "vclz", // ARM_INS_VCLZ
+  "vcmla", // ARM_INS_VCMLA
+  "vcmp", // ARM_INS_VCMP
+  "vcmul", // ARM_INS_VCMUL
+  "vctp", // ARM_INS_VCTP
+  "vcvta", // ARM_INS_VCVTA
+  "vcvtm", // ARM_INS_VCVTM
+  "vcvtn", // ARM_INS_VCVTN
+  "vcvtp", // ARM_INS_VCVTP
+  "vddup", // ARM_INS_VDDUP
+  "vdup", // ARM_INS_VDUP
+  "vdwdup", // ARM_INS_VDWDUP
+  "veor", // ARM_INS_VEOR
+  "vfmas", // ARM_INS_VFMAS
+  "vfma", // ARM_INS_VFMA
+  "vfms", // ARM_INS_VFMS
+  "vhadd", // ARM_INS_VHADD
+  "vhcadd", // ARM_INS_VHCADD
+  "vhsub", // ARM_INS_VHSUB
+  "vidup", // ARM_INS_VIDUP
+  "viwdup", // ARM_INS_VIWDUP
+  "vld20", // ARM_INS_VLD20
+  "vld21", // ARM_INS_VLD21
+  "vld40", // ARM_INS_VLD40
+  "vld41", // ARM_INS_VLD41
+  "vld42", // ARM_INS_VLD42
+  "vld43", // ARM_INS_VLD43
+  "vldrb", // ARM_INS_VLDRB
+  "vldrd", // ARM_INS_VLDRD
+  "vldrh", // ARM_INS_VLDRH
+  "vldrw", // ARM_INS_VLDRW
+  "vmaxav", // ARM_INS_VMAXAV
+  "vmaxa", // ARM_INS_VMAXA
+  "vmaxnmav", // ARM_INS_VMAXNMAV
+  "vmaxnma", // ARM_INS_VMAXNMA
+  "vmaxnmv", // ARM_INS_VMAXNMV
+  "vmaxnm", // ARM_INS_VMAXNM
+  "vmaxv", // ARM_INS_VMAXV
+  "vmax", // ARM_INS_VMAX
+  "vminav", // ARM_INS_VMINAV
+  "vmina", // ARM_INS_VMINA
+  "vminnmav", // ARM_INS_VMINNMAV
+  "vminnma", // ARM_INS_VMINNMA
+  "vminnmv", // ARM_INS_VMINNMV
+  "vminnm", // ARM_INS_VMINNM
+  "vminv", // ARM_INS_VMINV
+  "vmin", // ARM_INS_VMIN
+  "vmladava", // ARM_INS_VMLADAVA
+  "vmladavax", // ARM_INS_VMLADAVAX
+  "vmladav", // ARM_INS_VMLADAV
+  "vmladavx", // ARM_INS_VMLADAVX
+  "vmlaldava", // ARM_INS_VMLALDAVA
+  "vmlaldavax", // ARM_INS_VMLALDAVAX
+  "vmlaldav", // ARM_INS_VMLALDAV
+  "vmlaldavx", // ARM_INS_VMLALDAVX
+  "vmlas", // ARM_INS_VMLAS
+  "vmla", // ARM_INS_VMLA
+  "vmlsdava", // ARM_INS_VMLSDAVA
+  "vmlsdavax", // ARM_INS_VMLSDAVAX
+  "vmlsdav", // ARM_INS_VMLSDAV
+  "vmlsdavx", // ARM_INS_VMLSDAVX
+  "vmlsldava", // ARM_INS_VMLSLDAVA
+  "vmlsldavax", // ARM_INS_VMLSLDAVAX
+  "vmlsldav", // ARM_INS_VMLSLDAV
+  "vmlsldavx", // ARM_INS_VMLSLDAVX
+  "vmovlb", // ARM_INS_VMOVLB
+  "vmovlt", // ARM_INS_VMOVLT
+  "vmovnb", // ARM_INS_VMOVNB
+  "vmovnt", // ARM_INS_VMOVNT
+  "vmulh", // ARM_INS_VMULH
+  "vmullb", // ARM_INS_VMULLB
+  "vmullt", // ARM_INS_VMULLT
+  "vmul", // ARM_INS_VMUL
+  "vmvn", // ARM_INS_VMVN
+  "vneg", // ARM_INS_VNEG
+  "vorn", // ARM_INS_VORN
+  "vorr", // ARM_INS_VORR
+  "vpnot", // ARM_INS_VPNOT
+  "vpsel", // ARM_INS_VPSEL
+  "vpst", // ARM_INS_VPST
+  "vpt", // ARM_INS_VPT
+  "vqabs", // ARM_INS_VQABS
+  "vqadd", // ARM_INS_VQADD
+  "vqdmladhx", // ARM_INS_VQDMLADHX
+  "vqdmladh", // ARM_INS_VQDMLADH
+  "vqdmlah", // ARM_INS_VQDMLAH
+  "vqdmlash", // ARM_INS_VQDMLASH
+  "vqdmlsdhx", // ARM_INS_VQDMLSDHX
+  "vqdmlsdh", // ARM_INS_VQDMLSDH
+  "vqdmulh", // ARM_INS_VQDMULH
+  "vqdmullb", // ARM_INS_VQDMULLB
+  "vqdmullt", // ARM_INS_VQDMULLT
+  "vqmovnb", // ARM_INS_VQMOVNB
+  "vqmovnt", // ARM_INS_VQMOVNT
+  "vqmovunb", // ARM_INS_VQMOVUNB
+  "vqmovunt", // ARM_INS_VQMOVUNT
+  "vqneg", // ARM_INS_VQNEG
+  "vqrdmladhx", // ARM_INS_VQRDMLADHX
+  "vqrdmladh", // ARM_INS_VQRDMLADH
+  "vqrdmlah", // ARM_INS_VQRDMLAH
+  "vqrdmlash", // ARM_INS_VQRDMLASH
+  "vqrdmlsdhx", // ARM_INS_VQRDMLSDHX
+  "vqrdmlsdh", // ARM_INS_VQRDMLSDH
+  "vqrdmulh", // ARM_INS_VQRDMULH
+  "vqrshl", // ARM_INS_VQRSHL
+  "vqrshrnb", // ARM_INS_VQRSHRNB
+  "vqrshrnt", // ARM_INS_VQRSHRNT
+  "vqrshrunb", // ARM_INS_VQRSHRUNB
+  "vqrshrunt", // ARM_INS_VQRSHRUNT
+  "vqshlu", // ARM_INS_VQSHLU
+  "vqshl", // ARM_INS_VQSHL
+  "vqshrnb", // ARM_INS_VQSHRNB
+  "vqshrnt", // ARM_INS_VQSHRNT
+  "vqshrunb", // ARM_INS_VQSHRUNB
+  "vqshrunt", // ARM_INS_VQSHRUNT
+  "vqsub", // ARM_INS_VQSUB
+  "vrev16", // ARM_INS_VREV16
+  "vrev32", // ARM_INS_VREV32
+  "vrev64", // ARM_INS_VREV64
+  "vrhadd", // ARM_INS_VRHADD
+  "vrinta", // ARM_INS_VRINTA
+  "vrintm", // ARM_INS_VRINTM
+  "vrintn", // ARM_INS_VRINTN
+  "vrintp", // ARM_INS_VRINTP
+  "vrintx", // ARM_INS_VRINTX
+  "vrintz", // ARM_INS_VRINTZ
+  "vrmlaldavha", // ARM_INS_VRMLALDAVHA
+  "vrmlaldavhax", // ARM_INS_VRMLALDAVHAX
+  "vrmlaldavh", // ARM_INS_VRMLALDAVH
+  "vrmlaldavhx", // ARM_INS_VRMLALDAVHX
+  "vrmlsldavha", // ARM_INS_VRMLSLDAVHA
+  "vrmlsldavhax", // ARM_INS_VRMLSLDAVHAX
+  "vrmlsldavh", // ARM_INS_VRMLSLDAVH
+  "vrmlsldavhx", // ARM_INS_VRMLSLDAVHX
+  "vrmulh", // ARM_INS_VRMULH
+  "vrshl", // ARM_INS_VRSHL
+  "vrshrnb", // ARM_INS_VRSHRNB
+  "vrshrnt", // ARM_INS_VRSHRNT
+  "vrshr", // ARM_INS_VRSHR
+  "vsbc", // ARM_INS_VSBC
+  "vsbci", // ARM_INS_VSBCI
+  "vshlc", // ARM_INS_VSHLC
+  "vshllb", // ARM_INS_VSHLLB
+  "vshllt", // ARM_INS_VSHLLT
+  "vshl", // ARM_INS_VSHL
+  "vshrnb", // ARM_INS_VSHRNB
+  "vshrnt", // ARM_INS_VSHRNT
+  "vshr", // ARM_INS_VSHR
+  "vsli", // ARM_INS_VSLI
+  "vsri", // ARM_INS_VSRI
+  "vst20", // ARM_INS_VST20
+  "vst21", // ARM_INS_VST21
+  "vst40", // ARM_INS_VST40
+  "vst41", // ARM_INS_VST41
+  "vst42", // ARM_INS_VST42
+  "vst43", // ARM_INS_VST43
+  "vstrb", // ARM_INS_VSTRB
+  "vstrd", // ARM_INS_VSTRD
+  "vstrh", // ARM_INS_VSTRH
+  "vstrw", // ARM_INS_VSTRW
+  "vsub", // ARM_INS_VSUB
+  "wlstp", // ARM_INS_WLSTP
+  "mvn", // ARM_INS_MVN
+  "orr", // ARM_INS_ORR
+  "pkhbt", // ARM_INS_PKHBT
+  "pkhtb", // ARM_INS_PKHTB
+  "pldw", // ARM_INS_PLDW
+  "pld", // ARM_INS_PLD
+  "pli", // ARM_INS_PLI
+  "qadd", // ARM_INS_QADD
+  "qadd16", // ARM_INS_QADD16
+  "qadd8", // ARM_INS_QADD8
+  "qasx", // ARM_INS_QASX
+  "qdadd", // ARM_INS_QDADD
+  "qdsub", // ARM_INS_QDSUB
+  "qsax", // ARM_INS_QSAX
+  "qsub", // ARM_INS_QSUB
+  "qsub16", // ARM_INS_QSUB16
+  "qsub8", // ARM_INS_QSUB8
+  "rbit", // ARM_INS_RBIT
+  "rev", // ARM_INS_REV
+  "rev16", // ARM_INS_REV16
+  "revsh", // ARM_INS_REVSH
+  "rfeda", // ARM_INS_RFEDA
+  "rfedb", // ARM_INS_RFEDB
+  "rfeia", // ARM_INS_RFEIA
+  "rfeib", // ARM_INS_RFEIB
+  "rsb", // ARM_INS_RSB
+  "rsc", // ARM_INS_RSC
+  "sadd16", // ARM_INS_SADD16
+  "sadd8", // ARM_INS_SADD8
+  "sasx", // ARM_INS_SASX
+  "sb", // ARM_INS_SB
+  "sbc", // ARM_INS_SBC
+  "sbfx", // ARM_INS_SBFX
+  "sdiv", // ARM_INS_SDIV
+  "sel", // ARM_INS_SEL
+  "setend", // ARM_INS_SETEND
+  "setpan", // ARM_INS_SETPAN
+  "sha1c", // ARM_INS_SHA1C
+  "sha1h", // ARM_INS_SHA1H
+  "sha1m", // ARM_INS_SHA1M
+  "sha1p", // ARM_INS_SHA1P
+  "sha1su0", // ARM_INS_SHA1SU0
+  "sha1su1", // ARM_INS_SHA1SU1
+  "sha256h", // ARM_INS_SHA256H
+  "sha256h2", // ARM_INS_SHA256H2
+  "sha256su0", // ARM_INS_SHA256SU0
+  "sha256su1", // ARM_INS_SHA256SU1
+  "shadd16", // ARM_INS_SHADD16
+  "shadd8", // ARM_INS_SHADD8
+  "shasx", // ARM_INS_SHASX
+  "shsax", // ARM_INS_SHSAX
+  "shsub16", // ARM_INS_SHSUB16
+  "shsub8", // ARM_INS_SHSUB8
+  "smc", // ARM_INS_SMC
+  "smlabb", // ARM_INS_SMLABB
+  "smlabt", // ARM_INS_SMLABT
+  "smlad", // ARM_INS_SMLAD
+  "smladx", // ARM_INS_SMLADX
+  "smlal", // ARM_INS_SMLAL
+  "smlalbb", // ARM_INS_SMLALBB
+  "smlalbt", // ARM_INS_SMLALBT
+  "smlald", // ARM_INS_SMLALD
+  "smlaldx", // ARM_INS_SMLALDX
+  "smlaltb", // ARM_INS_SMLALTB
+  "smlaltt", // ARM_INS_SMLALTT
+  "smlatb", // ARM_INS_SMLATB
+  "smlatt", // ARM_INS_SMLATT
+  "smlawb", // ARM_INS_SMLAWB
+  "smlawt", // ARM_INS_SMLAWT
+  "smlsd", // ARM_INS_SMLSD
+  "smlsdx", // ARM_INS_SMLSDX
+  "smlsld", // ARM_INS_SMLSLD
+  "smlsldx", // ARM_INS_SMLSLDX
+  "smmla", // ARM_INS_SMMLA
+  "smmlar", // ARM_INS_SMMLAR
+  "smmls", // ARM_INS_SMMLS
+  "smmlsr", // ARM_INS_SMMLSR
+  "smmul", // ARM_INS_SMMUL
+  "smmulr", // ARM_INS_SMMULR
+  "smuad", // ARM_INS_SMUAD
+  "smuadx", // ARM_INS_SMUADX
+  "smulbb", // ARM_INS_SMULBB
+  "smulbt", // ARM_INS_SMULBT
+  "smull", // ARM_INS_SMULL
+  "smultb", // ARM_INS_SMULTB
+  "smultt", // ARM_INS_SMULTT
+  "smulwb", // ARM_INS_SMULWB
+  "smulwt", // ARM_INS_SMULWT
+  "smusd", // ARM_INS_SMUSD
+  "smusdx", // ARM_INS_SMUSDX
+  "srsda", // ARM_INS_SRSDA
+  "srsdb", // ARM_INS_SRSDB
+  "srsia", // ARM_INS_SRSIA
+  "srsib", // ARM_INS_SRSIB
+  "ssat", // ARM_INS_SSAT
+  "ssat16", // ARM_INS_SSAT16
+  "ssax", // ARM_INS_SSAX
+  "ssub16", // ARM_INS_SSUB16
+  "ssub8", // ARM_INS_SSUB8
+  "stc2l", // ARM_INS_STC2L
+  "stc2", // ARM_INS_STC2
+  "stcl", // ARM_INS_STCL
+  "stc", // ARM_INS_STC
+  "stl", // ARM_INS_STL
+  "stlb", // ARM_INS_STLB
+  "stlex", // ARM_INS_STLEX
+  "stlexb", // ARM_INS_STLEXB
+  "stlexd", // ARM_INS_STLEXD
+  "stlexh", // ARM_INS_STLEXH
+  "stlh", // ARM_INS_STLH
+  "stmda", // ARM_INS_STMDA
+  "stmdb", // ARM_INS_STMDB
+  "stm", // ARM_INS_STM
+  "stmib", // ARM_INS_STMIB
+  "strd", // ARM_INS_STRD
+  "strex", // ARM_INS_STREX
+  "strexb", // ARM_INS_STREXB
+  "strexd", // ARM_INS_STREXD
+  "strexh", // ARM_INS_STREXH
+  "strht", // ARM_INS_STRHT
+  "sub", // ARM_INS_SUB
+  "svc", // ARM_INS_SVC
+  "swp", // ARM_INS_SWP
+  "swpb", // ARM_INS_SWPB
+  "sxtab", // ARM_INS_SXTAB
+  "sxtab16", // ARM_INS_SXTAB16
+  "sxtah", // ARM_INS_SXTAH
+  "sxtb", // ARM_INS_SXTB
+  "sxtb16", // ARM_INS_SXTB16
+  "sxth", // ARM_INS_SXTH
+  "teq", // ARM_INS_TEQ
+  "trap", // ARM_INS_TRAP
+  "tsb", // ARM_INS_TSB
+  "tst", // ARM_INS_TST
+  "uadd16", // ARM_INS_UADD16
+  "uadd8", // ARM_INS_UADD8
+  "uasx", // ARM_INS_UASX
+  "ubfx", // ARM_INS_UBFX
+  "udf", // ARM_INS_UDF
+  "udiv", // ARM_INS_UDIV
+  "uhadd16", // ARM_INS_UHADD16
+  "uhadd8", // ARM_INS_UHADD8
+  "uhasx", // ARM_INS_UHASX
+  "uhsax", // ARM_INS_UHSAX
+  "uhsub16", // ARM_INS_UHSUB16
+  "uhsub8", // ARM_INS_UHSUB8
+  "umaal", // ARM_INS_UMAAL
+  "umlal", // ARM_INS_UMLAL
+  "umull", // ARM_INS_UMULL
+  "uqadd16", // ARM_INS_UQADD16
+  "uqadd8", // ARM_INS_UQADD8
+  "uqasx", // ARM_INS_UQASX
+  "uqsax", // ARM_INS_UQSAX
+  "uqsub16", // ARM_INS_UQSUB16
+  "uqsub8", // ARM_INS_UQSUB8
+  "usad8", // ARM_INS_USAD8
+  "usada8", // ARM_INS_USADA8
+  "usat", // ARM_INS_USAT
+  "usat16", // ARM_INS_USAT16
+  "usax", // ARM_INS_USAX
+  "usub16", // ARM_INS_USUB16
+  "usub8", // ARM_INS_USUB8
+  "uxtab", // ARM_INS_UXTAB
+  "uxtab16", // ARM_INS_UXTAB16
+  "uxtah", // ARM_INS_UXTAH
+  "uxtb", // ARM_INS_UXTB
+  "uxtb16", // ARM_INS_UXTB16
+  "uxth", // ARM_INS_UXTH
+  "vabal", // ARM_INS_VABAL
+  "vaba", // ARM_INS_VABA
+  "vabdl", // ARM_INS_VABDL
+  "vacge", // ARM_INS_VACGE
+  "vacgt", // ARM_INS_VACGT
+  "vaddhn", // ARM_INS_VADDHN
+  "vaddl", // ARM_INS_VADDL
+  "vaddw", // ARM_INS_VADDW
+  "vfmab", // ARM_INS_VFMAB
+  "vfmat", // ARM_INS_VFMAT
+  "vbif", // ARM_INS_VBIF
+  "vbit", // ARM_INS_VBIT
+  "vbsl", // ARM_INS_VBSL
+  "vceq", // ARM_INS_VCEQ
+  "vcge", // ARM_INS_VCGE
+  "vcgt", // ARM_INS_VCGT
+  "vcle", // ARM_INS_VCLE
+  "vclt", // ARM_INS_VCLT
+  "vcmpe", // ARM_INS_VCMPE
+  "vcnt", // ARM_INS_VCNT
+  "vdiv", // ARM_INS_VDIV
+  "vext", // ARM_INS_VEXT
+  "vfmal", // ARM_INS_VFMAL
+  "vfmsl", // ARM_INS_VFMSL
+  "vfnma", // ARM_INS_VFNMA
+  "vfnms", // ARM_INS_VFNMS
+  "vins", // ARM_INS_VINS
+  "vjcvt", // ARM_INS_VJCVT
+  "vldmdb", // ARM_INS_VLDMDB
+  "vldmia", // ARM_INS_VLDMIA
+  "vldr", // ARM_INS_VLDR
+  "vlldm", // ARM_INS_VLLDM
+  "vlstm", // ARM_INS_VLSTM
+  "vmlal", // ARM_INS_VMLAL
+  "vmls", // ARM_INS_VMLS
+  "vmlsl", // ARM_INS_VMLSL
+  "vmmla", // ARM_INS_VMMLA
+  "vmovx", // ARM_INS_VMOVX
+  "vmovl", // ARM_INS_VMOVL
+  "vmovn", // ARM_INS_VMOVN
+  "vmsr", // ARM_INS_VMSR
+  "vmull", // ARM_INS_VMULL
+  "vnmla", // ARM_INS_VNMLA
+  "vnmls", // ARM_INS_VNMLS
+  "vnmul", // ARM_INS_VNMUL
+  "vpadal", // ARM_INS_VPADAL
+  "vpaddl", // ARM_INS_VPADDL
+  "vpadd", // ARM_INS_VPADD
+  "vpmax", // ARM_INS_VPMAX
+  "vpmin", // ARM_INS_VPMIN
+  "vqdmlal", // ARM_INS_VQDMLAL
+  "vqdmlsl", // ARM_INS_VQDMLSL
+  "vqdmull", // ARM_INS_VQDMULL
+  "vqmovun", // ARM_INS_VQMOVUN
+  "vqmovn", // ARM_INS_VQMOVN
+  "vqrdmlsh", // ARM_INS_VQRDMLSH
+  "vqrshrn", // ARM_INS_VQRSHRN
+  "vqrshrun", // ARM_INS_VQRSHRUN
+  "vqshrn", // ARM_INS_VQSHRN
+  "vqshrun", // ARM_INS_VQSHRUN
+  "vraddhn", // ARM_INS_VRADDHN
+  "vrecpe", // ARM_INS_VRECPE
+  "vrecps", // ARM_INS_VRECPS
+  "vrintr", // ARM_INS_VRINTR
+  "vrshrn", // ARM_INS_VRSHRN
+  "vrsqrte", // ARM_INS_VRSQRTE
+  "vrsqrts", // ARM_INS_VRSQRTS
+  "vrsra", // ARM_INS_VRSRA
+  "vrsubhn", // ARM_INS_VRSUBHN
+  "vscclrm", // ARM_INS_VSCCLRM
+  "vsdot", // ARM_INS_VSDOT
+  "vseleq", // ARM_INS_VSELEQ
+  "vselge", // ARM_INS_VSELGE
+  "vselgt", // ARM_INS_VSELGT
+  "vselvs", // ARM_INS_VSELVS
+  "vshll", // ARM_INS_VSHLL
+  "vshrn", // ARM_INS_VSHRN
+  "vsmmla", // ARM_INS_VSMMLA
+  "vsqrt", // ARM_INS_VSQRT
+  "vsra", // ARM_INS_VSRA
+  "vstmdb", // ARM_INS_VSTMDB
+  "vstmia", // ARM_INS_VSTMIA
+  "vstr", // ARM_INS_VSTR
+  "vsubhn", // ARM_INS_VSUBHN
+  "vsubl", // ARM_INS_VSUBL
+  "vsubw", // ARM_INS_VSUBW
+  "vsudot", // ARM_INS_VSUDOT
+  "vswp", // ARM_INS_VSWP
+  "vtbl", // ARM_INS_VTBL
+  "vtbx", // ARM_INS_VTBX
+  "vcvtr", // ARM_INS_VCVTR
+  "vtrn", // ARM_INS_VTRN
+  "vtst", // ARM_INS_VTST
+  "vudot", // ARM_INS_VUDOT
+  "vummla", // ARM_INS_VUMMLA
+  "vusdot", // ARM_INS_VUSDOT
+  "vusmmla", // ARM_INS_VUSMMLA
+  "vuzp", // ARM_INS_VUZP
+  "vzip", // ARM_INS_VZIP
+  "addw", // ARM_INS_ADDW
+  "aut", // ARM_INS_AUT
+  "autg", // ARM_INS_AUTG
+  "bfl", // ARM_INS_BFL
+  "bflx", // ARM_INS_BFLX
+  "bf", // ARM_INS_BF
+  "bfcsel", // ARM_INS_BFCSEL
+  "bfx", // ARM_INS_BFX
+  "bti", // ARM_INS_BTI
+  "bxaut", // ARM_INS_BXAUT
+  "clrm", // ARM_INS_CLRM
+  "csel", // ARM_INS_CSEL
+  "csinc", // ARM_INS_CSINC
+  "csinv", // ARM_INS_CSINV
+  "csneg", // ARM_INS_CSNEG
+  "dcps1", // ARM_INS_DCPS1
+  "dcps2", // ARM_INS_DCPS2
+  "dcps3", // ARM_INS_DCPS3
+  "dls", // ARM_INS_DLS
+  "le", // ARM_INS_LE
+  "orn", // ARM_INS_ORN
+  "pac", // ARM_INS_PAC
+  "pacbti", // ARM_INS_PACBTI
+  "pacg", // ARM_INS_PACG
+  "sg", // ARM_INS_SG
+  "subs", // ARM_INS_SUBS
+  "subw", // ARM_INS_SUBW
+  "tbb", // ARM_INS_TBB
+  "tbh", // ARM_INS_TBH
+  "tt", // ARM_INS_TT
+  "tta", // ARM_INS_TTA
+  "ttat", // ARM_INS_TTAT
+  "ttt", // ARM_INS_TTT
+  "wls", // ARM_INS_WLS
+  "blxns", // ARM_INS_BLXNS
+  "bxns", // ARM_INS_BXNS
+  "cbnz", // ARM_INS_CBNZ
+  "cbz", // ARM_INS_CBZ
+  "pop", // ARM_INS_POP
+  "push", // ARM_INS_PUSH
+  "__brkdiv0", // ARM_INS___BRKDIV0

external/capstone/arch/ARM/ARMGenCSOpGroup.inc

@@ -0,0 +1,115 @@
+/* Capstone Disassembly Engine, https://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2024 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+  ARM_OP_GROUP_LdStmModeOperand = 0,
+  ARM_OP_GROUP_MandatoryInvertedPredicateOperand = 1,
+  ARM_OP_GROUP_RegImmShift = 2,
+  ARM_OP_GROUP_Operand = 3,
+  ARM_OP_GROUP_ModImmOperand = 4,
+  ARM_OP_GROUP_PredicateOperand = 5,
+  ARM_OP_GROUP_SORegImmOperand = 6,
+  ARM_OP_GROUP_SORegRegOperand = 7,
+  ARM_OP_GROUP_SBitModifierOperand = 8,
+  ARM_OP_GROUP_AddrModeImm12Operand_0 = 9,
+  ARM_OP_GROUP_AddrMode2Operand = 10,
+  ARM_OP_GROUP_CPInstOperand = 11,
+  ARM_OP_GROUP_MandatoryPredicateOperand = 12,
+  ARM_OP_GROUP_ThumbITMask = 13,
+  ARM_OP_GROUP_RegisterList = 14,
+  ARM_OP_GROUP_AddrMode7Operand = 15,
+  ARM_OP_GROUP_GPRPairOperand = 16,
+  ARM_OP_GROUP_AddrMode3Operand_0 = 17,
+  ARM_OP_GROUP_PCLabel = 18,
+  ARM_OP_GROUP_AddrModePCOperand = 19,
+  ARM_OP_GROUP_AddrMode2OffsetOperand = 20,
+  ARM_OP_GROUP_AddrMode3OffsetOperand = 21,
+  ARM_OP_GROUP_AddrMode6Operand = 22,
+  ARM_OP_GROUP_VectorListThreeAllLanes = 23,
+  ARM_OP_GROUP_VectorListThreeSpacedAllLanes = 24,
+  ARM_OP_GROUP_VectorListThree = 25,
+  ARM_OP_GROUP_VectorListThreeSpaced = 26,
+  ARM_OP_GROUP_VectorListFourAllLanes = 27,
+  ARM_OP_GROUP_VectorListFourSpacedAllLanes = 28,
+  ARM_OP_GROUP_VectorListFour = 29,
+  ARM_OP_GROUP_VectorListFourSpaced = 30,
+  ARM_OP_GROUP_T2SOOperand = 31,
+  ARM_OP_GROUP_T2AddrModeImm8Operand_0 = 32,
+  ARM_OP_GROUP_T2AddrModeImm8OffsetOperand = 33,
+  ARM_OP_GROUP_T2AddrModeImm8Operand_1 = 34,
+  ARM_OP_GROUP_AdrLabelOperand_0 = 35,
+  ARM_OP_GROUP_VectorIndex = 36,
+  ARM_OP_GROUP_BitfieldInvMaskImmOperand = 37,
+  ARM_OP_GROUP_PImmediate = 38,
+  ARM_OP_GROUP_VPTPredicateOperand = 39,
+  ARM_OP_GROUP_CImmediate = 40,
+  ARM_OP_GROUP_CPSIMod = 41,
+  ARM_OP_GROUP_CPSIFlag = 42,
+  ARM_OP_GROUP_MemBOption = 43,
+  ARM_OP_GROUP_FPImmOperand = 44,
+  ARM_OP_GROUP_InstSyncBOption = 45,
+  ARM_OP_GROUP_AddrMode5Operand_0 = 46,
+  ARM_OP_GROUP_CoprocOptionImm = 47,
+  ARM_OP_GROUP_PostIdxImm8s4Operand = 48,
+  ARM_OP_GROUP_AddrMode5Operand_1 = 49,
+  ARM_OP_GROUP_AddrModeImm12Operand_1 = 50,
+  ARM_OP_GROUP_AddrMode3Operand_1 = 51,
+  ARM_OP_GROUP_PostIdxImm8Operand = 52,
+  ARM_OP_GROUP_PostIdxRegOperand = 53,
+  ARM_OP_GROUP_BankedRegOperand = 54,
+  ARM_OP_GROUP_MSRMaskOperand = 55,
+  ARM_OP_GROUP_MveSaturateOp = 56,
+  ARM_OP_GROUP_VMOVModImmOperand = 57,
+  ARM_OP_GROUP_ComplexRotationOp_180_90 = 58,
+  ARM_OP_GROUP_ComplexRotationOp_90_0 = 59,
+  ARM_OP_GROUP_MandatoryRestrictedPredicateOperand = 60,
+  ARM_OP_GROUP_MVEVectorList_2 = 61,
+  ARM_OP_GROUP_MVEVectorList_4 = 62,
+  ARM_OP_GROUP_MveAddrModeRQOperand_0 = 63,
+  ARM_OP_GROUP_MveAddrModeRQOperand_3 = 64,
+  ARM_OP_GROUP_MveAddrModeRQOperand_1 = 65,
+  ARM_OP_GROUP_MveAddrModeRQOperand_2 = 66,
+  ARM_OP_GROUP_VPTMask = 67,
+  ARM_OP_GROUP_PKHLSLShiftImm = 68,
+  ARM_OP_GROUP_PKHASRShiftImm = 69,
+  ARM_OP_GROUP_ImmPlusOneOperand = 70,
+  ARM_OP_GROUP_SetendOperand = 71,
+  ARM_OP_GROUP_ShiftImmOperand = 72,
+  ARM_OP_GROUP_RotImmOperand = 73,
+  ARM_OP_GROUP_TraceSyncBOption = 74,
+  ARM_OP_GROUP_VectorListOneAllLanes = 75,
+  ARM_OP_GROUP_VectorListTwoAllLanes = 76,
+  ARM_OP_GROUP_NoHashImmediate = 77,
+  ARM_OP_GROUP_AddrMode6OffsetOperand = 78,
+  ARM_OP_GROUP_VectorListOne = 79,
+  ARM_OP_GROUP_VectorListTwo = 80,
+  ARM_OP_GROUP_VectorListTwoSpacedAllLanes = 81,
+  ARM_OP_GROUP_VectorListTwoSpaced = 82,
+  ARM_OP_GROUP_AddrMode5FP16Operand_0 = 83,
+  ARM_OP_GROUP_T2AddrModeImm8s4Operand_0 = 84,
+  ARM_OP_GROUP_T2AddrModeImm8s4OffsetOperand = 85,
+  ARM_OP_GROUP_T2AddrModeImm8s4Operand_1 = 86,
+  ARM_OP_GROUP_FBits16 = 87,
+  ARM_OP_GROUP_FBits32 = 88,
+  ARM_OP_GROUP_ThumbSRImm = 89,
+  ARM_OP_GROUP_ThumbLdrLabelOperand = 90,
+  ARM_OP_GROUP_T2AddrModeSoRegOperand = 91,
+  ARM_OP_GROUP_T2AddrModeImm0_1020s4Operand = 92,
+  ARM_OP_GROUP_AddrModeTBB = 93,
+  ARM_OP_GROUP_AddrModeTBH = 94,
+  ARM_OP_GROUP_ThumbS4ImmOperand = 95,
+  ARM_OP_GROUP_AdrLabelOperand_2 = 96,
+  ARM_OP_GROUP_ThumbAddrModeImm5S1Operand = 97,
+  ARM_OP_GROUP_ThumbAddrModeRROperand = 98,
+  ARM_OP_GROUP_ThumbAddrModeImm5S2Operand = 99,
+  ARM_OP_GROUP_ThumbAddrModeImm5S4Operand = 100,
+  ARM_OP_GROUP_ThumbAddrModeSPOperand = 101,

external/capstone/arch/ARM/ARMGenSubtargetInfo.inc

@@ -0,0 +1,248 @@
+/* Capstone Disassembly Engine, https://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2024 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+#ifdef GET_SUBTARGETINFO_ENUM
+#undef GET_SUBTARGETINFO_ENUM
+
+enum {
+  ARM_ARMv4 = 0,
+  ARM_ARMv4t = 1,
+  ARM_ARMv5t = 2,
+  ARM_ARMv5te = 3,
+  ARM_ARMv5tej = 4,
+  ARM_ARMv6 = 5,
+  ARM_ARMv6j = 6,
+  ARM_ARMv6k = 7,
+  ARM_ARMv6kz = 8,
+  ARM_ARMv6m = 9,
+  ARM_ARMv6sm = 10,
+  ARM_ARMv6t2 = 11,
+  ARM_ARMv7a = 12,
+  ARM_ARMv7em = 13,
+  ARM_ARMv7k = 14,
+  ARM_ARMv7m = 15,
+  ARM_ARMv7r = 16,
+  ARM_ARMv7s = 17,
+  ARM_ARMv7ve = 18,
+  ARM_ARMv8a = 19,
+  ARM_ARMv8mBaseline = 20,
+  ARM_ARMv8mMainline = 21,
+  ARM_ARMv8r = 22,
+  ARM_ARMv9a = 23,
+  ARM_ARMv81a = 24,
+  ARM_ARMv81mMainline = 25,
+  ARM_ARMv82a = 26,
+  ARM_ARMv83a = 27,
+  ARM_ARMv84a = 28,
+  ARM_ARMv85a = 29,
+  ARM_ARMv86a = 30,
+  ARM_ARMv87a = 31,
+  ARM_ARMv88a = 32,
+  ARM_ARMv89a = 33,
+  ARM_ARMv91a = 34,
+  ARM_ARMv92a = 35,
+  ARM_ARMv93a = 36,
+  ARM_ARMv94a = 37,
+  ARM_ARMv95a = 38,
+  ARM_Feature8MSecExt = 39,
+  ARM_FeatureAAPCSFrameChain = 40,
+  ARM_FeatureAAPCSFrameChainLeaf = 41,
+  ARM_FeatureAClass = 42,
+  ARM_FeatureAES = 43,
+  ARM_FeatureAcquireRelease = 44,
+  ARM_FeatureAtomics32 = 45,
+  ARM_FeatureAvoidMOVsShOp = 46,
+  ARM_FeatureAvoidPartialCPSR = 47,
+  ARM_FeatureBF16 = 48,
+  ARM_FeatureCLRBHB = 49,
+  ARM_FeatureCRC = 50,
+  ARM_FeatureCheapPredicableCPSR = 51,
+  ARM_FeatureCheckVLDnAlign = 52,
+  ARM_FeatureCoprocCDE0 = 53,
+  ARM_FeatureCoprocCDE1 = 54,
+  ARM_FeatureCoprocCDE2 = 55,
+  ARM_FeatureCoprocCDE3 = 56,
+  ARM_FeatureCoprocCDE4 = 57,
+  ARM_FeatureCoprocCDE5 = 58,
+  ARM_FeatureCoprocCDE6 = 59,
+  ARM_FeatureCoprocCDE7 = 60,
+  ARM_FeatureCrypto = 61,
+  ARM_FeatureD32 = 62,
+  ARM_FeatureDB = 63,
+  ARM_FeatureDFB = 64,
+  ARM_FeatureDSP = 65,
+  ARM_FeatureDontWidenVMOVS = 66,
+  ARM_FeatureDotProd = 67,
+  ARM_FeatureExecuteOnly = 68,
+  ARM_FeatureExpandMLx = 69,
+  ARM_FeatureFP16 = 70,
+  ARM_FeatureFP16FML = 71,
+  ARM_FeatureFP64 = 72,
+  ARM_FeatureFPAO = 73,
+  ARM_FeatureFPARMv8 = 74,
+  ARM_FeatureFPARMv8_D16 = 75,
+  ARM_FeatureFPARMv8_D16_SP = 76,
+  ARM_FeatureFPARMv8_SP = 77,
+  ARM_FeatureFPRegs = 78,
+  ARM_FeatureFPRegs16 = 79,
+  ARM_FeatureFPRegs64 = 80,
+  ARM_FeatureFixCMSE_CVE_2021_35465 = 81,
+  ARM_FeatureFixCortexA57AES1742098 = 82,
+  ARM_FeatureFullFP16 = 83,
+  ARM_FeatureFuseAES = 84,
+  ARM_FeatureFuseLiterals = 85,
+  ARM_FeatureHWDivARM = 86,
+  ARM_FeatureHWDivThumb = 87,
+  ARM_FeatureHardenSlsBlr = 88,
+  ARM_FeatureHardenSlsNoComdat = 89,
+  ARM_FeatureHardenSlsRetBr = 90,
+  ARM_FeatureHasNoBranchPredictor = 91,
+  ARM_FeatureHasRetAddrStack = 92,
+  ARM_FeatureHasSlowFPVFMx = 93,
+  ARM_FeatureHasSlowFPVMLx = 94,
+  ARM_FeatureHasVMLxHazards = 95,
+  ARM_FeatureLOB = 96,
+  ARM_FeatureLongCalls = 97,
+  ARM_FeatureMClass = 98,
+  ARM_FeatureMP = 99,
+  ARM_FeatureMVEVectorCostFactor1 = 100,
+  ARM_FeatureMVEVectorCostFactor2 = 101,
+  ARM_FeatureMVEVectorCostFactor4 = 102,
+  ARM_FeatureMatMulInt8 = 103,
+  ARM_FeatureMuxedUnits = 104,
+  ARM_FeatureNEON = 105,
+  ARM_FeatureNEONForFP = 106,
+  ARM_FeatureNEONForFPMovs = 107,
+  ARM_FeatureNaClTrap = 108,
+  ARM_FeatureNoARM = 109,
+  ARM_FeatureNoBTIAtReturnTwice = 110,
+  ARM_FeatureNoMovt = 111,
+  ARM_FeatureNoNegativeImmediates = 112,
+  ARM_FeatureNoPostRASched = 113,
+  ARM_FeatureNonpipelinedVFP = 114,
+  ARM_FeaturePACBTI = 115,
+  ARM_FeaturePerfMon = 116,
+  ARM_FeaturePref32BitThumb = 117,
+  ARM_FeaturePrefISHSTBarrier = 118,
+  ARM_FeaturePrefLoopAlign32 = 119,
+  ARM_FeaturePreferVMOVSR = 120,
+  ARM_FeatureProfUnpredicate = 121,
+  ARM_FeatureRAS = 122,
+  ARM_FeatureRClass = 123,
+  ARM_FeatureReadTpTPIDRPRW = 124,
+  ARM_FeatureReadTpTPIDRURO = 125,
+  ARM_FeatureReadTpTPIDRURW = 126,
+  ARM_FeatureReserveR9 = 127,
+  ARM_FeatureSB = 128,
+  ARM_FeatureSHA2 = 129,
+  ARM_FeatureSlowFPBrcc = 130,
+  ARM_FeatureSlowLoadDSubreg = 131,
+  ARM_FeatureSlowOddRegister = 132,
+  ARM_FeatureSlowVDUP32 = 133,
+  ARM_FeatureSlowVGETLNi32 = 134,
+  ARM_FeatureSplatVFPToNeon = 135,
+  ARM_FeatureStrictAlign = 136,
+  ARM_FeatureThumb2 = 137,
+  ARM_FeatureTrustZone = 138,
+  ARM_FeatureUseMIPipeliner = 139,
+  ARM_FeatureUseMISched = 140,
+  ARM_FeatureUseWideStrideVFP = 141,
+  ARM_FeatureV7Clrex = 142,
+  ARM_FeatureVFP2 = 143,
+  ARM_FeatureVFP2_SP = 144,
+  ARM_FeatureVFP3 = 145,
+  ARM_FeatureVFP3_D16 = 146,
+  ARM_FeatureVFP3_D16_SP = 147,
+  ARM_FeatureVFP3_SP = 148,
+  ARM_FeatureVFP4 = 149,
+  ARM_FeatureVFP4_D16 = 150,
+  ARM_FeatureVFP4_D16_SP = 151,
+  ARM_FeatureVFP4_SP = 152,
+  ARM_FeatureVMLxForwarding = 153,
+  ARM_FeatureVirtualization = 154,
+  ARM_FeatureZCZeroing = 155,
+  ARM_HasCDEOps = 156,
+  ARM_HasMVEFloatOps = 157,
+  ARM_HasMVEIntegerOps = 158,
+  ARM_HasV4TOps = 159,
+  ARM_HasV5TEOps = 160,
+  ARM_HasV5TOps = 161,
+  ARM_HasV6KOps = 162,
+  ARM_HasV6MOps = 163,
+  ARM_HasV6Ops = 164,
+  ARM_HasV6T2Ops = 165,
+  ARM_HasV7Ops = 166,
+  ARM_HasV8MBaselineOps = 167,
+  ARM_HasV8MMainlineOps = 168,
+  ARM_HasV8Ops = 169,
+  ARM_HasV8_1MMainlineOps = 170,
+  ARM_HasV8_1aOps = 171,
+  ARM_HasV8_2aOps = 172,
+  ARM_HasV8_3aOps = 173,
+  ARM_HasV8_4aOps = 174,
+  ARM_HasV8_5aOps = 175,
+  ARM_HasV8_6aOps = 176,
+  ARM_HasV8_7aOps = 177,
+  ARM_HasV8_8aOps = 178,
+  ARM_HasV8_9aOps = 179,
+  ARM_HasV9_0aOps = 180,
+  ARM_HasV9_1aOps = 181,
+  ARM_HasV9_2aOps = 182,
+  ARM_HasV9_3aOps = 183,
+  ARM_HasV9_4aOps = 184,
+  ARM_HasV9_5aOps = 185,
+  ARM_IWMMXT = 186,
+  ARM_IWMMXT2 = 187,
+  ARM_ModeBigEndianInstructions = 188,
+  ARM_ModeSoftFloat = 189,
+  ARM_ModeThumb = 190,
+  ARM_ProcA5 = 191,
+  ARM_ProcA7 = 192,
+  ARM_ProcA8 = 193,
+  ARM_ProcA9 = 194,
+  ARM_ProcA12 = 195,
+  ARM_ProcA15 = 196,
+  ARM_ProcA17 = 197,
+  ARM_ProcA32 = 198,
+  ARM_ProcA35 = 199,
+  ARM_ProcA53 = 200,
+  ARM_ProcA55 = 201,
+  ARM_ProcA57 = 202,
+  ARM_ProcA72 = 203,
+  ARM_ProcA73 = 204,
+  ARM_ProcA75 = 205,
+  ARM_ProcA76 = 206,
+  ARM_ProcA77 = 207,
+  ARM_ProcA78 = 208,
+  ARM_ProcA78C = 209,
+  ARM_ProcA710 = 210,
+  ARM_ProcExynos = 211,
+  ARM_ProcKrait = 212,
+  ARM_ProcKryo = 213,
+  ARM_ProcM3 = 214,
+  ARM_ProcM7 = 215,
+  ARM_ProcR4 = 216,
+  ARM_ProcR5 = 217,
+  ARM_ProcR7 = 218,
+  ARM_ProcR52 = 219,
+  ARM_ProcSwift = 220,
+  ARM_ProcV1 = 221,
+  ARM_ProcX1 = 222,
+  ARM_ProcX1C = 223,
+  ARM_XScale = 224,
+  ARM_NumSubtargetFeatures = 225
+};
+#endif // GET_SUBTARGETINFO_ENUM
+
+
+

external/capstone/arch/ARM/ARMGenSystemRegister.inc

@@ -0,0 +1,477 @@
+/* Capstone Disassembly Engine, https://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2024 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+#ifdef GET_BANKEDREG_DECL
+#endif
+
+#ifdef GET_MCLASSSYSREG_DECL
+#endif
+
+#ifdef GET_BANKEDREG_DECL
+const ARMBankedReg_BankedReg *ARMBankedReg_lookupBankedRegByName(const char * Name);
+const ARMBankedReg_BankedReg *ARMBankedReg_lookupBankedRegByEncoding(uint8_t Encoding);
+#endif
+
+#ifdef GET_MCLASSSYSREG_DECL
+const ARMSysReg_MClassSysReg *ARMSysReg_lookupMClassSysRegByName(const char * Name);
+const ARMSysReg_MClassSysReg *ARMSysReg_lookupMClassSysRegByM1Encoding12(uint16_t M1Encoding12);
+const ARMSysReg_MClassSysReg *ARMSysReg_lookupMClassSysRegByM2M3Encoding8(uint16_t M2M3Encoding8);
+const ARMSysReg_MClassSysReg *ARMSysReg_lookupMClassSysRegByEncoding(uint16_t Encoding);
+#endif
+
+#ifdef GET_BANKEDREG_IMPL
+static const ARMBankedReg_BankedReg BankedRegsList[] = {
+  { "elr_hyp", { .raw_val = ARM_BANKEDREG_ELR_HYP }, 0x1E }, // 0
+  { "lr_abt", { .raw_val = ARM_BANKEDREG_LR_ABT }, 0x14 }, // 1
+  { "lr_fiq", { .raw_val = ARM_BANKEDREG_LR_FIQ }, 0xE }, // 2
+  { "lr_irq", { .raw_val = ARM_BANKEDREG_LR_IRQ }, 0x10 }, // 3
+  { "lr_mon", { .raw_val = ARM_BANKEDREG_LR_MON }, 0x1C }, // 4
+  { "lr_svc", { .raw_val = ARM_BANKEDREG_LR_SVC }, 0x12 }, // 5
+  { "lr_und", { .raw_val = ARM_BANKEDREG_LR_UND }, 0x16 }, // 6
+  { "lr_usr", { .raw_val = ARM_BANKEDREG_LR_USR }, 0x6 }, // 7
+  { "r10_fiq", { .raw_val = ARM_BANKEDREG_R10_FIQ }, 0xA }, // 8
+  { "r10_usr", { .raw_val = ARM_BANKEDREG_R10_USR }, 0x2 }, // 9
+  { "r11_fiq", { .raw_val = ARM_BANKEDREG_R11_FIQ }, 0xB }, // 10
+  { "r11_usr", { .raw_val = ARM_BANKEDREG_R11_USR }, 0x3 }, // 11
+  { "r12_fiq", { .raw_val = ARM_BANKEDREG_R12_FIQ }, 0xC }, // 12
+  { "r12_usr", { .raw_val = ARM_BANKEDREG_R12_USR }, 0x4 }, // 13
+  { "r8_fiq", { .raw_val = ARM_BANKEDREG_R8_FIQ }, 0x8 }, // 14
+  { "r8_usr", { .raw_val = ARM_BANKEDREG_R8_USR }, 0x0 }, // 15
+  { "r9_fiq", { .raw_val = ARM_BANKEDREG_R9_FIQ }, 0x9 }, // 16
+  { "r9_usr", { .raw_val = ARM_BANKEDREG_R9_USR }, 0x1 }, // 17
+  { "spsr_abt", { .raw_val = ARM_BANKEDREG_SPSR_ABT }, 0x34 }, // 18
+  { "spsr_fiq", { .raw_val = ARM_BANKEDREG_SPSR_FIQ }, 0x2E }, // 19
+  { "spsr_hyp", { .raw_val = ARM_BANKEDREG_SPSR_HYP }, 0x3E }, // 20
+  { "spsr_irq", { .raw_val = ARM_BANKEDREG_SPSR_IRQ }, 0x30 }, // 21
+  { "spsr_mon", { .raw_val = ARM_BANKEDREG_SPSR_MON }, 0x3C }, // 22
+  { "spsr_svc", { .raw_val = ARM_BANKEDREG_SPSR_SVC }, 0x32 }, // 23
+  { "spsr_und", { .raw_val = ARM_BANKEDREG_SPSR_UND }, 0x36 }, // 24
+  { "sp_abt", { .raw_val = ARM_BANKEDREG_SP_ABT }, 0x15 }, // 25
+  { "sp_fiq", { .raw_val = ARM_BANKEDREG_SP_FIQ }, 0xD }, // 26
+  { "sp_hyp", { .raw_val = ARM_BANKEDREG_SP_HYP }, 0x1F }, // 27
+  { "sp_irq", { .raw_val = ARM_BANKEDREG_SP_IRQ }, 0x11 }, // 28
+  { "sp_mon", { .raw_val = ARM_BANKEDREG_SP_MON }, 0x1D }, // 29
+  { "sp_svc", { .raw_val = ARM_BANKEDREG_SP_SVC }, 0x13 }, // 30
+  { "sp_und", { .raw_val = ARM_BANKEDREG_SP_UND }, 0x17 }, // 31
+  { "sp_usr", { .raw_val = ARM_BANKEDREG_SP_USR }, 0x5 }, // 32
+  };
+
+const ARMBankedReg_BankedReg *ARMBankedReg_lookupBankedRegByName(const char * Name) {
+  static const struct IndexTypeStr Index[] = {
+    { "ELR_HYP", 0 },
+    { "LR_ABT", 1 },
+    { "LR_FIQ", 2 },
+    { "LR_IRQ", 3 },
+    { "LR_MON", 4 },
+    { "LR_SVC", 5 },
+    { "LR_UND", 6 },
+    { "LR_USR", 7 },
+    { "R10_FIQ", 8 },
+    { "R10_USR", 9 },
+    { "R11_FIQ", 10 },
+    { "R11_USR", 11 },
+    { "R12_FIQ", 12 },
+    { "R12_USR", 13 },
+    { "R8_FIQ", 14 },
+    { "R8_USR", 15 },
+    { "R9_FIQ", 16 },
+    { "R9_USR", 17 },
+    { "SPSR_ABT", 18 },
+    { "SPSR_FIQ", 19 },
+    { "SPSR_HYP", 20 },
+    { "SPSR_IRQ", 21 },
+    { "SPSR_MON", 22 },
+    { "SPSR_SVC", 23 },
+    { "SPSR_UND", 24 },
+    { "SP_ABT", 25 },
+    { "SP_FIQ", 26 },
+    { "SP_HYP", 27 },
+    { "SP_IRQ", 28 },
+    { "SP_MON", 29 },
+    { "SP_SVC", 30 },
+    { "SP_UND", 31 },
+    { "SP_USR", 32 },
+  };
+
+   unsigned i = binsearch_IndexTypeStrEncoding(Index, ARR_SIZE(Index), Name);
+   if (i == -1)
+      return NULL;
+   else
+      return &BankedRegsList[Index[i].index];
+}
+
+const ARMBankedReg_BankedReg *ARMBankedReg_lookupBankedRegByEncoding(uint8_t Encoding) {
+  static const struct IndexType Index[] = {
+    { 0x0, 15 },
+    { 0x1, 17 },
+    { 0x2, 9 },
+    { 0x3, 11 },
+    { 0x4, 13 },
+    { 0x5, 32 },
+    { 0x6, 7 },
+    { 0x8, 14 },
+    { 0x9, 16 },
+    { 0xA, 8 },
+    { 0xB, 10 },
+    { 0xC, 12 },
+    { 0xD, 26 },
+    { 0xE, 2 },
+    { 0x10, 3 },
+    { 0x11, 28 },
+    { 0x12, 5 },
+    { 0x13, 30 },
+    { 0x14, 1 },
+    { 0x15, 25 },
+    { 0x16, 6 },
+    { 0x17, 31 },
+    { 0x1C, 4 },
+    { 0x1D, 29 },
+    { 0x1E, 0 },
+    { 0x1F, 27 },
+    { 0x2E, 19 },
+    { 0x30, 21 },
+    { 0x32, 23 },
+    { 0x34, 18 },
+    { 0x36, 24 },
+    { 0x3C, 22 },
+    { 0x3E, 20 },
+  };
+
+   unsigned i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Encoding);
+   if (i == -1)
+      return NULL;
+   else
+      return &BankedRegsList[Index[i].index];
+}
+
+#endif
+
+#ifdef GET_MCLASSSYSREG_IMPL
+static const ARMSysReg_MClassSysReg MClassSysRegsList[] = {
+  { "apsr", { .raw_val = ARM_MCLASSSYSREG_APSR }, 0x800, 0x100, 0x800,  {0}  }, // 0
+  { "apsr_g", { .raw_val = ARM_MCLASSSYSREG_APSR_G }, 0x400, 0x0, 0x400,  {ARM_FeatureDSP}  }, // 1
+  { "apsr_nzcvq", { .raw_val = ARM_MCLASSSYSREG_APSR_NZCVQ }, 0x1800, 0x200, 0x800,  {0}  }, // 2
+  { "apsr_nzcvqg", { .raw_val = ARM_MCLASSSYSREG_APSR_NZCVQG }, 0xC00, 0x300, 0xC00,  {ARM_FeatureDSP}  }, // 3
+  { "basepri", { .raw_val = ARM_MCLASSSYSREG_BASEPRI }, 0x811, 0x111, 0x811,  {ARM_HasV7Ops}  }, // 4
+  { "basepri_max", { .raw_val = ARM_MCLASSSYSREG_BASEPRI_MAX }, 0x812, 0x112, 0x812,  {ARM_HasV7Ops}  }, // 5
+  { "basepri_ns", { .raw_val = ARM_MCLASSSYSREG_BASEPRI_NS }, 0x891, 0x191, 0x891,  {ARM_Feature8MSecExt, ARM_HasV7Ops}  }, // 6
+  { "control", { .raw_val = ARM_MCLASSSYSREG_CONTROL }, 0x814, 0x114, 0x814,  {0}  }, // 7
+  { "control_ns", { .raw_val = ARM_MCLASSSYSREG_CONTROL_NS }, 0x894, 0x194, 0x894,  {ARM_Feature8MSecExt}  }, // 8
+  { "eapsr", { .raw_val = ARM_MCLASSSYSREG_EAPSR }, 0x802, 0x102, 0x802,  {0}  }, // 9
+  { "eapsr_g", { .raw_val = ARM_MCLASSSYSREG_EAPSR_G }, 0x402, 0x2, 0x402,  {ARM_FeatureDSP}  }, // 10
+  { "eapsr_nzcvq", { .raw_val = ARM_MCLASSSYSREG_EAPSR_NZCVQ }, 0x1802, 0x202, 0x802,  {0}  }, // 11
+  { "eapsr_nzcvqg", { .raw_val = ARM_MCLASSSYSREG_EAPSR_NZCVQG }, 0xC02, 0x302, 0xC02,  {ARM_FeatureDSP}  }, // 12
+  { "epsr", { .raw_val = ARM_MCLASSSYSREG_EPSR }, 0x806, 0x106, 0x806,  {0}  }, // 13
+  { "faultmask", { .raw_val = ARM_MCLASSSYSREG_FAULTMASK }, 0x813, 0x113, 0x813,  {ARM_HasV7Ops}  }, // 14
+  { "faultmask_ns", { .raw_val = ARM_MCLASSSYSREG_FAULTMASK_NS }, 0x893, 0x193, 0x893,  {ARM_Feature8MSecExt, ARM_HasV7Ops}  }, // 15
+  { "iapsr", { .raw_val = ARM_MCLASSSYSREG_IAPSR }, 0x801, 0x101, 0x801,  {0}  }, // 16
+  { "iapsr_g", { .raw_val = ARM_MCLASSSYSREG_IAPSR_G }, 0x401, 0x1, 0x401,  {ARM_FeatureDSP}  }, // 17
+  { "iapsr_nzcvq", { .raw_val = ARM_MCLASSSYSREG_IAPSR_NZCVQ }, 0x1801, 0x201, 0x801,  {0}  }, // 18
+  { "iapsr_nzcvqg", { .raw_val = ARM_MCLASSSYSREG_IAPSR_NZCVQG }, 0xC01, 0x301, 0xC01,  {ARM_FeatureDSP}  }, // 19
+  { "iepsr", { .raw_val = ARM_MCLASSSYSREG_IEPSR }, 0x807, 0x107, 0x807,  {0}  }, // 20
+  { "ipsr", { .raw_val = ARM_MCLASSSYSREG_IPSR }, 0x805, 0x105, 0x805,  {0}  }, // 21
+  { "msp", { .raw_val = ARM_MCLASSSYSREG_MSP }, 0x808, 0x108, 0x808,  {0}  }, // 22
+  { "msplim", { .raw_val = ARM_MCLASSSYSREG_MSPLIM }, 0x80A, 0x10A, 0x80A,  {ARM_HasV8MBaselineOps}  }, // 23
+  { "msplim_ns", { .raw_val = ARM_MCLASSSYSREG_MSPLIM_NS }, 0x88A, 0x18A, 0x88A,  {ARM_Feature8MSecExt, ARM_HasV8MBaselineOps}  }, // 24
+  { "msp_ns", { .raw_val = ARM_MCLASSSYSREG_MSP_NS }, 0x888, 0x188, 0x888,  {ARM_Feature8MSecExt}  }, // 25
+  { "pac_key_p_0", { .raw_val = ARM_MCLASSSYSREG_PAC_KEY_P_0 }, 0x820, 0x120, 0x820,  {ARM_FeaturePACBTI}  }, // 26
+  { "pac_key_p_0_ns", { .raw_val = ARM_MCLASSSYSREG_PAC_KEY_P_0_NS }, 0x8A0, 0x1A0, 0x8A0,  {ARM_FeaturePACBTI}  }, // 27
+  { "pac_key_p_1", { .raw_val = ARM_MCLASSSYSREG_PAC_KEY_P_1 }, 0x821, 0x121, 0x821,  {ARM_FeaturePACBTI}  }, // 28
+  { "pac_key_p_1_ns", { .raw_val = ARM_MCLASSSYSREG_PAC_KEY_P_1_NS }, 0x8A1, 0x1A1, 0x8A1,  {ARM_FeaturePACBTI}  }, // 29
+  { "pac_key_p_2", { .raw_val = ARM_MCLASSSYSREG_PAC_KEY_P_2 }, 0x822, 0x122, 0x822,  {ARM_FeaturePACBTI}  }, // 30
+  { "pac_key_p_2_ns", { .raw_val = ARM_MCLASSSYSREG_PAC_KEY_P_2_NS }, 0x8A2, 0x1A2, 0x8A2,  {ARM_FeaturePACBTI}  }, // 31
+  { "pac_key_p_3", { .raw_val = ARM_MCLASSSYSREG_PAC_KEY_P_3 }, 0x823, 0x123, 0x823,  {ARM_FeaturePACBTI}  }, // 32
+  { "pac_key_p_3_ns", { .raw_val = ARM_MCLASSSYSREG_PAC_KEY_P_3_NS }, 0x8A3, 0x1A3, 0x8A3,  {ARM_FeaturePACBTI}  }, // 33
+  { "pac_key_u_0", { .raw_val = ARM_MCLASSSYSREG_PAC_KEY_U_0 }, 0x824, 0x124, 0x824,  {ARM_FeaturePACBTI}  }, // 34
+  { "pac_key_u_0_ns", { .raw_val = ARM_MCLASSSYSREG_PAC_KEY_U_0_NS }, 0x8A4, 0x1A4, 0x8A4,  {ARM_FeaturePACBTI}  }, // 35
+  { "pac_key_u_1", { .raw_val = ARM_MCLASSSYSREG_PAC_KEY_U_1 }, 0x825, 0x125, 0x825,  {ARM_FeaturePACBTI}  }, // 36
+  { "pac_key_u_1_ns", { .raw_val = ARM_MCLASSSYSREG_PAC_KEY_U_1_NS }, 0x8A5, 0x1A5, 0x8A5,  {ARM_FeaturePACBTI}  }, // 37
+  { "pac_key_u_2", { .raw_val = ARM_MCLASSSYSREG_PAC_KEY_U_2 }, 0x826, 0x126, 0x826,  {ARM_FeaturePACBTI}  }, // 38
+  { "pac_key_u_2_ns", { .raw_val = ARM_MCLASSSYSREG_PAC_KEY_U_2_NS }, 0x8A6, 0x1A6, 0x8A6,  {ARM_FeaturePACBTI}  }, // 39
+  { "pac_key_u_3", { .raw_val = ARM_MCLASSSYSREG_PAC_KEY_U_3 }, 0x827, 0x127, 0x827,  {ARM_FeaturePACBTI}  }, // 40
+  { "pac_key_u_3_ns", { .raw_val = ARM_MCLASSSYSREG_PAC_KEY_U_3_NS }, 0x8A7, 0x1A7, 0x8A7,  {ARM_FeaturePACBTI}  }, // 41
+  { "primask", { .raw_val = ARM_MCLASSSYSREG_PRIMASK }, 0x810, 0x110, 0x810,  {0}  }, // 42
+  { "primask_ns", { .raw_val = ARM_MCLASSSYSREG_PRIMASK_NS }, 0x890, 0x190, 0x890,  {0}  }, // 43
+  { "psp", { .raw_val = ARM_MCLASSSYSREG_PSP }, 0x809, 0x109, 0x809,  {0}  }, // 44
+  { "psplim", { .raw_val = ARM_MCLASSSYSREG_PSPLIM }, 0x80B, 0x10B, 0x80B,  {ARM_HasV8MBaselineOps}  }, // 45
+  { "psplim_ns", { .raw_val = ARM_MCLASSSYSREG_PSPLIM_NS }, 0x88B, 0x18B, 0x88B,  {ARM_Feature8MSecExt, ARM_HasV8MBaselineOps}  }, // 46
+  { "psp_ns", { .raw_val = ARM_MCLASSSYSREG_PSP_NS }, 0x889, 0x189, 0x889,  {ARM_Feature8MSecExt}  }, // 47
+  { "sp_ns", { .raw_val = ARM_MCLASSSYSREG_SP_NS }, 0x898, 0x198, 0x898,  {ARM_Feature8MSecExt}  }, // 48
+  { "xpsr", { .raw_val = ARM_MCLASSSYSREG_XPSR }, 0x803, 0x103, 0x803,  {0}  }, // 49
+  { "xpsr_g", { .raw_val = ARM_MCLASSSYSREG_XPSR_G }, 0x403, 0x3, 0x403,  {ARM_FeatureDSP}  }, // 50
+  { "xpsr_nzcvq", { .raw_val = ARM_MCLASSSYSREG_XPSR_NZCVQ }, 0x1803, 0x203, 0x803,  {0}  }, // 51
+  { "xpsr_nzcvqg", { .raw_val = ARM_MCLASSSYSREG_XPSR_NZCVQG }, 0xC03, 0x303, 0xC03,  {ARM_FeatureDSP}  }, // 52
+  };
+
+const ARMSysReg_MClassSysReg *ARMSysReg_lookupMClassSysRegByName(const char * Name) {
+  static const struct IndexTypeStr Index[] = {
+    { "APSR", 0 },
+    { "APSR_G", 1 },
+    { "APSR_NZCVQ", 2 },
+    { "APSR_NZCVQG", 3 },
+    { "BASEPRI", 4 },
+    { "BASEPRI_MAX", 5 },
+    { "BASEPRI_NS", 6 },
+    { "CONTROL", 7 },
+    { "CONTROL_NS", 8 },
+    { "EAPSR", 9 },
+    { "EAPSR_G", 10 },
+    { "EAPSR_NZCVQ", 11 },
+    { "EAPSR_NZCVQG", 12 },
+    { "EPSR", 13 },
+    { "FAULTMASK", 14 },
+    { "FAULTMASK_NS", 15 },
+    { "IAPSR", 16 },
+    { "IAPSR_G", 17 },
+    { "IAPSR_NZCVQ", 18 },
+    { "IAPSR_NZCVQG", 19 },
+    { "IEPSR", 20 },
+    { "IPSR", 21 },
+    { "MSP", 22 },
+    { "MSPLIM", 23 },
+    { "MSPLIM_NS", 24 },
+    { "MSP_NS", 25 },
+    { "PAC_KEY_P_0", 26 },
+    { "PAC_KEY_P_0_NS", 27 },
+    { "PAC_KEY_P_1", 28 },
+    { "PAC_KEY_P_1_NS", 29 },
+    { "PAC_KEY_P_2", 30 },
+    { "PAC_KEY_P_2_NS", 31 },
+    { "PAC_KEY_P_3", 32 },
+    { "PAC_KEY_P_3_NS", 33 },
+    { "PAC_KEY_U_0", 34 },
+    { "PAC_KEY_U_0_NS", 35 },
+    { "PAC_KEY_U_1", 36 },
+    { "PAC_KEY_U_1_NS", 37 },
+    { "PAC_KEY_U_2", 38 },
+    { "PAC_KEY_U_2_NS", 39 },
+    { "PAC_KEY_U_3", 40 },
+    { "PAC_KEY_U_3_NS", 41 },
+    { "PRIMASK", 42 },
+    { "PRIMASK_NS", 43 },
+    { "PSP", 44 },
+    { "PSPLIM", 45 },
+    { "PSPLIM_NS", 46 },
+    { "PSP_NS", 47 },
+    { "SP_NS", 48 },
+    { "XPSR", 49 },
+    { "XPSR_G", 50 },
+    { "XPSR_NZCVQ", 51 },
+    { "XPSR_NZCVQG", 52 },
+  };
+
+   unsigned i = binsearch_IndexTypeStrEncoding(Index, ARR_SIZE(Index), Name);
+   if (i == -1)
+      return NULL;
+   else
+      return &MClassSysRegsList[Index[i].index];
+}
+
+const ARMSysReg_MClassSysReg *ARMSysReg_lookupMClassSysRegByM1Encoding12(uint16_t M1Encoding12) {
+  static const struct IndexType Index[] = {
+    { 0x400, 1 },
+    { 0x401, 17 },
+    { 0x402, 10 },
+    { 0x403, 50 },
+    { 0x800, 0 },
+    { 0x801, 16 },
+    { 0x802, 9 },
+    { 0x803, 49 },
+    { 0x805, 21 },
+    { 0x806, 13 },
+    { 0x807, 20 },
+    { 0x808, 22 },
+    { 0x809, 44 },
+    { 0x80A, 23 },
+    { 0x80B, 45 },
+    { 0x810, 42 },
+    { 0x811, 4 },
+    { 0x812, 5 },
+    { 0x813, 14 },
+    { 0x814, 7 },
+    { 0x820, 26 },
+    { 0x821, 28 },
+    { 0x822, 30 },
+    { 0x823, 32 },
+    { 0x824, 34 },
+    { 0x825, 36 },
+    { 0x826, 38 },
+    { 0x827, 40 },
+    { 0x888, 25 },
+    { 0x889, 47 },
+    { 0x88A, 24 },
+    { 0x88B, 46 },
+    { 0x890, 43 },
+    { 0x891, 6 },
+    { 0x893, 15 },
+    { 0x894, 8 },
+    { 0x898, 48 },
+    { 0x8A0, 27 },
+    { 0x8A1, 29 },
+    { 0x8A2, 31 },
+    { 0x8A3, 33 },
+    { 0x8A4, 35 },
+    { 0x8A5, 37 },
+    { 0x8A6, 39 },
+    { 0x8A7, 41 },
+    { 0xC00, 3 },
+    { 0xC01, 19 },
+    { 0xC02, 12 },
+    { 0xC03, 52 },
+    { 0x1800, 2 },
+    { 0x1801, 18 },
+    { 0x1802, 11 },
+    { 0x1803, 51 },
+  };
+
+   unsigned i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), M1Encoding12);
+   if (i == -1)
+      return NULL;
+   else
+      return &MClassSysRegsList[Index[i].index];
+}
+
+const ARMSysReg_MClassSysReg *ARMSysReg_lookupMClassSysRegByM2M3Encoding8(uint16_t M2M3Encoding8) {
+  static const struct IndexType Index[] = {
+    { 0x0, 1 },
+    { 0x1, 17 },
+    { 0x2, 10 },
+    { 0x3, 50 },
+    { 0x100, 0 },
+    { 0x101, 16 },
+    { 0x102, 9 },
+    { 0x103, 49 },
+    { 0x105, 21 },
+    { 0x106, 13 },
+    { 0x107, 20 },
+    { 0x108, 22 },
+    { 0x109, 44 },
+    { 0x10A, 23 },
+    { 0x10B, 45 },
+    { 0x110, 42 },
+    { 0x111, 4 },
+    { 0x112, 5 },
+    { 0x113, 14 },
+    { 0x114, 7 },
+    { 0x120, 26 },
+    { 0x121, 28 },
+    { 0x122, 30 },
+    { 0x123, 32 },
+    { 0x124, 34 },
+    { 0x125, 36 },
+    { 0x126, 38 },
+    { 0x127, 40 },
+    { 0x188, 25 },
+    { 0x189, 47 },
+    { 0x18A, 24 },
+    { 0x18B, 46 },
+    { 0x190, 43 },
+    { 0x191, 6 },
+    { 0x193, 15 },
+    { 0x194, 8 },
+    { 0x198, 48 },
+    { 0x1A0, 27 },
+    { 0x1A1, 29 },
+    { 0x1A2, 31 },
+    { 0x1A3, 33 },
+    { 0x1A4, 35 },
+    { 0x1A5, 37 },
+    { 0x1A6, 39 },
+    { 0x1A7, 41 },
+    { 0x200, 2 },
+    { 0x201, 18 },
+    { 0x202, 11 },
+    { 0x203, 51 },
+    { 0x300, 3 },
+    { 0x301, 19 },
+    { 0x302, 12 },
+    { 0x303, 52 },
+  };
+
+   unsigned i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), M2M3Encoding8);
+   if (i == -1)
+      return NULL;
+   else
+      return &MClassSysRegsList[Index[i].index];
+}
+
+const ARMSysReg_MClassSysReg *ARMSysReg_lookupMClassSysRegByEncoding(uint16_t Encoding) {
+  static const struct IndexType Index[] = {
+    { 0x400, 1 },
+    { 0x401, 17 },
+    { 0x402, 10 },
+    { 0x403, 50 },
+    { 0x800, 0 },
+    { 0x800, 2 },
+    { 0x801, 16 },
+    { 0x801, 18 },
+    { 0x802, 9 },
+    { 0x802, 11 },
+    { 0x803, 49 },
+    { 0x803, 51 },
+    { 0x805, 21 },
+    { 0x806, 13 },
+    { 0x807, 20 },
+    { 0x808, 22 },
+    { 0x809, 44 },
+    { 0x80A, 23 },
+    { 0x80B, 45 },
+    { 0x810, 42 },
+    { 0x811, 4 },
+    { 0x812, 5 },
+    { 0x813, 14 },
+    { 0x814, 7 },
+    { 0x820, 26 },
+    { 0x821, 28 },
+    { 0x822, 30 },
+    { 0x823, 32 },
+    { 0x824, 34 },
+    { 0x825, 36 },
+    { 0x826, 38 },
+    { 0x827, 40 },
+    { 0x888, 25 },
+    { 0x889, 47 },
+    { 0x88A, 24 },
+    { 0x88B, 46 },
+    { 0x890, 43 },
+    { 0x891, 6 },
+    { 0x893, 15 },
+    { 0x894, 8 },
+    { 0x898, 48 },
+    { 0x8A0, 27 },
+    { 0x8A1, 29 },
+    { 0x8A2, 31 },
+    { 0x8A3, 33 },
+    { 0x8A4, 35 },
+    { 0x8A5, 37 },
+    { 0x8A6, 39 },
+    { 0x8A7, 41 },
+    { 0xC00, 3 },
+    { 0xC01, 19 },
+    { 0xC02, 12 },
+    { 0xC03, 52 },
+  };
+
+   unsigned i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Encoding);
+   if (i == -1)
+      return NULL;
+   else
+      return &MClassSysRegsList[Index[i].index];
+}
+
+#endif
+
+#undef GET_BANKEDREG_DECL
+#undef GET_BANKEDREG_IMPL
+#undef GET_MCLASSSYSREG_DECL
+#undef GET_MCLASSSYSREG_IMPL

external/capstone/arch/ARM/ARMInsnEnum.inc

@@ -0,0 +1,162 @@
+/* Capstone Disassembly Engine, https://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
+/* By Rot127 <unisono@quyllur.org>, 2023 */
+
+/* Auto generated file. Do not edit. */
+/* Code generator: https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
+
+ARM_INS___BRKDIV0, ARM_INS_ADC, ARM_INS_ADD, ARM_INS_ADDW, ARM_INS_ADR,
+	ARM_INS_AESD, ARM_INS_AESE, ARM_INS_AESIMC, ARM_INS_AESMC, ARM_INS_AND,
+	ARM_INS_ASR, ARM_INS_ASRL, ARM_INS_AUT, ARM_INS_AUTG, ARM_INS_B,
+	ARM_INS_BF, ARM_INS_BFC, ARM_INS_BFCSEL, ARM_INS_BFI, ARM_INS_BFL,
+	ARM_INS_BFLX, ARM_INS_BFX, ARM_INS_BIC, ARM_INS_BKPT, ARM_INS_BL,
+	ARM_INS_BLX, ARM_INS_BLXNS, ARM_INS_BTI, ARM_INS_BX, ARM_INS_BXAUT,
+	ARM_INS_BXJ, ARM_INS_BXNS, ARM_INS_CBNZ, ARM_INS_CBZ, ARM_INS_CDP,
+	ARM_INS_CDP2, ARM_INS_CINC, ARM_INS_CINV, ARM_INS_CLRBHB, ARM_INS_CLREX,
+	ARM_INS_CLRM, ARM_INS_CLZ, ARM_INS_CMN, ARM_INS_CMP, ARM_INS_CNEG,
+	ARM_INS_CPS, ARM_INS_CRC32B, ARM_INS_CRC32CB, ARM_INS_CRC32CH,
+	ARM_INS_CRC32CW, ARM_INS_CRC32H, ARM_INS_CRC32W, ARM_INS_CSDB,
+	ARM_INS_CSEL, ARM_INS_CSET, ARM_INS_CSETM, ARM_INS_CSINC, ARM_INS_CSINV,
+	ARM_INS_CSNEG, ARM_INS_CX1, ARM_INS_CX1A, ARM_INS_CX1D, ARM_INS_CX1DA,
+	ARM_INS_CX2, ARM_INS_CX2A, ARM_INS_CX2D, ARM_INS_CX2DA, ARM_INS_CX3,
+	ARM_INS_CX3A, ARM_INS_CX3D, ARM_INS_CX3DA, ARM_INS_DBG, ARM_INS_DCPS1,
+	ARM_INS_DCPS2, ARM_INS_DCPS3, ARM_INS_DFB, ARM_INS_DLS, ARM_INS_DLSTP,
+	ARM_INS_DMB, ARM_INS_DSB, ARM_INS_EOR, ARM_INS_ERET, ARM_INS_ESB,
+	ARM_INS_FADDD, ARM_INS_FADDS, ARM_INS_FCMPZD, ARM_INS_FCMPZS,
+	ARM_INS_FCONSTD, ARM_INS_FCONSTS, ARM_INS_FLDMDBX, ARM_INS_FLDMIAX,
+	ARM_INS_FMDHR, ARM_INS_FMDLR, ARM_INS_FMSTAT, ARM_INS_FSTMDBX,
+	ARM_INS_FSTMIAX, ARM_INS_FSUBD, ARM_INS_FSUBS, ARM_INS_HINT,
+	ARM_INS_HLT, ARM_INS_HVC, ARM_INS_ISB, ARM_INS_IT, ARM_INS_LCTP,
+	ARM_INS_LDA, ARM_INS_LDAB, ARM_INS_LDAEX, ARM_INS_LDAEXB,
+	ARM_INS_LDAEXD, ARM_INS_LDAEXH, ARM_INS_LDAH, ARM_INS_LDC, ARM_INS_LDC2,
+	ARM_INS_LDC2L, ARM_INS_LDCL, ARM_INS_LDM, ARM_INS_LDMDA, ARM_INS_LDMDB,
+	ARM_INS_LDMIB, ARM_INS_LDR, ARM_INS_LDRB, ARM_INS_LDRBT, ARM_INS_LDRD,
+	ARM_INS_LDREX, ARM_INS_LDREXB, ARM_INS_LDREXD, ARM_INS_LDREXH,
+	ARM_INS_LDRH, ARM_INS_LDRHT, ARM_INS_LDRSB, ARM_INS_LDRSBT,
+	ARM_INS_LDRSH, ARM_INS_LDRSHT, ARM_INS_LDRT, ARM_INS_LE, ARM_INS_LETP,
+	ARM_INS_LSL, ARM_INS_LSLL, ARM_INS_LSR, ARM_INS_LSRL, ARM_INS_MCR,
+	ARM_INS_MCR2, ARM_INS_MCRR, ARM_INS_MCRR2, ARM_INS_MLA, ARM_INS_MLS,
+	ARM_INS_MOV, ARM_INS_MOVS, ARM_INS_MOVT, ARM_INS_MOVW, ARM_INS_MRC,
+	ARM_INS_MRC2, ARM_INS_MRRC, ARM_INS_MRRC2, ARM_INS_MRS, ARM_INS_MSR,
+	ARM_INS_MUL, ARM_INS_MVN, ARM_INS_NEG, ARM_INS_NOP, ARM_INS_ORN,
+	ARM_INS_ORR, ARM_INS_PAC, ARM_INS_PACBTI, ARM_INS_PACG, ARM_INS_PKHBT,
+	ARM_INS_PKHTB, ARM_INS_PLD, ARM_INS_PLDW, ARM_INS_PLI, ARM_INS_POP,
+	ARM_INS_PSSBB, ARM_INS_PUSH, ARM_INS_QADD, ARM_INS_QADD16,
+	ARM_INS_QADD8, ARM_INS_QASX, ARM_INS_QDADD, ARM_INS_QDSUB, ARM_INS_QSAX,
+	ARM_INS_QSUB, ARM_INS_QSUB16, ARM_INS_QSUB8, ARM_INS_RBIT, ARM_INS_REV,
+	ARM_INS_REV16, ARM_INS_REVSH, ARM_INS_RFEDA, ARM_INS_RFEDB,
+	ARM_INS_RFEIA, ARM_INS_RFEIB, ARM_INS_ROR, ARM_INS_RRX, ARM_INS_RSB,
+	ARM_INS_RSC, ARM_INS_SADD16, ARM_INS_SADD8, ARM_INS_SASX, ARM_INS_SB,
+	ARM_INS_SBC, ARM_INS_SBFX, ARM_INS_SDIV, ARM_INS_SEL, ARM_INS_SETEND,
+	ARM_INS_SETPAN, ARM_INS_SEV, ARM_INS_SEVL, ARM_INS_SG, ARM_INS_SHA1C,
+	ARM_INS_SHA1H, ARM_INS_SHA1M, ARM_INS_SHA1P, ARM_INS_SHA1SU0,
+	ARM_INS_SHA1SU1, ARM_INS_SHA256H, ARM_INS_SHA256H2, ARM_INS_SHA256SU0,
+	ARM_INS_SHA256SU1, ARM_INS_SHADD16, ARM_INS_SHADD8, ARM_INS_SHASX,
+	ARM_INS_SHSAX, ARM_INS_SHSUB16, ARM_INS_SHSUB8, ARM_INS_SMC,
+	ARM_INS_SMLABB, ARM_INS_SMLABT, ARM_INS_SMLAD, ARM_INS_SMLADX,
+	ARM_INS_SMLAL, ARM_INS_SMLALBB, ARM_INS_SMLALBT, ARM_INS_SMLALD,
+	ARM_INS_SMLALDX, ARM_INS_SMLALTB, ARM_INS_SMLALTT, ARM_INS_SMLATB,
+	ARM_INS_SMLATT, ARM_INS_SMLAWB, ARM_INS_SMLAWT, ARM_INS_SMLSD,
+	ARM_INS_SMLSDX, ARM_INS_SMLSLD, ARM_INS_SMLSLDX, ARM_INS_SMMLA,
+	ARM_INS_SMMLAR, ARM_INS_SMMLS, ARM_INS_SMMLSR, ARM_INS_SMMUL,
+	ARM_INS_SMMULR, ARM_INS_SMUAD, ARM_INS_SMUADX, ARM_INS_SMULBB,
+	ARM_INS_SMULBT, ARM_INS_SMULL, ARM_INS_SMULTB, ARM_INS_SMULTT,
+	ARM_INS_SMULWB, ARM_INS_SMULWT, ARM_INS_SMUSD, ARM_INS_SMUSDX,
+	ARM_INS_SQRSHR, ARM_INS_SQRSHRL, ARM_INS_SQSHL, ARM_INS_SQSHLL,
+	ARM_INS_SRSDA, ARM_INS_SRSDB, ARM_INS_SRSHR, ARM_INS_SRSHRL,
+	ARM_INS_SRSIA, ARM_INS_SRSIB, ARM_INS_SSAT, ARM_INS_SSAT16,
+	ARM_INS_SSAX, ARM_INS_SSBB, ARM_INS_SSUB16, ARM_INS_SSUB8, ARM_INS_STC,
+	ARM_INS_STC2, ARM_INS_STC2L, ARM_INS_STCL, ARM_INS_STL, ARM_INS_STLB,
+	ARM_INS_STLEX, ARM_INS_STLEXB, ARM_INS_STLEXD, ARM_INS_STLEXH,
+	ARM_INS_STLH, ARM_INS_STM, ARM_INS_STMDA, ARM_INS_STMDB, ARM_INS_STMIB,
+	ARM_INS_STR, ARM_INS_STRB, ARM_INS_STRBT, ARM_INS_STRD, ARM_INS_STREX,
+	ARM_INS_STREXB, ARM_INS_STREXD, ARM_INS_STREXH, ARM_INS_STRH,
+	ARM_INS_STRHT, ARM_INS_STRT, ARM_INS_SUB, ARM_INS_SUBS, ARM_INS_SUBW,
+	ARM_INS_SVC, ARM_INS_SWP, ARM_INS_SWPB, ARM_INS_SXTAB, ARM_INS_SXTAB16,
+	ARM_INS_SXTAH, ARM_INS_SXTB, ARM_INS_SXTB16, ARM_INS_SXTH, ARM_INS_TBB,
+	ARM_INS_TBH, ARM_INS_TEQ, ARM_INS_TRAP, ARM_INS_TSB, ARM_INS_TST,
+	ARM_INS_TT, ARM_INS_TTA, ARM_INS_TTAT, ARM_INS_TTT, ARM_INS_UADD16,
+	ARM_INS_UADD8, ARM_INS_UASX, ARM_INS_UBFX, ARM_INS_UDF, ARM_INS_UDIV,
+	ARM_INS_UHADD16, ARM_INS_UHADD8, ARM_INS_UHASX, ARM_INS_UHSAX,
+	ARM_INS_UHSUB16, ARM_INS_UHSUB8, ARM_INS_UMAAL, ARM_INS_UMLAL,
+	ARM_INS_UMULL, ARM_INS_UQADD16, ARM_INS_UQADD8, ARM_INS_UQASX,
+	ARM_INS_UQRSHL, ARM_INS_UQRSHLL, ARM_INS_UQSAX, ARM_INS_UQSHL,
+	ARM_INS_UQSHLL, ARM_INS_UQSUB16, ARM_INS_UQSUB8, ARM_INS_URSHR,
+	ARM_INS_URSHRL, ARM_INS_USAD8, ARM_INS_USADA8, ARM_INS_USAT,
+	ARM_INS_USAT16, ARM_INS_USAX, ARM_INS_USUB16, ARM_INS_USUB8,
+	ARM_INS_UXTAB, ARM_INS_UXTAB16, ARM_INS_UXTAH, ARM_INS_UXTB,
+	ARM_INS_UXTB16, ARM_INS_UXTH, ARM_INS_VABA, ARM_INS_VABAL,
+	ARM_INS_VABAV, ARM_INS_VABD, ARM_INS_VABDL, ARM_INS_VABS, ARM_INS_VACGE,
+	ARM_INS_VACGT, ARM_INS_VACLE, ARM_INS_VACLT, ARM_INS_VADC,
+	ARM_INS_VADCI, ARM_INS_VADD, ARM_INS_VADDHN, ARM_INS_VADDL,
+	ARM_INS_VADDLV, ARM_INS_VADDLVA, ARM_INS_VADDV, ARM_INS_VADDVA,
+	ARM_INS_VADDW, ARM_INS_VAND, ARM_INS_VBIC, ARM_INS_VBIF, ARM_INS_VBIT,
+	ARM_INS_VBRSR, ARM_INS_VBSL, ARM_INS_VCADD, ARM_INS_VCEQ, ARM_INS_VCGE,
+	ARM_INS_VCGT, ARM_INS_VCLE, ARM_INS_VCLS, ARM_INS_VCLT, ARM_INS_VCLZ,
+	ARM_INS_VCMLA, ARM_INS_VCMP, ARM_INS_VCMPE, ARM_INS_VCMUL, ARM_INS_VCNT,
+	ARM_INS_VCTP, ARM_INS_VCVT, ARM_INS_VCVTA, ARM_INS_VCVTB, ARM_INS_VCVTM,
+	ARM_INS_VCVTN, ARM_INS_VCVTP, ARM_INS_VCVTR, ARM_INS_VCVTT,
+	ARM_INS_VCX1, ARM_INS_VCX1A, ARM_INS_VCX2, ARM_INS_VCX2A, ARM_INS_VCX3,
+	ARM_INS_VCX3A, ARM_INS_VDDUP, ARM_INS_VDIV, ARM_INS_VDOT, ARM_INS_VDUP,
+	ARM_INS_VDWDUP, ARM_INS_VEOR, ARM_INS_VEXT, ARM_INS_VFMA, ARM_INS_VFMAB,
+	ARM_INS_VFMAL, ARM_INS_VFMAS, ARM_INS_VFMAT, ARM_INS_VFMS,
+	ARM_INS_VFMSL, ARM_INS_VFNMA, ARM_INS_VFNMS, ARM_INS_VHADD,
+	ARM_INS_VHCADD, ARM_INS_VHSUB, ARM_INS_VIDUP, ARM_INS_VINS,
+	ARM_INS_VIWDUP, ARM_INS_VJCVT, ARM_INS_VLD1, ARM_INS_VLD2,
+	ARM_INS_VLD20, ARM_INS_VLD21, ARM_INS_VLD3, ARM_INS_VLD4, ARM_INS_VLD40,
+	ARM_INS_VLD41, ARM_INS_VLD42, ARM_INS_VLD43, ARM_INS_VLDMDB,
+	ARM_INS_VLDMIA, ARM_INS_VLDR, ARM_INS_VLDRB, ARM_INS_VLDRD,
+	ARM_INS_VLDRH, ARM_INS_VLDRW, ARM_INS_VLLDM, ARM_INS_VLSTM,
+	ARM_INS_VMAX, ARM_INS_VMAXA, ARM_INS_VMAXAV, ARM_INS_VMAXNM,
+	ARM_INS_VMAXNMA, ARM_INS_VMAXNMAV, ARM_INS_VMAXNMV, ARM_INS_VMAXV,
+	ARM_INS_VMIN, ARM_INS_VMINA, ARM_INS_VMINAV, ARM_INS_VMINNM,
+	ARM_INS_VMINNMA, ARM_INS_VMINNMAV, ARM_INS_VMINNMV, ARM_INS_VMINV,
+	ARM_INS_VMLA, ARM_INS_VMLADAV, ARM_INS_VMLADAVA, ARM_INS_VMLADAVAX,
+	ARM_INS_VMLADAVX, ARM_INS_VMLAL, ARM_INS_VMLALDAV, ARM_INS_VMLALDAVA,
+	ARM_INS_VMLALDAVAX, ARM_INS_VMLALDAVX, ARM_INS_VMLALV, ARM_INS_VMLALVA,
+	ARM_INS_VMLAS, ARM_INS_VMLAV, ARM_INS_VMLAVA, ARM_INS_VMLS,
+	ARM_INS_VMLSDAV, ARM_INS_VMLSDAVA, ARM_INS_VMLSDAVAX, ARM_INS_VMLSDAVX,
+	ARM_INS_VMLSL, ARM_INS_VMLSLDAV, ARM_INS_VMLSLDAVA, ARM_INS_VMLSLDAVAX,
+	ARM_INS_VMLSLDAVX, ARM_INS_VMMLA, ARM_INS_VMOV, ARM_INS_VMOVL,
+	ARM_INS_VMOVLB, ARM_INS_VMOVLT, ARM_INS_VMOVN, ARM_INS_VMOVNB,
+	ARM_INS_VMOVNT, ARM_INS_VMOVX, ARM_INS_VMRS, ARM_INS_VMSR, ARM_INS_VMUL,
+	ARM_INS_VMULH, ARM_INS_VMULL, ARM_INS_VMULLB, ARM_INS_VMULLT,
+	ARM_INS_VMVN, ARM_INS_VNEG, ARM_INS_VNMLA, ARM_INS_VNMLS, ARM_INS_VNMUL,
+	ARM_INS_VORN, ARM_INS_VORR, ARM_INS_VPADAL, ARM_INS_VPADD,
+	ARM_INS_VPADDL, ARM_INS_VPMAX, ARM_INS_VPMIN, ARM_INS_VPNOT,
+	ARM_INS_VPOP, ARM_INS_VPSEL, ARM_INS_VPST, ARM_INS_VPT, ARM_INS_VPUSH,
+	ARM_INS_VQABS, ARM_INS_VQADD, ARM_INS_VQDMLADH, ARM_INS_VQDMLADHX,
+	ARM_INS_VQDMLAH, ARM_INS_VQDMLAL, ARM_INS_VQDMLASH, ARM_INS_VQDMLSDH,
+	ARM_INS_VQDMLSDHX, ARM_INS_VQDMLSL, ARM_INS_VQDMULH, ARM_INS_VQDMULL,
+	ARM_INS_VQDMULLB, ARM_INS_VQDMULLT, ARM_INS_VQMOVN, ARM_INS_VQMOVNB,
+	ARM_INS_VQMOVNT, ARM_INS_VQMOVUN, ARM_INS_VQMOVUNB, ARM_INS_VQMOVUNT,
+	ARM_INS_VQNEG, ARM_INS_VQRDMLADH, ARM_INS_VQRDMLADHX, ARM_INS_VQRDMLAH,
+	ARM_INS_VQRDMLASH, ARM_INS_VQRDMLSDH, ARM_INS_VQRDMLSDHX,
+	ARM_INS_VQRDMLSH, ARM_INS_VQRDMULH, ARM_INS_VQRSHL, ARM_INS_VQRSHRN,
+	ARM_INS_VQRSHRNB, ARM_INS_VQRSHRNT, ARM_INS_VQRSHRUN, ARM_INS_VQRSHRUNB,
+	ARM_INS_VQRSHRUNT, ARM_INS_VQSHL, ARM_INS_VQSHLU, ARM_INS_VQSHRN,
+	ARM_INS_VQSHRNB, ARM_INS_VQSHRNT, ARM_INS_VQSHRUN, ARM_INS_VQSHRUNB,
+	ARM_INS_VQSHRUNT, ARM_INS_VQSUB, ARM_INS_VRADDHN, ARM_INS_VRECPE,
+	ARM_INS_VRECPS, ARM_INS_VREV16, ARM_INS_VREV32, ARM_INS_VREV64,
+	ARM_INS_VRHADD, ARM_INS_VRINTA, ARM_INS_VRINTM, ARM_INS_VRINTN,
+	ARM_INS_VRINTP, ARM_INS_VRINTR, ARM_INS_VRINTX, ARM_INS_VRINTZ,
+	ARM_INS_VRMLALDAVH, ARM_INS_VRMLALDAVHA, ARM_INS_VRMLALDAVHAX,
+	ARM_INS_VRMLALDAVHX, ARM_INS_VRMLALVH, ARM_INS_VRMLALVHA,
+	ARM_INS_VRMLSLDAVH, ARM_INS_VRMLSLDAVHA, ARM_INS_VRMLSLDAVHAX,
+	ARM_INS_VRMLSLDAVHX, ARM_INS_VRMULH, ARM_INS_VRSHL, ARM_INS_VRSHR,
+	ARM_INS_VRSHRN, ARM_INS_VRSHRNB, ARM_INS_VRSHRNT, ARM_INS_VRSQRTE,
+	ARM_INS_VRSQRTS, ARM_INS_VRSRA, ARM_INS_VRSUBHN, ARM_INS_VSBC,
+	ARM_INS_VSBCI, ARM_INS_VSCCLRM, ARM_INS_VSDOT, ARM_INS_VSELEQ,
+	ARM_INS_VSELGE, ARM_INS_VSELGT, ARM_INS_VSELVS, ARM_INS_VSHL,
+	ARM_INS_VSHLC, ARM_INS_VSHLL, ARM_INS_VSHLLB, ARM_INS_VSHLLT,
+	ARM_INS_VSHR, ARM_INS_VSHRN, ARM_INS_VSHRNB, ARM_INS_VSHRNT,
+	ARM_INS_VSLI, ARM_INS_VSMMLA, ARM_INS_VSQRT, ARM_INS_VSRA, ARM_INS_VSRI,
+	ARM_INS_VST1, ARM_INS_VST2, ARM_INS_VST20, ARM_INS_VST21, ARM_INS_VST3,
+	ARM_INS_VST4, ARM_INS_VST40, ARM_INS_VST41, ARM_INS_VST42,
+	ARM_INS_VST43, ARM_INS_VSTMDB, ARM_INS_VSTMIA, ARM_INS_VSTR,
+	ARM_INS_VSTRB, ARM_INS_VSTRD, ARM_INS_VSTRH, ARM_INS_VSTRW,
+	ARM_INS_VSUB, ARM_INS_VSUBHN, ARM_INS_VSUBL, ARM_INS_VSUBW,
+	ARM_INS_VSUDOT, ARM_INS_VSWP, ARM_INS_VTBL, ARM_INS_VTBX, ARM_INS_VTRN,
+	ARM_INS_VTST, ARM_INS_VUDOT, ARM_INS_VUMMLA, ARM_INS_VUSDOT,
+	ARM_INS_VUSMMLA, ARM_INS_VUZP, ARM_INS_VZIP, ARM_INS_WFE, ARM_INS_WFI,
+	ARM_INS_WLS, ARM_INS_WLSTP, ARM_INS_YIELD,

external/capstone/arch/ARM/ARMInstPrinter.h

@@ -0,0 +1,32 @@
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically translated source file from LLVM. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Only small edits allowed. */
+/* For multiple similar edits, please create a Patch for the translator. */
+
+/* Capstone's C++ file translator: */
+/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
+
+//===- ARMInstPrinter.h - Convert ARM MCInst to assembly syntax -*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This class prints an ARM MCInst to a .s file.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef CS_ARM_INSTPRINTER_H
+#define CS_ARM_INSTPRINTER_H
+
+unsigned translateShiftImm(unsigned imm);
+
+#endif // CS_ARM_INSTPRINTER_H

external/capstone/arch/ARM/ARMLinkage.h

@@ -0,0 +1,22 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
+
+#ifndef CS_ARM_LINKAGE_H
+#define CS_ARM_LINKAGE_H
+
+// Function definitions to call static LLVM functions.
+
+#include "../../MCDisassembler.h"
+#include "../../MCInst.h"
+#include "../../MCRegisterInfo.h"
+#include "../../SStream.h"
+#include "capstone/capstone.h"
+
+DecodeStatus ARM_LLVM_getInstruction(csh handle, const uint8_t *Bytes,
+				     size_t ByteLen, MCInst *MI, uint16_t *Size,
+				     uint64_t Address, void *Info);
+const char *ARM_LLVM_getRegisterName(unsigned RegNo, unsigned AltIdx);
+void ARM_LLVM_printInstruction(MCInst *MI, SStream *O,
+			       void * /* MCRegisterInfo* */ info);
+
+#endif // CS_ARM_LINKAGE_H

external/capstone/arch/ARM/ARMMapping.h

@@ -0,0 +1,88 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
+
+#ifndef CS_ARM_MAPPING_H
+#define CS_ARM_MAPPING_H
+
+#include "../../include/capstone/capstone.h"
+#include "../../utils.h"
+#include "ARMBaseInfo.h"
+
+typedef enum {
+#include "ARMGenCSOpGroup.inc"
+} arm_op_group;
+
+extern const ARMBankedReg_BankedReg *
+ARMBankedReg_lookupBankedRegByEncoding(uint8_t Encoding);
+extern const ARMSysReg_MClassSysReg *
+ARMSysReg_lookupMClassSysRegByEncoding(uint16_t Encoding);
+
+// return name of register in friendly string
+const char *ARM_reg_name(csh handle, unsigned int reg);
+
+void ARM_printer(MCInst *MI, SStream *O, void * /* MCRegisterInfo* */ info);
+
+// given internal insn id, return public instruction ID
+void ARM_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
+
+const char *ARM_insn_name(csh handle, unsigned int id);
+
+const char *ARM_group_name(csh handle, unsigned int id);
+
+// check if this insn is relative branch
+bool ARM_rel_branch(cs_struct *h, unsigned int insn_id);
+
+bool ARM_blx_to_arm_mode(cs_struct *h, unsigned int insn_id);
+
+void ARM_reg_access(const cs_insn *insn, cs_regs regs_read,
+		    uint8_t *regs_read_count, cs_regs regs_write,
+		    uint8_t *regs_write_count);
+
+const ARMBankedReg_BankedReg *
+ARMBankedReg_lookupBankedRegByEncoding(uint8_t encoding);
+
+bool ARM_getInstruction(csh handle, const uint8_t *code, size_t code_len,
+			MCInst *instr, uint16_t *size, uint64_t address,
+			void *info);
+void ARM_set_instr_map_data(MCInst *MI);
+
+void ARM_init_mri(MCRegisterInfo *MRI);
+
+// cs_detail related functions
+void ARM_init_cs_detail(MCInst *MI);
+void ARM_add_cs_detail(MCInst *MI, int /* arm_op_group */ op_group,
+		       va_list args);
+static inline void add_cs_detail(MCInst *MI, int /* arm_op_group */ op_group,
+				 ...)
+{
+	if (!MI->flat_insn->detail)
+		return;
+	va_list args;
+	va_start(args, op_group);
+	ARM_add_cs_detail(MI, op_group, args);
+	va_end(args);
+}
+
+void ARM_insert_detail_op_reg_at(MCInst *MI, unsigned index, arm_reg Reg,
+				 cs_ac_type access);
+void ARM_insert_detail_op_imm_at(MCInst *MI, unsigned index, int64_t Val,
+				 cs_ac_type access);
+void ARM_set_detail_op_reg(MCInst *MI, unsigned OpNum, arm_reg Reg);
+void ARM_set_detail_op_sysop(MCInst *MI, int SysReg, arm_op_type type,
+			     bool IsOutReg, uint8_t Mask, uint16_t Sysm);
+void ARM_set_detail_op_imm(MCInst *MI, unsigned OpNum, arm_op_type ImmType,
+			   int64_t Imm);
+void ARM_set_detail_op_float(MCInst *MI, unsigned OpNum, uint64_t Imm);
+void ARM_set_detail_op_mem(MCInst *MI, unsigned OpNum, bool is_index_reg,
+			   int scale, uint64_t Val);
+void ARM_set_detail_op_mem_offset(MCInst *MI, unsigned OpNum, uint64_t Val,
+				  bool subtracted);
+void ARM_set_detail_op_neon_lane(MCInst *MI, unsigned OpNum);
+
+void ARM_check_updates_flags(MCInst *MI);
+
+void ARM_setup_op(cs_arm_op *op);
+void ARM_add_vector_data(MCInst *MI, arm_vectordata_type data_type);
+void ARM_add_vector_size(MCInst *MI, unsigned size);
+
+#endif // CS_ARM_MAPPING_H

external/capstone/arch/ARM/ARMModule.c

@@ -0,0 +1,52 @@
+/* Capstone Disassembly Engine */
+/* By Dang Hoang Vu <danghvu@gmail.com> 2013 */
+
+#include "capstone/capstone.h"
+#ifdef CAPSTONE_HAS_ARM
+
+#include "ARMModule.h"
+#include "../../MCRegisterInfo.h"
+#include "../../cs_priv.h"
+#include "ARMInstPrinter.h"
+#include "ARMMapping.h"
+
+cs_err ARM_global_init(cs_struct *ud)
+{
+	MCRegisterInfo *mri;
+	mri = cs_mem_malloc(sizeof(*mri));
+
+	ARM_init_mri(mri);
+
+	ud->printer = ARM_printer;
+	ud->printer_info = mri;
+	ud->reg_name = ARM_reg_name;
+	ud->insn_id = ARM_get_insn_id;
+	ud->insn_name = ARM_insn_name;
+	ud->group_name = ARM_group_name;
+	ud->post_printer = NULL;
+#ifndef CAPSTONE_DIET
+	ud->reg_access = ARM_reg_access;
+#endif
+
+	ud->disasm = ARM_getInstruction;
+
+	return CS_ERR_OK;
+}
+
+cs_err ARM_option(cs_struct *handle, cs_opt_type type, size_t value)
+{
+	switch (type) {
+	case CS_OPT_MODE:
+		handle->mode |= (cs_mode)value;
+		break;
+	case CS_OPT_SYNTAX:
+		handle->syntax |= (int)value;
+		break;
+	default:
+		break;
+	}
+
+	return CS_ERR_OK;
+}
+
+#endif

external/capstone/arch/ARM/ARMModule.h

@@ -0,0 +1,12 @@
+/* Capstone Disassembly Engine */
+/* By Travis Finkenauer <tmfinken@gmail.com>, 2018 */
+
+#ifndef CS_ARM_MODULE_H
+#define CS_ARM_MODULE_H
+
+#include "../../utils.h"
+
+cs_err ARM_global_init(cs_struct *ud);
+cs_err ARM_option(cs_struct *handle, cs_opt_type type, size_t value);
+
+#endif