Files
kaizen/external/capstone/MCInstrDesc.h
T
iris 00cc9309cb Squashed 'external/ircolib/' changes from ce3cd726c..de6e324bd
de6e324bd separate emu thread
10d3daf86 Roms List improvements
95d202f37 Let's make the rom list process on a separate thread so the emulator doesnt take ages to load.
fc306967f Wow the ROM Header was just completely busted. Game list view works now
bad1691ee fuck this shit
2b59e5f46 game list in progress
d26417b83 remappable inputs in progress
ac4af8106 input
e72abc240 update readme
430139dc9 Qt6 frontend
3080d4d45 Fix this small bug too
08cd13b85 Cop0 unused functions do not actually pose a threat (as per manual). They don't do anything, so shall we.
61bb4fb44 make idle loop detection a little more specific with where the load goes
b037de4c3 SAZDFsdff
12e81e73e need to figure out why n64-systemtest loops indefinitely at some address that appears to be valid (i think it's me not invalidating the cache properly)
204f0e13b idle skipping seems to work!
cb8bb634a sdkfjlasdf
58e5c89c1 Fix compilation issue on my machine (no idea)
24fb2898e attempting more serious idle skipping
214719577 Place rsp.Step inside cached interpreter. Gains about 3 more fps
bb97dcc23 mmmmm
920b77d38 wjkhasdfjhkasdf
430ccdab4 it's a start...
4f42a673a Cached interpreter plays Mario 64. Start looking into RSP as well
c9a030787 idle skipping works!
5fbda03ce new idea
366637aba Idle skipping... maybe?
609fa2fb0 Cache instructions implemented but broken lmao. Commented out for now
e140a6d12 - Stop using inheritance for CPU, instead use composition. - Introduce KAIZEN_JIT_ENABLED optional define instead of relying on __aarch64__ and the like. - More cache work
68e613057 prep cache impl
811b4d809 fix clang format
fda755f7d idk
d5024ebbf small MI refactor in preparation of (eventually) implementing the RDRAM interface properly
694b45341 Merge commit '206dcdedf195fb320913584180edb12c7731e396' as 'external/SDL'
206dcdedf Squashed 'external/SDL/' content from commit 4d17b99d0a
4d16e1cb4 need to update sdl
848b19920 Fix compilation error
db61b5299 Merge commit 'e94a94559f28e49678fbcf72199a5258137b0fe9' as 'external/imgui'
e94a94559 Squashed 'external/imgui/' content from commit 02e9b8cac
52edb3757 need to update imgui
c1a705e86 Emulate weird JALR behaviour
4b4c32f4b Fix exception for "unusable COP1" in 4 instructions i missed accidentally (again)
df5828142 Bug putting 0s in the log everywhere
f8b580048 Make isviewer a sink to file
8241e9735 Fix exception for "unusable COP1" in 4 instructions i missed accidentally
b29715f20 small changes
d9a620bc1 make use of my new small utility library
0d1aa938e Add 'external/ircolib/' from commit 'ce3cd726c8df8388d554abf8bb55d55020eb4450'
e64eb40b3 Fuck git

git-subtree-dir: external/ircolib
git-subtree-split: de6e324bde
2026-06-15 11:56:38 +02:00

172 lines
5.4 KiB
C++

//===-- llvm/MC/MCInstrDesc.h - Instruction Descriptors -*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file defines the MCOperandInfo and MCInstrDesc classes, which
// are used to describe target instructions and their operands.
//
//===----------------------------------------------------------------------===//
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
#ifndef CS_LLVM_MC_MCINSTRDESC_H
#define CS_LLVM_MC_MCINSTRDESC_H
#include "MCRegisterInfo.h"
#include "capstone/platform.h"
//===----------------------------------------------------------------------===//
// Machine Operand Flags and Description
//===----------------------------------------------------------------------===//
/// Operand constraints. These are encoded in 16 bits with one of the
/// low-order 3 bits specifying that a constraint is present and the
/// corresponding high-order hex digit specifying the constraint value.
/// This allows for a maximum of 3 constraints.
typedef enum {
MCOI_TIED_TO = 0, // Operand tied to another operand.
MCOI_EARLY_CLOBBER // Operand is an early clobber register operand
} MCOI_OperandConstraint;
// Define a macro to produce each constraint value.
#define CONSTRAINT_MCOI_TIED_TO(op) \
((1 << MCOI_TIED_TO) | ((op) << (4 + MCOI_TIED_TO * 4)))
#define CONSTRAINT_MCOI_EARLY_CLOBBER \
(1 << MCOI_EARLY_CLOBBER)
/// OperandFlags - These are flags set on operands, but should be considered
/// private, all access should go through the MCOperandInfo accessors.
/// See the accessors for a description of what these are.
enum MCOI_OperandFlags {
MCOI_LookupPtrRegClass = 0,
MCOI_Predicate,
MCOI_OptionalDef
};
/// Operand Type - Operands are tagged with one of the values of this enum.
enum MCOI_OperandType {
MCOI_OPERAND_UNKNOWN = 0,
MCOI_OPERAND_IMMEDIATE = 1,
MCOI_OPERAND_REGISTER = 2,
MCOI_OPERAND_MEMORY = 3,
MCOI_OPERAND_PCREL = 4,
MCOI_OPERAND_FIRST_GENERIC = 6,
MCOI_OPERAND_GENERIC_0 = 6,
MCOI_OPERAND_GENERIC_1 = 7,
MCOI_OPERAND_GENERIC_2 = 8,
MCOI_OPERAND_GENERIC_3 = 9,
MCOI_OPERAND_GENERIC_4 = 10,
MCOI_OPERAND_GENERIC_5 = 11,
MCOI_OPERAND_LAST_GENERIC = 11,
MCOI_OPERAND_FIRST_GENERIC_IMM = 12,
MCOI_OPERAND_GENERIC_IMM_0 = 12,
MCOI_OPERAND_LAST_GENERIC_IMM = 12,
MCOI_OPERAND_FIRST_TARGET = 13,
};
/// MCOperandInfo - This holds information about one operand of a machine
/// instruction, indicating the register class for register operands, etc.
///
typedef struct MCOperandInfo {
/// This specifies the register class enumeration of the operand
/// if the operand is a register. If isLookupPtrRegClass is set, then this is
/// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to
/// get a dynamic register class.
int16_t RegClass;
/// These are flags from the MCOI::OperandFlags enum.
uint8_t Flags;
/// Information about the type of the operand.
uint8_t OperandType;
/// The lower 3 bits are used to specify which constraints are set.
/// The higher 13 bits are used to specify the value of constraints (4 bits each).
uint16_t Constraints;
/// Currently no other information.
} MCOperandInfo;
//===----------------------------------------------------------------------===//
// Machine Instruction Flags and Description
//===----------------------------------------------------------------------===//
/// MCInstrDesc flags - These should be considered private to the
/// implementation of the MCInstrDesc class. Clients should use the predicate
/// methods on MCInstrDesc, not use these directly. These all correspond to
/// bitfields in the MCInstrDesc::Flags field.
enum {
MCID_Variadic = 0,
MCID_HasOptionalDef,
MCID_Pseudo,
MCID_Return,
MCID_Call,
MCID_Barrier,
MCID_Terminator,
MCID_Branch,
MCID_IndirectBranch,
MCID_Compare,
MCID_MoveImm,
MCID_MoveReg,
MCID_Bitcast,
MCID_Select,
MCID_DelaySlot,
MCID_FoldableAsLoad,
MCID_MayLoad,
MCID_MayStore,
MCID_Predicable,
MCID_NotDuplicable,
MCID_UnmodeledSideEffects,
MCID_Commutable,
MCID_ConvertibleTo3Addr,
MCID_UsesCustomInserter,
MCID_HasPostISelHook,
MCID_Rematerializable,
MCID_CheapAsAMove,
MCID_ExtraSrcRegAllocReq,
MCID_ExtraDefRegAllocReq,
MCID_RegSequence,
MCID_ExtractSubreg,
MCID_InsertSubreg,
MCID_Convergent,
MCID_Add,
MCID_Trap,
};
/// MCInstrDesc - Describe properties that are true of each instruction in the
/// target description file. This captures information about side effects,
/// register use and many other things. There is one instance of this struct
/// for each target instruction class, and the MachineInstr class points to
/// this struct directly to describe itself.
typedef struct MCInstrDesc {
unsigned char NumOperands; // Num of args (may be more if variable_ops)
const MCOperandInfo *OpInfo; // 'NumOperands' entries about operands
} MCInstrDesc;
bool MCOperandInfo_isPredicate(const MCOperandInfo *m);
bool MCOperandInfo_isOptionalDef(const MCOperandInfo *m);
bool MCOperandInfo_isTiedToOp(const MCOperandInfo *m);
int MCOperandInfo_getOperandConstraint(const MCInstrDesc *OpInfo,
unsigned OpNum,
MCOI_OperandConstraint Constraint);
const MCInstrDesc *MCInstrDesc_get(unsigned opcode,
const MCInstrDesc *table,
unsigned tbl_size);
#endif