00cc9309cb
de6e324bdseparate emu thread10d3daf86Roms List improvements95d202f37Let's make the rom list process on a separate thread so the emulator doesnt take ages to load.fc306967fWow the ROM Header was just completely busted. Game list view works nowbad1691eefuck this shit2b59e5f46game list in progressd26417b83remappable inputs in progressac4af8106inpute72abc240update readme430139dc9Qt6 frontend3080d4d45Fix this small bug too08cd13b85Cop0 unused functions do not actually pose a threat (as per manual). They don't do anything, so shall we.61bb4fb44make idle loop detection a little more specific with where the load goesb037de4c3SAZDFsdff12e81e73eneed to figure out why n64-systemtest loops indefinitely at some address that appears to be valid (i think it's me not invalidating the cache properly)204f0e13bidle skipping seems to work!cb8bb634asdkfjlasdf58e5c89c1Fix compilation issue on my machine (no idea)24fb2898eattempting more serious idle skipping214719577Place rsp.Step inside cached interpreter. Gains about 3 more fpsbb97dcc23mmmmm920b77d38wjkhasdfjhkasdf430ccdab4it's a start...4f42a673aCached interpreter plays Mario 64. Start looking into RSP as wellc9a030787idle skipping works!5fbda03cenew idea366637abaIdle skipping... maybe?609fa2fb0Cache instructions implemented but broken lmao. Commented out for nowe140a6d12- Stop using inheritance for CPU, instead use composition. - Introduce KAIZEN_JIT_ENABLED optional define instead of relying on __aarch64__ and the like. - More cache work68e613057prep cache impl811b4d809fix clang formatfda755f7didkd5024ebbfsmall MI refactor in preparation of (eventually) implementing the RDRAM interface properly694b45341Merge commit '206dcdedf195fb320913584180edb12c7731e396' as 'external/SDL'206dcdedfSquashed 'external/SDL/' content from commit 4d17b99d0a4d16e1cb4need to update sdl848b19920Fix compilation errordb61b5299Merge commit 'e94a94559f28e49678fbcf72199a5258137b0fe9' as 'external/imgui'e94a94559Squashed 'external/imgui/' content from commit 02e9b8cac52edb3757need to update imguic1a705e86Emulate weird JALR behaviour4b4c32f4bFix exception for "unusable COP1" in 4 instructions i missed accidentally (again)df5828142Bug putting 0s in the log everywheref8b580048Make isviewer a sink to file8241e9735Fix exception for "unusable COP1" in 4 instructions i missed accidentallyb29715f20small changesd9a620bc1make use of my new small utility library0d1aa938eAdd 'external/ircolib/' from commit 'ce3cd726c8df8388d554abf8bb55d55020eb4450'e64eb40b3Fuck git git-subtree-dir: external/ircolib git-subtree-split:de6e324bde
172 lines
5.4 KiB
C++
172 lines
5.4 KiB
C++
//===-- llvm/MC/MCInstrDesc.h - Instruction Descriptors -*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the MCOperandInfo and MCInstrDesc classes, which
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// are used to describe target instructions and their operands.
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//
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//===----------------------------------------------------------------------===//
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/* Capstone Disassembly Engine */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
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#ifndef CS_LLVM_MC_MCINSTRDESC_H
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#define CS_LLVM_MC_MCINSTRDESC_H
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#include "MCRegisterInfo.h"
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#include "capstone/platform.h"
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//===----------------------------------------------------------------------===//
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// Machine Operand Flags and Description
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//===----------------------------------------------------------------------===//
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/// Operand constraints. These are encoded in 16 bits with one of the
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/// low-order 3 bits specifying that a constraint is present and the
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/// corresponding high-order hex digit specifying the constraint value.
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/// This allows for a maximum of 3 constraints.
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typedef enum {
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MCOI_TIED_TO = 0, // Operand tied to another operand.
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MCOI_EARLY_CLOBBER // Operand is an early clobber register operand
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} MCOI_OperandConstraint;
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// Define a macro to produce each constraint value.
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#define CONSTRAINT_MCOI_TIED_TO(op) \
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((1 << MCOI_TIED_TO) | ((op) << (4 + MCOI_TIED_TO * 4)))
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#define CONSTRAINT_MCOI_EARLY_CLOBBER \
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(1 << MCOI_EARLY_CLOBBER)
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/// OperandFlags - These are flags set on operands, but should be considered
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/// private, all access should go through the MCOperandInfo accessors.
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/// See the accessors for a description of what these are.
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enum MCOI_OperandFlags {
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MCOI_LookupPtrRegClass = 0,
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MCOI_Predicate,
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MCOI_OptionalDef
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};
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/// Operand Type - Operands are tagged with one of the values of this enum.
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enum MCOI_OperandType {
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MCOI_OPERAND_UNKNOWN = 0,
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MCOI_OPERAND_IMMEDIATE = 1,
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MCOI_OPERAND_REGISTER = 2,
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MCOI_OPERAND_MEMORY = 3,
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MCOI_OPERAND_PCREL = 4,
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MCOI_OPERAND_FIRST_GENERIC = 6,
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MCOI_OPERAND_GENERIC_0 = 6,
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MCOI_OPERAND_GENERIC_1 = 7,
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MCOI_OPERAND_GENERIC_2 = 8,
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MCOI_OPERAND_GENERIC_3 = 9,
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MCOI_OPERAND_GENERIC_4 = 10,
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MCOI_OPERAND_GENERIC_5 = 11,
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MCOI_OPERAND_LAST_GENERIC = 11,
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MCOI_OPERAND_FIRST_GENERIC_IMM = 12,
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MCOI_OPERAND_GENERIC_IMM_0 = 12,
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MCOI_OPERAND_LAST_GENERIC_IMM = 12,
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MCOI_OPERAND_FIRST_TARGET = 13,
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};
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/// MCOperandInfo - This holds information about one operand of a machine
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/// instruction, indicating the register class for register operands, etc.
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///
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typedef struct MCOperandInfo {
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/// This specifies the register class enumeration of the operand
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/// if the operand is a register. If isLookupPtrRegClass is set, then this is
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/// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to
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/// get a dynamic register class.
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int16_t RegClass;
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/// These are flags from the MCOI::OperandFlags enum.
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uint8_t Flags;
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/// Information about the type of the operand.
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uint8_t OperandType;
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/// The lower 3 bits are used to specify which constraints are set.
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/// The higher 13 bits are used to specify the value of constraints (4 bits each).
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uint16_t Constraints;
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/// Currently no other information.
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} MCOperandInfo;
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//===----------------------------------------------------------------------===//
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// Machine Instruction Flags and Description
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//===----------------------------------------------------------------------===//
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/// MCInstrDesc flags - These should be considered private to the
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/// implementation of the MCInstrDesc class. Clients should use the predicate
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/// methods on MCInstrDesc, not use these directly. These all correspond to
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/// bitfields in the MCInstrDesc::Flags field.
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enum {
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MCID_Variadic = 0,
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MCID_HasOptionalDef,
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MCID_Pseudo,
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MCID_Return,
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MCID_Call,
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MCID_Barrier,
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MCID_Terminator,
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MCID_Branch,
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MCID_IndirectBranch,
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MCID_Compare,
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MCID_MoveImm,
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MCID_MoveReg,
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MCID_Bitcast,
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MCID_Select,
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MCID_DelaySlot,
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MCID_FoldableAsLoad,
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MCID_MayLoad,
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MCID_MayStore,
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MCID_Predicable,
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MCID_NotDuplicable,
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MCID_UnmodeledSideEffects,
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MCID_Commutable,
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MCID_ConvertibleTo3Addr,
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MCID_UsesCustomInserter,
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MCID_HasPostISelHook,
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MCID_Rematerializable,
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MCID_CheapAsAMove,
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MCID_ExtraSrcRegAllocReq,
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MCID_ExtraDefRegAllocReq,
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MCID_RegSequence,
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MCID_ExtractSubreg,
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MCID_InsertSubreg,
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MCID_Convergent,
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MCID_Add,
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MCID_Trap,
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};
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/// MCInstrDesc - Describe properties that are true of each instruction in the
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/// target description file. This captures information about side effects,
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/// register use and many other things. There is one instance of this struct
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/// for each target instruction class, and the MachineInstr class points to
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/// this struct directly to describe itself.
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typedef struct MCInstrDesc {
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unsigned char NumOperands; // Num of args (may be more if variable_ops)
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const MCOperandInfo *OpInfo; // 'NumOperands' entries about operands
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} MCInstrDesc;
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bool MCOperandInfo_isPredicate(const MCOperandInfo *m);
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bool MCOperandInfo_isOptionalDef(const MCOperandInfo *m);
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bool MCOperandInfo_isTiedToOp(const MCOperandInfo *m);
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int MCOperandInfo_getOperandConstraint(const MCInstrDesc *OpInfo,
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unsigned OpNum,
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MCOI_OperandConstraint Constraint);
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const MCInstrDesc *MCInstrDesc_get(unsigned opcode,
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const MCInstrDesc *table,
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unsigned tbl_size);
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#endif
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