iris
00cc9309cb
de6e324bdseparate emu thread10d3daf86Roms List improvements95d202f37Let's make the rom list process on a separate thread so the emulator doesnt take ages to load.fc306967fWow the ROM Header was just completely busted. Game list view works nowbad1691eefuck this shit2b59e5f46game list in progressd26417b83remappable inputs in progressac4af8106inpute72abc240update readme430139dc9Qt6 frontend3080d4d45Fix this small bug too08cd13b85Cop0 unused functions do not actually pose a threat (as per manual). They don't do anything, so shall we.61bb4fb44make idle loop detection a little more specific with where the load goesb037de4c3SAZDFsdff12e81e73eneed to figure out why n64-systemtest loops indefinitely at some address that appears to be valid (i think it's me not invalidating the cache properly)204f0e13bidle skipping seems to work!cb8bb634asdkfjlasdf58e5c89c1Fix compilation issue on my machine (no idea)24fb2898eattempting more serious idle skipping214719577Place rsp.Step inside cached interpreter. Gains about 3 more fpsbb97dcc23mmmmm920b77d38wjkhasdfjhkasdf430ccdab4it's a start...4f42a673aCached interpreter plays Mario 64. Start looking into RSP as wellc9a030787idle skipping works!5fbda03cenew idea366637abaIdle skipping... maybe?609fa2fb0Cache instructions implemented but broken lmao. Commented out for nowe140a6d12- Stop using inheritance for CPU, instead use composition. - Introduce KAIZEN_JIT_ENABLED optional define instead of relying on __aarch64__ and the like. - More cache work68e613057prep cache impl811b4d809fix clang formatfda755f7didkd5024ebbfsmall MI refactor in preparation of (eventually) implementing the RDRAM interface properly694b45341Merge commit '206dcdedf195fb320913584180edb12c7731e396' as 'external/SDL'206dcdedfSquashed 'external/SDL/' content from commit 4d17b99d0a4d16e1cb4need to update sdl848b19920Fix compilation errordb61b5299Merge commit 'e94a94559f28e49678fbcf72199a5258137b0fe9' as 'external/imgui'e94a94559Squashed 'external/imgui/' content from commit 02e9b8cac52edb3757need to update imguic1a705e86Emulate weird JALR behaviour4b4c32f4bFix exception for "unusable COP1" in 4 instructions i missed accidentally (again)df5828142Bug putting 0s in the log everywheref8b580048Make isviewer a sink to file8241e9735Fix exception for "unusable COP1" in 4 instructions i missed accidentallyb29715f20small changesd9a620bc1make use of my new small utility library0d1aa938eAdd 'external/ircolib/' from commit 'ce3cd726c8df8388d554abf8bb55d55020eb4450'e64eb40b3Fuck git git-subtree-dir: external/ircolib git-subtree-split:de6e324bde
89 lines
2.9 KiB
C
89 lines
2.9 KiB
C
/* Capstone Disassembly Engine */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
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#ifndef CS_ARM_MAPPING_H
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#define CS_ARM_MAPPING_H
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#include "../../include/capstone/capstone.h"
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#include "../../utils.h"
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#include "ARMBaseInfo.h"
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typedef enum {
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#include "ARMGenCSOpGroup.inc"
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} arm_op_group;
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extern const ARMBankedReg_BankedReg *
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ARMBankedReg_lookupBankedRegByEncoding(uint8_t Encoding);
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extern const ARMSysReg_MClassSysReg *
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ARMSysReg_lookupMClassSysRegByEncoding(uint16_t Encoding);
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// return name of register in friendly string
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const char *ARM_reg_name(csh handle, unsigned int reg);
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void ARM_printer(MCInst *MI, SStream *O, void * /* MCRegisterInfo* */ info);
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// given internal insn id, return public instruction ID
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void ARM_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
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const char *ARM_insn_name(csh handle, unsigned int id);
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const char *ARM_group_name(csh handle, unsigned int id);
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// check if this insn is relative branch
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bool ARM_rel_branch(cs_struct *h, unsigned int insn_id);
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bool ARM_blx_to_arm_mode(cs_struct *h, unsigned int insn_id);
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void ARM_reg_access(const cs_insn *insn, cs_regs regs_read,
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uint8_t *regs_read_count, cs_regs regs_write,
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uint8_t *regs_write_count);
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const ARMBankedReg_BankedReg *
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ARMBankedReg_lookupBankedRegByEncoding(uint8_t encoding);
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bool ARM_getInstruction(csh handle, const uint8_t *code, size_t code_len,
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MCInst *instr, uint16_t *size, uint64_t address,
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void *info);
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void ARM_set_instr_map_data(MCInst *MI);
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void ARM_init_mri(MCRegisterInfo *MRI);
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// cs_detail related functions
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void ARM_init_cs_detail(MCInst *MI);
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void ARM_add_cs_detail(MCInst *MI, int /* arm_op_group */ op_group,
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va_list args);
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static inline void add_cs_detail(MCInst *MI, int /* arm_op_group */ op_group,
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...)
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{
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if (!MI->flat_insn->detail)
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return;
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va_list args;
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va_start(args, op_group);
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ARM_add_cs_detail(MI, op_group, args);
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va_end(args);
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}
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void ARM_insert_detail_op_reg_at(MCInst *MI, unsigned index, arm_reg Reg,
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cs_ac_type access);
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void ARM_insert_detail_op_imm_at(MCInst *MI, unsigned index, int64_t Val,
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cs_ac_type access);
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void ARM_set_detail_op_reg(MCInst *MI, unsigned OpNum, arm_reg Reg);
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void ARM_set_detail_op_sysop(MCInst *MI, int SysReg, arm_op_type type,
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bool IsOutReg, uint8_t Mask, uint16_t Sysm);
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void ARM_set_detail_op_imm(MCInst *MI, unsigned OpNum, arm_op_type ImmType,
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int64_t Imm);
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void ARM_set_detail_op_float(MCInst *MI, unsigned OpNum, uint64_t Imm);
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void ARM_set_detail_op_mem(MCInst *MI, unsigned OpNum, bool is_index_reg,
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int scale, uint64_t Val);
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void ARM_set_detail_op_mem_offset(MCInst *MI, unsigned OpNum, uint64_t Val,
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bool subtracted);
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void ARM_set_detail_op_neon_lane(MCInst *MI, unsigned OpNum);
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void ARM_check_updates_flags(MCInst *MI);
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void ARM_setup_op(cs_arm_op *op);
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void ARM_add_vector_data(MCInst *MI, arm_vectordata_type data_type);
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void ARM_add_vector_size(MCInst *MI, unsigned size);
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#endif // CS_ARM_MAPPING_H
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