iris
00cc9309cb
de6e324bdseparate emu thread10d3daf86Roms List improvements95d202f37Let's make the rom list process on a separate thread so the emulator doesnt take ages to load.fc306967fWow the ROM Header was just completely busted. Game list view works nowbad1691eefuck this shit2b59e5f46game list in progressd26417b83remappable inputs in progressac4af8106inpute72abc240update readme430139dc9Qt6 frontend3080d4d45Fix this small bug too08cd13b85Cop0 unused functions do not actually pose a threat (as per manual). They don't do anything, so shall we.61bb4fb44make idle loop detection a little more specific with where the load goesb037de4c3SAZDFsdff12e81e73eneed to figure out why n64-systemtest loops indefinitely at some address that appears to be valid (i think it's me not invalidating the cache properly)204f0e13bidle skipping seems to work!cb8bb634asdkfjlasdf58e5c89c1Fix compilation issue on my machine (no idea)24fb2898eattempting more serious idle skipping214719577Place rsp.Step inside cached interpreter. Gains about 3 more fpsbb97dcc23mmmmm920b77d38wjkhasdfjhkasdf430ccdab4it's a start...4f42a673aCached interpreter plays Mario 64. Start looking into RSP as wellc9a030787idle skipping works!5fbda03cenew idea366637abaIdle skipping... maybe?609fa2fb0Cache instructions implemented but broken lmao. Commented out for nowe140a6d12- Stop using inheritance for CPU, instead use composition. - Introduce KAIZEN_JIT_ENABLED optional define instead of relying on __aarch64__ and the like. - More cache work68e613057prep cache impl811b4d809fix clang formatfda755f7didkd5024ebbfsmall MI refactor in preparation of (eventually) implementing the RDRAM interface properly694b45341Merge commit '206dcdedf195fb320913584180edb12c7731e396' as 'external/SDL'206dcdedfSquashed 'external/SDL/' content from commit 4d17b99d0a4d16e1cb4need to update sdl848b19920Fix compilation errordb61b5299Merge commit 'e94a94559f28e49678fbcf72199a5258137b0fe9' as 'external/imgui'e94a94559Squashed 'external/imgui/' content from commit 02e9b8cac52edb3757need to update imguic1a705e86Emulate weird JALR behaviour4b4c32f4bFix exception for "unusable COP1" in 4 instructions i missed accidentally (again)df5828142Bug putting 0s in the log everywheref8b580048Make isviewer a sink to file8241e9735Fix exception for "unusable COP1" in 4 instructions i missed accidentallyb29715f20small changesd9a620bc1make use of my new small utility library0d1aa938eAdd 'external/ircolib/' from commit 'ce3cd726c8df8388d554abf8bb55d55020eb4450'e64eb40b3Fuck git git-subtree-dir: external/ircolib git-subtree-split:de6e324bde
159 lines
4.9 KiB
C
159 lines
4.9 KiB
C
#include "../../SStream.h"
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#include "../../MCInst.h"
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/* Capstone Disassembly Engine, http://www.capstone-engine.org */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
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/* Rot127 <unisono@quyllur.org> 2022-2023 */
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/* Automatically translated source file from LLVM. */
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/* LLVM-commit: <commit> */
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/* LLVM-tag: <tag> */
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/* Only small edits allowed. */
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/* For multiple similar edits, please create a Patch for the translator. */
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/* Capstone's C++ file translator: */
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/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
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//=== MipsInstPrinter.h - Convert Mips MCInst to assembly syntax -*- C++ -*-==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This class prints a Mips MCInst to a .s file.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSINSTPRINTER_H
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#define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSINSTPRINTER_H
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#include <stdio.h>
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#include <string.h>
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#include <stdlib.h>
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#include <capstone/platform.h>
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#include "../../MCInstPrinter.h"
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#include "../../cs_priv.h"
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#define CONCAT(a, b) CONCAT_(a, b)
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#define CONCAT_(a, b) a##_##b
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// These enumeration declarations were originally in MipsInstrInfo.h but
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// had to be moved here to avoid circular dependencies between
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// LLVMMipsCodeGen and LLVMMipsAsmPrinter.
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// CS namespace begin: Mips
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// Mips Branch Codes
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typedef enum MipsFPBranchCode {
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Mips_BRANCH_F,
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Mips_BRANCH_T,
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Mips_BRANCH_FL,
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Mips_BRANCH_TL,
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Mips_BRANCH_INVALID
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} Mips_FPBranchCode;
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// Mips Condition Codes
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typedef enum MipsCondCode {
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// To be used with float branch True
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Mips_FCOND_F,
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Mips_FCOND_UN,
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Mips_FCOND_OEQ,
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Mips_FCOND_UEQ,
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Mips_FCOND_OLT,
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Mips_FCOND_ULT,
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Mips_FCOND_OLE,
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Mips_FCOND_ULE,
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Mips_FCOND_SF,
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Mips_FCOND_NGLE,
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Mips_FCOND_SEQ,
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Mips_FCOND_NGL,
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Mips_FCOND_LT,
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Mips_FCOND_NGE,
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Mips_FCOND_LE,
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Mips_FCOND_NGT,
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// To be used with float branch False
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// This conditions have the same mnemonic as the
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// above ones, but are used with a branch False;
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Mips_FCOND_T,
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Mips_FCOND_OR,
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Mips_FCOND_UNE,
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Mips_FCOND_ONE,
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Mips_FCOND_UGE,
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Mips_FCOND_OGE,
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Mips_FCOND_UGT,
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Mips_FCOND_OGT,
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Mips_FCOND_ST,
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Mips_FCOND_GLE,
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Mips_FCOND_SNE,
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Mips_FCOND_GL,
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Mips_FCOND_NLT,
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Mips_FCOND_GE,
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Mips_FCOND_NLE,
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Mips_FCOND_GT
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} Mips_CondCode;
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static const char *MipsFCCToString(Mips_CondCode CC);
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// CS namespace end: Mips
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// end namespace Mips
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// Autogenerated by tblgen.
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static const char *getRegisterName(unsigned RegNo);
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static void printInstruction(MCInst *MI, uint64_t Address, SStream *O);
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static bool printAliasInstr(MCInst *MI, uint64_t Address, SStream *OS);
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static void printCustomAliasOperand(MCInst *MI, uint64_t Address, unsigned OpIdx,
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unsigned PrintMethodIdx, SStream *O);
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static void printOperand(MCInst *MI, unsigned OpNo, SStream *O);
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static void printJumpOperand(MCInst *MI, unsigned OpNo, SStream *O);
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static void printBranchOperand(MCInst *MI, uint64_t Address, unsigned OpNo,
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SStream *O);
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#define DECLARE_printUImm_2(Bits, Offset) \
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static void CONCAT(printUImm, CONCAT(Bits, Offset))( \
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MCInst *MI, int opNum, SStream *O)
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#define DECLARE_printUImm(Bits) \
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static void CONCAT(printUImm, CONCAT(Bits, 0))( \
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MCInst *MI, int opNum, SStream *O)
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DECLARE_printUImm(0);
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DECLARE_printUImm(1);
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DECLARE_printUImm(10);
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DECLARE_printUImm(12);
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DECLARE_printUImm(16);
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DECLARE_printUImm(2);
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DECLARE_printUImm(20);
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DECLARE_printUImm(26);
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DECLARE_printUImm(3);
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DECLARE_printUImm(32);
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DECLARE_printUImm(4);
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DECLARE_printUImm(5);
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DECLARE_printUImm(6);
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DECLARE_printUImm(7);
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DECLARE_printUImm(8);
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DECLARE_printUImm_2(2, 1);
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DECLARE_printUImm_2(5, 1);
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DECLARE_printUImm_2(5, 32);
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DECLARE_printUImm_2(5, 33);
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DECLARE_printUImm_2(6, 1);
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DECLARE_printUImm_2(6, 2);
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static void printMemOperand(MCInst *MI, int opNum, SStream *O);
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static void printMemOperandEA(MCInst *MI, int opNum, SStream *O);
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static void printFCCOperand(MCInst *MI, int opNum, SStream *O);
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static bool printAlias(const char *Str, const MCInst *MI, uint64_t Address,
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unsigned OpNo, SStream *OS, bool IsBranch);
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static bool printAlias2(const char *Str, const MCInst *MI, uint64_t Address,
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unsigned OpNo0, unsigned OpNo1, SStream *OS,
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bool IsBranch);
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static bool printAlias3(const char *Str, const MCInst *MI, uint64_t Address,
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unsigned OpNo0, unsigned OpNo1, unsigned OpNo2, SStream *OS);
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static bool printAlias4(const MCInst *MI, uint64_t Address, SStream *OS);
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static void printRegisterList(MCInst *MI, int opNum, SStream *O);
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static void printNanoMipsRegisterList(MCInst *MI, int opNum, SStream *O);
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static void printHi20(MCInst *MI, int OpNum, SStream *O);
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static void printHi20PCRel(MCInst *MI, uint64_t Address, int OpNum, SStream *O);
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static void printPCRel(MCInst *MI, uint64_t Address, int OpNum, SStream *O);
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#endif
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