iris
00cc9309cb
de6e324bdseparate emu thread10d3daf86Roms List improvements95d202f37Let's make the rom list process on a separate thread so the emulator doesnt take ages to load.fc306967fWow the ROM Header was just completely busted. Game list view works nowbad1691eefuck this shit2b59e5f46game list in progressd26417b83remappable inputs in progressac4af8106inpute72abc240update readme430139dc9Qt6 frontend3080d4d45Fix this small bug too08cd13b85Cop0 unused functions do not actually pose a threat (as per manual). They don't do anything, so shall we.61bb4fb44make idle loop detection a little more specific with where the load goesb037de4c3SAZDFsdff12e81e73eneed to figure out why n64-systemtest loops indefinitely at some address that appears to be valid (i think it's me not invalidating the cache properly)204f0e13bidle skipping seems to work!cb8bb634asdkfjlasdf58e5c89c1Fix compilation issue on my machine (no idea)24fb2898eattempting more serious idle skipping214719577Place rsp.Step inside cached interpreter. Gains about 3 more fpsbb97dcc23mmmmm920b77d38wjkhasdfjhkasdf430ccdab4it's a start...4f42a673aCached interpreter plays Mario 64. Start looking into RSP as wellc9a030787idle skipping works!5fbda03cenew idea366637abaIdle skipping... maybe?609fa2fb0Cache instructions implemented but broken lmao. Commented out for nowe140a6d12- Stop using inheritance for CPU, instead use composition. - Introduce KAIZEN_JIT_ENABLED optional define instead of relying on __aarch64__ and the like. - More cache work68e613057prep cache impl811b4d809fix clang formatfda755f7didkd5024ebbfsmall MI refactor in preparation of (eventually) implementing the RDRAM interface properly694b45341Merge commit '206dcdedf195fb320913584180edb12c7731e396' as 'external/SDL'206dcdedfSquashed 'external/SDL/' content from commit 4d17b99d0a4d16e1cb4need to update sdl848b19920Fix compilation errordb61b5299Merge commit 'e94a94559f28e49678fbcf72199a5258137b0fe9' as 'external/imgui'e94a94559Squashed 'external/imgui/' content from commit 02e9b8cac52edb3757need to update imguic1a705e86Emulate weird JALR behaviour4b4c32f4bFix exception for "unusable COP1" in 4 instructions i missed accidentally (again)df5828142Bug putting 0s in the log everywheref8b580048Make isviewer a sink to file8241e9735Fix exception for "unusable COP1" in 4 instructions i missed accidentallyb29715f20small changesd9a620bc1make use of my new small utility library0d1aa938eAdd 'external/ircolib/' from commit 'ce3cd726c8df8388d554abf8bb55d55020eb4450'e64eb40b3Fuck git git-subtree-dir: external/ircolib git-subtree-split:de6e324bde
484 lines
29 KiB
C
484 lines
29 KiB
C
/*===-- X86DisassemblerDecoderCommon.h - Disassembler decoder -----*- C -*-===*
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*
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* The LLVM Compiler Infrastructure
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*
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* This file is distributed under the University of Illinois Open Source
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* License. See LICENSE.TXT for details.
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*
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*===----------------------------------------------------------------------===*
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*
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* This file is part of the X86 Disassembler.
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* It contains common definitions used by both the disassembler and the table
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* generator.
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* Documentation for the disassembler can be found in X86Disassembler.h.
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*
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*===----------------------------------------------------------------------===*/
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/* Capstone Disassembly Engine */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
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/*
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* This header file provides those definitions that need to be shared between
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* the decoder and the table generator in a C-friendly manner.
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*/
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#ifndef CS_X86_DISASSEMBLERDECODERCOMMON_H
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#define CS_X86_DISASSEMBLERDECODERCOMMON_H
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#define INSTRUCTIONS_SYM x86DisassemblerInstrSpecifiers
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#define CONTEXTS_SYM x86DisassemblerContexts
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#define ONEBYTE_SYM x86DisassemblerOneByteOpcodes
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#define TWOBYTE_SYM x86DisassemblerTwoByteOpcodes
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#define THREEBYTE38_SYM x86DisassemblerThreeByte38Opcodes
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#define THREEBYTE3A_SYM x86DisassemblerThreeByte3AOpcodes
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#define XOP8_MAP_SYM x86DisassemblerXOP8Opcodes
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#define XOP9_MAP_SYM x86DisassemblerXOP9Opcodes
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#define XOPA_MAP_SYM x86DisassemblerXOPAOpcodes
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#define THREEDNOW_MAP_SYM x86Disassembler3DNowOpcodes
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/*
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* Attributes of an instruction that must be known before the opcode can be
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* processed correctly. Most of these indicate the presence of particular
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* prefixes, but ATTR_64BIT is simply an attribute of the decoding context.
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*/
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#define ATTRIBUTE_BITS \
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ENUM_ENTRY(ATTR_NONE, 0x00) \
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ENUM_ENTRY(ATTR_64BIT, (0x1 << 0)) \
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ENUM_ENTRY(ATTR_XS, (0x1 << 1)) \
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ENUM_ENTRY(ATTR_XD, (0x1 << 2)) \
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ENUM_ENTRY(ATTR_REXW, (0x1 << 3)) \
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ENUM_ENTRY(ATTR_OPSIZE, (0x1 << 4)) \
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ENUM_ENTRY(ATTR_ADSIZE, (0x1 << 5)) \
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ENUM_ENTRY(ATTR_VEX, (0x1 << 6)) \
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ENUM_ENTRY(ATTR_VEXL, (0x1 << 7)) \
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ENUM_ENTRY(ATTR_EVEX, (0x1 << 8)) \
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ENUM_ENTRY(ATTR_EVEXL, (0x1 << 9)) \
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ENUM_ENTRY(ATTR_EVEXL2, (0x1 << 10)) \
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ENUM_ENTRY(ATTR_EVEXK, (0x1 << 11)) \
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ENUM_ENTRY(ATTR_EVEXKZ, (0x1 << 12)) \
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ENUM_ENTRY(ATTR_EVEXB, (0x1 << 13))
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#define ENUM_ENTRY(n, v) n = v,
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enum attributeBits {
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ATTRIBUTE_BITS
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ATTR_max
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};
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#undef ENUM_ENTRY
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/*
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* Combinations of the above attributes that are relevant to instruction
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* decode. Although other combinations are possible, they can be reduced to
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* these without affecting the ultimately decoded instruction.
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*/
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// Class name Rank Rationale for rank assignment
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#define INSTRUCTION_CONTEXTS \
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ENUM_ENTRY(IC, 0, "says nothing about the instruction") \
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ENUM_ENTRY(IC_64BIT, 1, "says the instruction applies in " \
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"64-bit mode but no more") \
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ENUM_ENTRY(IC_OPSIZE, 3, "requires an OPSIZE prefix, so " \
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"operands change width") \
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ENUM_ENTRY(IC_ADSIZE, 3, "requires an ADSIZE prefix, so " \
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"operands change width") \
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ENUM_ENTRY(IC_OPSIZE_ADSIZE, 4, "requires ADSIZE and OPSIZE prefixes") \
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ENUM_ENTRY(IC_XD, 2, "may say something about the opcode " \
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"but not the operands") \
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ENUM_ENTRY(IC_XS, 2, "may say something about the opcode " \
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"but not the operands") \
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ENUM_ENTRY(IC_XD_OPSIZE, 3, "requires an OPSIZE prefix, so " \
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"operands change width") \
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ENUM_ENTRY(IC_XS_OPSIZE, 3, "requires an OPSIZE prefix, so " \
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"operands change width") \
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ENUM_ENTRY(IC_XD_ADSIZE, 3, "requires an ADSIZE prefix, so " \
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"operands change width") \
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ENUM_ENTRY(IC_XS_ADSIZE, 3, "requires an ADSIZE prefix, so " \
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"operands change width") \
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ENUM_ENTRY(IC_64BIT_REXW, 5, "requires a REX.W prefix, so operands "\
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"change width; overrides IC_OPSIZE") \
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ENUM_ENTRY(IC_64BIT_REXW_ADSIZE, 6, "requires a REX.W prefix and 0x67 " \
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"prefix") \
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ENUM_ENTRY(IC_64BIT_OPSIZE, 3, "Just as meaningful as IC_OPSIZE") \
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ENUM_ENTRY(IC_64BIT_ADSIZE, 3, "Just as meaningful as IC_ADSIZE") \
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ENUM_ENTRY(IC_64BIT_OPSIZE_ADSIZE, 4, "Just as meaningful as IC_OPSIZE/" \
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"IC_ADSIZE") \
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ENUM_ENTRY(IC_64BIT_XD, 6, "XD instructions are SSE; REX.W is " \
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"secondary") \
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ENUM_ENTRY(IC_64BIT_XS, 6, "Just as meaningful as IC_64BIT_XD") \
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ENUM_ENTRY(IC_64BIT_XD_OPSIZE, 3, "Just as meaningful as IC_XD_OPSIZE") \
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ENUM_ENTRY(IC_64BIT_XS_OPSIZE, 3, "Just as meaningful as IC_XS_OPSIZE") \
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ENUM_ENTRY(IC_64BIT_XD_ADSIZE, 3, "Just as meaningful as IC_XD_ADSIZE") \
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ENUM_ENTRY(IC_64BIT_XS_ADSIZE, 3, "Just as meaningful as IC_XS_ADSIZE") \
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ENUM_ENTRY(IC_64BIT_REXW_XS, 7, "OPSIZE could mean a different " \
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"opcode") \
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ENUM_ENTRY(IC_64BIT_REXW_XD, 7, "Just as meaningful as " \
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"IC_64BIT_REXW_XS") \
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ENUM_ENTRY(IC_64BIT_REXW_OPSIZE, 8, "The Dynamic Duo! Prefer over all " \
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"else because this changes most " \
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"operands' meaning") \
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ENUM_ENTRY(IC_VEX, 1, "requires a VEX prefix") \
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ENUM_ENTRY(IC_VEX_XS, 2, "requires VEX and the XS prefix") \
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ENUM_ENTRY(IC_VEX_XD, 2, "requires VEX and the XD prefix") \
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ENUM_ENTRY(IC_VEX_OPSIZE, 2, "requires VEX and the OpSize prefix") \
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ENUM_ENTRY(IC_VEX_W, 3, "requires VEX and the W prefix") \
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ENUM_ENTRY(IC_VEX_W_XS, 4, "requires VEX, W, and XS prefix") \
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ENUM_ENTRY(IC_VEX_W_XD, 4, "requires VEX, W, and XD prefix") \
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ENUM_ENTRY(IC_VEX_W_OPSIZE, 4, "requires VEX, W, and OpSize") \
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ENUM_ENTRY(IC_VEX_L, 3, "requires VEX and the L prefix") \
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ENUM_ENTRY(IC_VEX_L_XS, 4, "requires VEX and the L and XS prefix")\
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ENUM_ENTRY(IC_VEX_L_XD, 4, "requires VEX and the L and XD prefix")\
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ENUM_ENTRY(IC_VEX_L_OPSIZE, 4, "requires VEX, L, and OpSize") \
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ENUM_ENTRY(IC_VEX_L_W, 4, "requires VEX, L and W") \
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ENUM_ENTRY(IC_VEX_L_W_XS, 5, "requires VEX, L, W and XS prefix") \
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ENUM_ENTRY(IC_VEX_L_W_XD, 5, "requires VEX, L, W and XD prefix") \
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ENUM_ENTRY(IC_VEX_L_W_OPSIZE, 5, "requires VEX, L, W and OpSize") \
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ENUM_ENTRY(IC_EVEX, 1, "requires an EVEX prefix") \
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ENUM_ENTRY(IC_EVEX_XS, 2, "requires EVEX and the XS prefix") \
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ENUM_ENTRY(IC_EVEX_XD, 2, "requires EVEX and the XD prefix") \
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ENUM_ENTRY(IC_EVEX_OPSIZE, 2, "requires EVEX and the OpSize prefix") \
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ENUM_ENTRY(IC_EVEX_W, 3, "requires EVEX and the W prefix") \
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ENUM_ENTRY(IC_EVEX_W_XS, 4, "requires EVEX, W, and XS prefix") \
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ENUM_ENTRY(IC_EVEX_W_XD, 4, "requires EVEX, W, and XD prefix") \
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ENUM_ENTRY(IC_EVEX_W_OPSIZE, 4, "requires EVEX, W, and OpSize") \
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ENUM_ENTRY(IC_EVEX_L, 3, "requires EVEX and the L prefix") \
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ENUM_ENTRY(IC_EVEX_L_XS, 4, "requires EVEX and the L and XS prefix")\
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ENUM_ENTRY(IC_EVEX_L_XD, 4, "requires EVEX and the L and XD prefix")\
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ENUM_ENTRY(IC_EVEX_L_OPSIZE, 4, "requires EVEX, L, and OpSize") \
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ENUM_ENTRY(IC_EVEX_L_W, 3, "requires EVEX, L and W") \
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ENUM_ENTRY(IC_EVEX_L_W_XS, 4, "requires EVEX, L, W and XS prefix") \
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ENUM_ENTRY(IC_EVEX_L_W_XD, 4, "requires EVEX, L, W and XD prefix") \
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ENUM_ENTRY(IC_EVEX_L_W_OPSIZE, 4, "requires EVEX, L, W and OpSize") \
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ENUM_ENTRY(IC_EVEX_L2, 3, "requires EVEX and the L2 prefix") \
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ENUM_ENTRY(IC_EVEX_L2_XS, 4, "requires EVEX and the L2 and XS prefix")\
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ENUM_ENTRY(IC_EVEX_L2_XD, 4, "requires EVEX and the L2 and XD prefix")\
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ENUM_ENTRY(IC_EVEX_L2_OPSIZE, 4, "requires EVEX, L2, and OpSize") \
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ENUM_ENTRY(IC_EVEX_L2_W, 3, "requires EVEX, L2 and W") \
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ENUM_ENTRY(IC_EVEX_L2_W_XS, 4, "requires EVEX, L2, W and XS prefix") \
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ENUM_ENTRY(IC_EVEX_L2_W_XD, 4, "requires EVEX, L2, W and XD prefix") \
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ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE, 4, "requires EVEX, L2, W and OpSize") \
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ENUM_ENTRY(IC_EVEX_K, 1, "requires an EVEX_K prefix") \
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ENUM_ENTRY(IC_EVEX_XS_K, 2, "requires EVEX_K and the XS prefix") \
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ENUM_ENTRY(IC_EVEX_XD_K, 2, "requires EVEX_K and the XD prefix") \
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ENUM_ENTRY(IC_EVEX_OPSIZE_K, 2, "requires EVEX_K and the OpSize prefix") \
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ENUM_ENTRY(IC_EVEX_W_K, 3, "requires EVEX_K and the W prefix") \
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ENUM_ENTRY(IC_EVEX_W_XS_K, 4, "requires EVEX_K, W, and XS prefix") \
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ENUM_ENTRY(IC_EVEX_W_XD_K, 4, "requires EVEX_K, W, and XD prefix") \
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ENUM_ENTRY(IC_EVEX_W_OPSIZE_K, 4, "requires EVEX_K, W, and OpSize") \
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ENUM_ENTRY(IC_EVEX_L_K, 3, "requires EVEX_K and the L prefix") \
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ENUM_ENTRY(IC_EVEX_L_XS_K, 4, "requires EVEX_K and the L and XS prefix")\
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ENUM_ENTRY(IC_EVEX_L_XD_K, 4, "requires EVEX_K and the L and XD prefix")\
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ENUM_ENTRY(IC_EVEX_L_OPSIZE_K, 4, "requires EVEX_K, L, and OpSize") \
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ENUM_ENTRY(IC_EVEX_L_W_K, 3, "requires EVEX_K, L and W") \
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ENUM_ENTRY(IC_EVEX_L_W_XS_K, 4, "requires EVEX_K, L, W and XS prefix") \
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ENUM_ENTRY(IC_EVEX_L_W_XD_K, 4, "requires EVEX_K, L, W and XD prefix") \
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ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_K, 4, "requires EVEX_K, L, W and OpSize") \
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ENUM_ENTRY(IC_EVEX_L2_K, 3, "requires EVEX_K and the L2 prefix") \
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ENUM_ENTRY(IC_EVEX_L2_XS_K, 4, "requires EVEX_K and the L2 and XS prefix")\
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ENUM_ENTRY(IC_EVEX_L2_XD_K, 4, "requires EVEX_K and the L2 and XD prefix")\
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ENUM_ENTRY(IC_EVEX_L2_OPSIZE_K, 4, "requires EVEX_K, L2, and OpSize") \
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ENUM_ENTRY(IC_EVEX_L2_W_K, 3, "requires EVEX_K, L2 and W") \
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ENUM_ENTRY(IC_EVEX_L2_W_XS_K, 4, "requires EVEX_K, L2, W and XS prefix") \
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ENUM_ENTRY(IC_EVEX_L2_W_XD_K, 4, "requires EVEX_K, L2, W and XD prefix") \
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ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_K, 4, "requires EVEX_K, L2, W and OpSize") \
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ENUM_ENTRY(IC_EVEX_B, 1, "requires an EVEX_B prefix") \
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ENUM_ENTRY(IC_EVEX_XS_B, 2, "requires EVEX_B and the XS prefix") \
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ENUM_ENTRY(IC_EVEX_XD_B, 2, "requires EVEX_B and the XD prefix") \
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ENUM_ENTRY(IC_EVEX_OPSIZE_B, 2, "requires EVEX_B and the OpSize prefix") \
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ENUM_ENTRY(IC_EVEX_W_B, 3, "requires EVEX_B and the W prefix") \
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ENUM_ENTRY(IC_EVEX_W_XS_B, 4, "requires EVEX_B, W, and XS prefix") \
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ENUM_ENTRY(IC_EVEX_W_XD_B, 4, "requires EVEX_B, W, and XD prefix") \
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ENUM_ENTRY(IC_EVEX_W_OPSIZE_B, 4, "requires EVEX_B, W, and OpSize") \
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ENUM_ENTRY(IC_EVEX_L_B, 3, "requires EVEX_B and the L prefix") \
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ENUM_ENTRY(IC_EVEX_L_XS_B, 4, "requires EVEX_B and the L and XS prefix")\
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ENUM_ENTRY(IC_EVEX_L_XD_B, 4, "requires EVEX_B and the L and XD prefix")\
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ENUM_ENTRY(IC_EVEX_L_OPSIZE_B, 4, "requires EVEX_B, L, and OpSize") \
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ENUM_ENTRY(IC_EVEX_L_W_B, 3, "requires EVEX_B, L and W") \
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ENUM_ENTRY(IC_EVEX_L_W_XS_B, 4, "requires EVEX_B, L, W and XS prefix") \
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ENUM_ENTRY(IC_EVEX_L_W_XD_B, 4, "requires EVEX_B, L, W and XD prefix") \
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ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_B, 4, "requires EVEX_B, L, W and OpSize") \
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ENUM_ENTRY(IC_EVEX_L2_B, 3, "requires EVEX_B and the L2 prefix") \
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ENUM_ENTRY(IC_EVEX_L2_XS_B, 4, "requires EVEX_B and the L2 and XS prefix")\
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ENUM_ENTRY(IC_EVEX_L2_XD_B, 4, "requires EVEX_B and the L2 and XD prefix")\
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ENUM_ENTRY(IC_EVEX_L2_OPSIZE_B, 4, "requires EVEX_B, L2, and OpSize") \
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ENUM_ENTRY(IC_EVEX_L2_W_B, 3, "requires EVEX_B, L2 and W") \
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ENUM_ENTRY(IC_EVEX_L2_W_XS_B, 4, "requires EVEX_B, L2, W and XS prefix") \
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ENUM_ENTRY(IC_EVEX_L2_W_XD_B, 4, "requires EVEX_B, L2, W and XD prefix") \
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ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_B, 4, "requires EVEX_B, L2, W and OpSize") \
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ENUM_ENTRY(IC_EVEX_K_B, 1, "requires EVEX_B and EVEX_K prefix") \
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ENUM_ENTRY(IC_EVEX_XS_K_B, 2, "requires EVEX_B, EVEX_K and the XS prefix") \
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ENUM_ENTRY(IC_EVEX_XD_K_B, 2, "requires EVEX_B, EVEX_K and the XD prefix") \
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ENUM_ENTRY(IC_EVEX_OPSIZE_K_B, 2, "requires EVEX_B, EVEX_K and the OpSize prefix") \
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ENUM_ENTRY(IC_EVEX_W_K_B, 3, "requires EVEX_B, EVEX_K and the W prefix") \
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ENUM_ENTRY(IC_EVEX_W_XS_K_B, 4, "requires EVEX_B, EVEX_K, W, and XS prefix") \
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ENUM_ENTRY(IC_EVEX_W_XD_K_B, 4, "requires EVEX_B, EVEX_K, W, and XD prefix") \
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ENUM_ENTRY(IC_EVEX_W_OPSIZE_K_B, 4, "requires EVEX_B, EVEX_K, W, and OpSize") \
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ENUM_ENTRY(IC_EVEX_L_K_B, 3, "requires EVEX_B, EVEX_K and the L prefix") \
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ENUM_ENTRY(IC_EVEX_L_XS_K_B, 4, "requires EVEX_B, EVEX_K and the L and XS prefix")\
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ENUM_ENTRY(IC_EVEX_L_XD_K_B, 4, "requires EVEX_B, EVEX_K and the L and XD prefix")\
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ENUM_ENTRY(IC_EVEX_L_OPSIZE_K_B, 4, "requires EVEX_B, EVEX_K, L, and OpSize") \
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ENUM_ENTRY(IC_EVEX_L_W_K_B, 3, "requires EVEX_B, EVEX_K, L and W") \
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ENUM_ENTRY(IC_EVEX_L_W_XS_K_B, 4, "requires EVEX_B, EVEX_K, L, W and XS prefix") \
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ENUM_ENTRY(IC_EVEX_L_W_XD_K_B, 4, "requires EVEX_B, EVEX_K, L, W and XD prefix") \
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ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_K_B,4, "requires EVEX_B, EVEX_K, L, W and OpSize") \
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ENUM_ENTRY(IC_EVEX_L2_K_B, 3, "requires EVEX_B, EVEX_K and the L2 prefix") \
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ENUM_ENTRY(IC_EVEX_L2_XS_K_B, 4, "requires EVEX_B, EVEX_K and the L2 and XS prefix")\
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ENUM_ENTRY(IC_EVEX_L2_XD_K_B, 4, "requires EVEX_B, EVEX_K and the L2 and XD prefix")\
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ENUM_ENTRY(IC_EVEX_L2_OPSIZE_K_B, 4, "requires EVEX_B, EVEX_K, L2, and OpSize") \
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ENUM_ENTRY(IC_EVEX_L2_W_K_B, 3, "requires EVEX_B, EVEX_K, L2 and W") \
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ENUM_ENTRY(IC_EVEX_L2_W_XS_K_B, 4, "requires EVEX_B, EVEX_K, L2, W and XS prefix") \
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ENUM_ENTRY(IC_EVEX_L2_W_XD_K_B, 4, "requires EVEX_B, EVEX_K, L2, W and XD prefix") \
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ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_K_B,4, "requires EVEX_B, EVEX_K, L2, W and OpSize") \
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ENUM_ENTRY(IC_EVEX_KZ_B, 1, "requires EVEX_B and EVEX_KZ prefix") \
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ENUM_ENTRY(IC_EVEX_XS_KZ_B, 2, "requires EVEX_B, EVEX_KZ and the XS prefix") \
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ENUM_ENTRY(IC_EVEX_XD_KZ_B, 2, "requires EVEX_B, EVEX_KZ and the XD prefix") \
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ENUM_ENTRY(IC_EVEX_OPSIZE_KZ_B, 2, "requires EVEX_B, EVEX_KZ and the OpSize prefix") \
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ENUM_ENTRY(IC_EVEX_W_KZ_B, 3, "requires EVEX_B, EVEX_KZ and the W prefix") \
|
|
ENUM_ENTRY(IC_EVEX_W_XS_KZ_B, 4, "requires EVEX_B, EVEX_KZ, W, and XS prefix") \
|
|
ENUM_ENTRY(IC_EVEX_W_XD_KZ_B, 4, "requires EVEX_B, EVEX_KZ, W, and XD prefix") \
|
|
ENUM_ENTRY(IC_EVEX_W_OPSIZE_KZ_B, 4, "requires EVEX_B, EVEX_KZ, W, and OpSize") \
|
|
ENUM_ENTRY(IC_EVEX_L_KZ_B, 3, "requires EVEX_B, EVEX_KZ and the L prefix") \
|
|
ENUM_ENTRY(IC_EVEX_L_XS_KZ_B, 4, "requires EVEX_B, EVEX_KZ and the L and XS prefix")\
|
|
ENUM_ENTRY(IC_EVEX_L_XD_KZ_B, 4, "requires EVEX_B, EVEX_KZ and the L and XD prefix")\
|
|
ENUM_ENTRY(IC_EVEX_L_OPSIZE_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L, and OpSize") \
|
|
ENUM_ENTRY(IC_EVEX_L_W_KZ_B, 3, "requires EVEX_B, EVEX_KZ, L and W") \
|
|
ENUM_ENTRY(IC_EVEX_L_W_XS_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L, W and XS prefix") \
|
|
ENUM_ENTRY(IC_EVEX_L_W_XD_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L, W and XD prefix") \
|
|
ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L, W and OpSize") \
|
|
ENUM_ENTRY(IC_EVEX_L2_KZ_B, 3, "requires EVEX_B, EVEX_KZ and the L2 prefix") \
|
|
ENUM_ENTRY(IC_EVEX_L2_XS_KZ_B, 4, "requires EVEX_B, EVEX_KZ and the L2 and XS prefix")\
|
|
ENUM_ENTRY(IC_EVEX_L2_XD_KZ_B, 4, "requires EVEX_B, EVEX_KZ and the L2 and XD prefix")\
|
|
ENUM_ENTRY(IC_EVEX_L2_OPSIZE_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L2, and OpSize") \
|
|
ENUM_ENTRY(IC_EVEX_L2_W_KZ_B, 3, "requires EVEX_B, EVEX_KZ, L2 and W") \
|
|
ENUM_ENTRY(IC_EVEX_L2_W_XS_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L2, W and XS prefix") \
|
|
ENUM_ENTRY(IC_EVEX_L2_W_XD_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L2, W and XD prefix") \
|
|
ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L2, W and OpSize") \
|
|
ENUM_ENTRY(IC_EVEX_KZ, 1, "requires an EVEX_KZ prefix") \
|
|
ENUM_ENTRY(IC_EVEX_XS_KZ, 2, "requires EVEX_KZ and the XS prefix") \
|
|
ENUM_ENTRY(IC_EVEX_XD_KZ, 2, "requires EVEX_KZ and the XD prefix") \
|
|
ENUM_ENTRY(IC_EVEX_OPSIZE_KZ, 2, "requires EVEX_KZ and the OpSize prefix") \
|
|
ENUM_ENTRY(IC_EVEX_W_KZ, 3, "requires EVEX_KZ and the W prefix") \
|
|
ENUM_ENTRY(IC_EVEX_W_XS_KZ, 4, "requires EVEX_KZ, W, and XS prefix") \
|
|
ENUM_ENTRY(IC_EVEX_W_XD_KZ, 4, "requires EVEX_KZ, W, and XD prefix") \
|
|
ENUM_ENTRY(IC_EVEX_W_OPSIZE_KZ, 4, "requires EVEX_KZ, W, and OpSize") \
|
|
ENUM_ENTRY(IC_EVEX_L_KZ, 3, "requires EVEX_KZ and the L prefix") \
|
|
ENUM_ENTRY(IC_EVEX_L_XS_KZ, 4, "requires EVEX_KZ and the L and XS prefix")\
|
|
ENUM_ENTRY(IC_EVEX_L_XD_KZ, 4, "requires EVEX_KZ and the L and XD prefix")\
|
|
ENUM_ENTRY(IC_EVEX_L_OPSIZE_KZ, 4, "requires EVEX_KZ, L, and OpSize") \
|
|
ENUM_ENTRY(IC_EVEX_L_W_KZ, 3, "requires EVEX_KZ, L and W") \
|
|
ENUM_ENTRY(IC_EVEX_L_W_XS_KZ, 4, "requires EVEX_KZ, L, W and XS prefix") \
|
|
ENUM_ENTRY(IC_EVEX_L_W_XD_KZ, 4, "requires EVEX_KZ, L, W and XD prefix") \
|
|
ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_KZ, 4, "requires EVEX_KZ, L, W and OpSize") \
|
|
ENUM_ENTRY(IC_EVEX_L2_KZ, 3, "requires EVEX_KZ and the L2 prefix") \
|
|
ENUM_ENTRY(IC_EVEX_L2_XS_KZ, 4, "requires EVEX_KZ and the L2 and XS prefix")\
|
|
ENUM_ENTRY(IC_EVEX_L2_XD_KZ, 4, "requires EVEX_KZ and the L2 and XD prefix")\
|
|
ENUM_ENTRY(IC_EVEX_L2_OPSIZE_KZ, 4, "requires EVEX_KZ, L2, and OpSize") \
|
|
ENUM_ENTRY(IC_EVEX_L2_W_KZ, 3, "requires EVEX_KZ, L2 and W") \
|
|
ENUM_ENTRY(IC_EVEX_L2_W_XS_KZ, 4, "requires EVEX_KZ, L2, W and XS prefix") \
|
|
ENUM_ENTRY(IC_EVEX_L2_W_XD_KZ, 4, "requires EVEX_KZ, L2, W and XD prefix") \
|
|
ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_KZ, 4, "requires EVEX_KZ, L2, W and OpSize")
|
|
|
|
#define ENUM_ENTRY(n, r, d) n,
|
|
typedef enum {
|
|
INSTRUCTION_CONTEXTS
|
|
IC_max
|
|
} InstructionContext;
|
|
#undef ENUM_ENTRY
|
|
|
|
/*
|
|
* Opcode types, which determine which decode table to use, both in the Intel
|
|
* manual and also for the decoder.
|
|
*/
|
|
typedef enum {
|
|
ONEBYTE = 0,
|
|
TWOBYTE = 1,
|
|
THREEBYTE_38 = 2,
|
|
THREEBYTE_3A = 3,
|
|
XOP8_MAP = 4,
|
|
XOP9_MAP = 5,
|
|
XOPA_MAP = 6,
|
|
THREEDNOW_MAP = 7
|
|
} OpcodeType;
|
|
|
|
/*
|
|
* The following structs are used for the hierarchical decode table. After
|
|
* determining the instruction's class (i.e., which IC_* constant applies to
|
|
* it), the decoder reads the opcode. Some instructions require specific
|
|
* values of the ModR/M byte, so the ModR/M byte indexes into the final table.
|
|
*
|
|
* If a ModR/M byte is not required, "required" is left unset, and the values
|
|
* for each instructionID are identical.
|
|
*/
|
|
|
|
typedef uint16_t InstrUID;
|
|
|
|
/*
|
|
* ModRMDecisionType - describes the type of ModR/M decision, allowing the
|
|
* consumer to determine the number of entries in it.
|
|
*
|
|
* MODRM_ONEENTRY - No matter what the value of the ModR/M byte is, the decoded
|
|
* instruction is the same.
|
|
* MODRM_SPLITRM - If the ModR/M byte is between 0x00 and 0xbf, the opcode
|
|
* corresponds to one instruction; otherwise, it corresponds to
|
|
* a different instruction.
|
|
* MODRM_SPLITMISC- If the ModR/M byte is between 0x00 and 0xbf, ModR/M byte
|
|
* divided by 8 is used to select instruction; otherwise, each
|
|
* value of the ModR/M byte could correspond to a different
|
|
* instruction.
|
|
* MODRM_SPLITREG - ModR/M byte divided by 8 is used to select instruction. This
|
|
corresponds to instructions that use reg field as opcode
|
|
* MODRM_FULL - Potentially, each value of the ModR/M byte could correspond
|
|
* to a different instruction.
|
|
*/
|
|
|
|
#define MODRMTYPES \
|
|
ENUM_ENTRY(MODRM_ONEENTRY) \
|
|
ENUM_ENTRY(MODRM_SPLITRM) \
|
|
ENUM_ENTRY(MODRM_SPLITMISC) \
|
|
ENUM_ENTRY(MODRM_SPLITREG) \
|
|
ENUM_ENTRY(MODRM_FULL)
|
|
|
|
#define ENUM_ENTRY(n) n,
|
|
typedef enum {
|
|
MODRMTYPES
|
|
MODRM_max
|
|
} ModRMDecisionType;
|
|
#undef ENUM_ENTRY
|
|
|
|
#define CASE_ENCODING_RM \
|
|
case ENCODING_RM: \
|
|
case ENCODING_RM_CD2: \
|
|
case ENCODING_RM_CD4: \
|
|
case ENCODING_RM_CD8: \
|
|
case ENCODING_RM_CD16: \
|
|
case ENCODING_RM_CD32: \
|
|
case ENCODING_RM_CD64
|
|
|
|
#define CASE_ENCODING_VSIB \
|
|
case ENCODING_VSIB: \
|
|
case ENCODING_VSIB_CD2: \
|
|
case ENCODING_VSIB_CD4: \
|
|
case ENCODING_VSIB_CD8: \
|
|
case ENCODING_VSIB_CD16: \
|
|
case ENCODING_VSIB_CD32: \
|
|
case ENCODING_VSIB_CD64
|
|
|
|
// Physical encodings of instruction operands.
|
|
|
|
#define ENCODINGS \
|
|
ENUM_ENTRY(ENCODING_NONE, "") \
|
|
ENUM_ENTRY(ENCODING_REG, "Register operand in ModR/M byte.") \
|
|
ENUM_ENTRY(ENCODING_RM, "R/M operand in ModR/M byte.") \
|
|
ENUM_ENTRY(ENCODING_RM_CD2, "R/M operand with CDisp scaling of 2") \
|
|
ENUM_ENTRY(ENCODING_RM_CD4, "R/M operand with CDisp scaling of 4") \
|
|
ENUM_ENTRY(ENCODING_RM_CD8, "R/M operand with CDisp scaling of 8") \
|
|
ENUM_ENTRY(ENCODING_RM_CD16,"R/M operand with CDisp scaling of 16") \
|
|
ENUM_ENTRY(ENCODING_RM_CD32,"R/M operand with CDisp scaling of 32") \
|
|
ENUM_ENTRY(ENCODING_RM_CD64,"R/M operand with CDisp scaling of 64") \
|
|
ENUM_ENTRY(ENCODING_VSIB, "VSIB operand in ModR/M byte.") \
|
|
ENUM_ENTRY(ENCODING_VSIB_CD2, "VSIB operand with CDisp scaling of 2") \
|
|
ENUM_ENTRY(ENCODING_VSIB_CD4, "VSIB operand with CDisp scaling of 4") \
|
|
ENUM_ENTRY(ENCODING_VSIB_CD8, "VSIB operand with CDisp scaling of 8") \
|
|
ENUM_ENTRY(ENCODING_VSIB_CD16,"VSIB operand with CDisp scaling of 16") \
|
|
ENUM_ENTRY(ENCODING_VSIB_CD32,"VSIB operand with CDisp scaling of 32") \
|
|
ENUM_ENTRY(ENCODING_VSIB_CD64,"VSIB operand with CDisp scaling of 64") \
|
|
ENUM_ENTRY(ENCODING_VVVV, "Register operand in VEX.vvvv byte.") \
|
|
ENUM_ENTRY(ENCODING_WRITEMASK, "Register operand in EVEX.aaa byte.") \
|
|
ENUM_ENTRY(ENCODING_IB, "1-byte immediate") \
|
|
ENUM_ENTRY(ENCODING_IW, "2-byte") \
|
|
ENUM_ENTRY(ENCODING_ID, "4-byte") \
|
|
ENUM_ENTRY(ENCODING_IO, "8-byte") \
|
|
ENUM_ENTRY(ENCODING_RB, "(AL..DIL, R8L..R15L) Register code added to " \
|
|
"the opcode byte") \
|
|
ENUM_ENTRY(ENCODING_RW, "(AX..DI, R8W..R15W)") \
|
|
ENUM_ENTRY(ENCODING_RD, "(EAX..EDI, R8D..R15D)") \
|
|
ENUM_ENTRY(ENCODING_RO, "(RAX..RDI, R8..R15)") \
|
|
ENUM_ENTRY(ENCODING_FP, "Position on floating-point stack in ModR/M " \
|
|
"byte.") \
|
|
ENUM_ENTRY(ENCODING_Iv, "Immediate of operand size") \
|
|
ENUM_ENTRY(ENCODING_Ia, "Immediate of address size") \
|
|
ENUM_ENTRY(ENCODING_IRC, "Immediate for static rounding control") \
|
|
ENUM_ENTRY(ENCODING_Rv, "Register code of operand size added to the " \
|
|
"opcode byte") \
|
|
ENUM_ENTRY(ENCODING_DUP, "Duplicate of another operand; ID is encoded " \
|
|
"in type") \
|
|
ENUM_ENTRY(ENCODING_SI, "Source index; encoded in OpSize/Adsize prefix") \
|
|
ENUM_ENTRY(ENCODING_DI, "Destination index; encoded in prefixes")
|
|
|
|
#define ENUM_ENTRY(n, d) n,
|
|
typedef enum {
|
|
ENCODINGS
|
|
ENCODING_max
|
|
} OperandEncoding;
|
|
#undef ENUM_ENTRY
|
|
|
|
/*
|
|
* Semantic interpretations of instruction operands.
|
|
*/
|
|
#define TYPES \
|
|
ENUM_ENTRY(TYPE_NONE, "") \
|
|
ENUM_ENTRY(TYPE_REL, "immediate address") \
|
|
ENUM_ENTRY(TYPE_R8, "1-byte register operand") \
|
|
ENUM_ENTRY(TYPE_R16, "2-byte") \
|
|
ENUM_ENTRY(TYPE_R32, "4-byte") \
|
|
ENUM_ENTRY(TYPE_R64, "8-byte") \
|
|
ENUM_ENTRY(TYPE_IMM, "immediate operand") \
|
|
ENUM_ENTRY(TYPE_IMM3, "1-byte immediate operand between 0 and 7") \
|
|
ENUM_ENTRY(TYPE_IMM5, "1-byte immediate operand between 0 and 31") \
|
|
ENUM_ENTRY(TYPE_AVX512ICC, "1-byte immediate operand for AVX512 icmp") \
|
|
ENUM_ENTRY(TYPE_UIMM8, "1-byte unsigned immediate operand") \
|
|
ENUM_ENTRY(TYPE_M, "Memory operand") \
|
|
ENUM_ENTRY(TYPE_MVSIBX, "Memory operand using XMM index") \
|
|
ENUM_ENTRY(TYPE_MVSIBY, "Memory operand using YMM index") \
|
|
ENUM_ENTRY(TYPE_MVSIBZ, "Memory operand using ZMM index") \
|
|
ENUM_ENTRY(TYPE_SRCIDX, "memory at source index") \
|
|
ENUM_ENTRY(TYPE_DSTIDX, "memory at destination index") \
|
|
ENUM_ENTRY(TYPE_MOFFS, "memory offset (relative to segment base)") \
|
|
ENUM_ENTRY(TYPE_ST, "Position on the floating-point stack") \
|
|
ENUM_ENTRY(TYPE_MM64, "8-byte MMX register") \
|
|
ENUM_ENTRY(TYPE_XMM, "16-byte") \
|
|
ENUM_ENTRY(TYPE_YMM, "32-byte") \
|
|
ENUM_ENTRY(TYPE_ZMM, "64-byte") \
|
|
ENUM_ENTRY(TYPE_VK, "mask register") \
|
|
ENUM_ENTRY(TYPE_SEGMENTREG, "Segment register operand") \
|
|
ENUM_ENTRY(TYPE_DEBUGREG, "Debug register operand") \
|
|
ENUM_ENTRY(TYPE_CONTROLREG, "Control register operand") \
|
|
ENUM_ENTRY(TYPE_BNDR, "MPX bounds register") \
|
|
\
|
|
ENUM_ENTRY(TYPE_Rv, "Register operand of operand size") \
|
|
ENUM_ENTRY(TYPE_RELv, "Immediate address of operand size") \
|
|
ENUM_ENTRY(TYPE_DUP0, "Duplicate of operand 0") \
|
|
ENUM_ENTRY(TYPE_DUP1, "operand 1") \
|
|
ENUM_ENTRY(TYPE_DUP2, "operand 2") \
|
|
ENUM_ENTRY(TYPE_DUP3, "operand 3") \
|
|
ENUM_ENTRY(TYPE_DUP4, "operand 4") \
|
|
|
|
#define ENUM_ENTRY(n, d) n,
|
|
typedef enum {
|
|
TYPES
|
|
TYPE_max
|
|
} OperandType;
|
|
#undef ENUM_ENTRY
|
|
|
|
/*
|
|
* The specification for how to extract and interpret one operand.
|
|
*/
|
|
typedef struct OperandSpecifier {
|
|
uint8_t encoding;
|
|
uint8_t type;
|
|
} OperandSpecifier;
|
|
|
|
#define X86_MAX_OPERANDS 6
|
|
|
|
/*
|
|
* Decoding mode for the Intel disassembler. 16-bit, 32-bit, and 64-bit mode
|
|
* are supported, and represent real mode, IA-32e, and IA-32e in 64-bit mode,
|
|
* respectively.
|
|
*/
|
|
typedef enum {
|
|
MODE_16BIT,
|
|
MODE_32BIT,
|
|
MODE_64BIT
|
|
} DisassemblerMode;
|
|
|
|
#endif
|