Files
kaizen/external/capstone/bindings/vb6/CInstDetails.cls
T
iris 00cc9309cb Squashed 'external/ircolib/' changes from ce3cd726c..de6e324bd
de6e324bd separate emu thread
10d3daf86 Roms List improvements
95d202f37 Let's make the rom list process on a separate thread so the emulator doesnt take ages to load.
fc306967f Wow the ROM Header was just completely busted. Game list view works now
bad1691ee fuck this shit
2b59e5f46 game list in progress
d26417b83 remappable inputs in progress
ac4af8106 input
e72abc240 update readme
430139dc9 Qt6 frontend
3080d4d45 Fix this small bug too
08cd13b85 Cop0 unused functions do not actually pose a threat (as per manual). They don't do anything, so shall we.
61bb4fb44 make idle loop detection a little more specific with where the load goes
b037de4c3 SAZDFsdff
12e81e73e need to figure out why n64-systemtest loops indefinitely at some address that appears to be valid (i think it's me not invalidating the cache properly)
204f0e13b idle skipping seems to work!
cb8bb634a sdkfjlasdf
58e5c89c1 Fix compilation issue on my machine (no idea)
24fb2898e attempting more serious idle skipping
214719577 Place rsp.Step inside cached interpreter. Gains about 3 more fps
bb97dcc23 mmmmm
920b77d38 wjkhasdfjhkasdf
430ccdab4 it's a start...
4f42a673a Cached interpreter plays Mario 64. Start looking into RSP as well
c9a030787 idle skipping works!
5fbda03ce new idea
366637aba Idle skipping... maybe?
609fa2fb0 Cache instructions implemented but broken lmao. Commented out for now
e140a6d12 - Stop using inheritance for CPU, instead use composition. - Introduce KAIZEN_JIT_ENABLED optional define instead of relying on __aarch64__ and the like. - More cache work
68e613057 prep cache impl
811b4d809 fix clang format
fda755f7d idk
d5024ebbf small MI refactor in preparation of (eventually) implementing the RDRAM interface properly
694b45341 Merge commit '206dcdedf195fb320913584180edb12c7731e396' as 'external/SDL'
206dcdedf Squashed 'external/SDL/' content from commit 4d17b99d0a
4d16e1cb4 need to update sdl
848b19920 Fix compilation error
db61b5299 Merge commit 'e94a94559f28e49678fbcf72199a5258137b0fe9' as 'external/imgui'
e94a94559 Squashed 'external/imgui/' content from commit 02e9b8cac
52edb3757 need to update imgui
c1a705e86 Emulate weird JALR behaviour
4b4c32f4b Fix exception for "unusable COP1" in 4 instructions i missed accidentally (again)
df5828142 Bug putting 0s in the log everywhere
f8b580048 Make isviewer a sink to file
8241e9735 Fix exception for "unusable COP1" in 4 instructions i missed accidentally
b29715f20 small changes
d9a620bc1 make use of my new small utility library
0d1aa938e Add 'external/ircolib/' from commit 'ce3cd726c8df8388d554abf8bb55d55020eb4450'
e64eb40b3 Fuck git

git-subtree-dir: external/ircolib
git-subtree-split: de6e324bde
2026-06-15 11:56:38 +02:00

120 lines
3.7 KiB
OpenEdge ABL

VERSION 1.0 CLASS
BEGIN
MultiUse = -1 'True
Persistable = 0 'NotPersistable
DataBindingBehavior = 0 'vbNone
DataSourceBehavior = 0 'vbNone
MTSTransactionMode = 0 'NotAnMTSObject
END
Attribute VB_Name = "CInstDetails"
Attribute VB_GlobalNameSpace = False
Attribute VB_Creatable = True
Attribute VB_PredeclaredId = False
Attribute VB_Exposed = False
Option Explicit
'Capstone Disassembly Engine bindings for VB6
'Contributed by FireEye FLARE Team
'Author: David Zimmer <david.zimmer@fireeye.com>, <dzzie@yahoo.com>
'License: Apache 2.0
'Copyright: FireEye 2017
'Public Type cs_detail
' regs_read(0 To 15) As Byte ' list of implicit registers read by this insn UNSIGNED
' regs_read_count As Byte ' number of implicit registers read by this insn UNSIGNED
' regs_write(0 To 19) As Byte ' list of implicit registers modified by this insn UNSIGNED
' regs_write_count As Byte ' number of implicit registers modified by this insn UNSIGNED
' groups(0 To 7) As Byte ' list of group this instruction belong to UNSIGNED
' groups_count As Byte ' number of groups this insn belongs to UNSIGNED
'
' // Architecture-specific instruction info
' union {
' cs_x86 x86; // X86 architecture, including 16-bit, 32-bit & 64-bit mode
' cs_arm64 arm64; // ARM64 architecture (aka AArch64)
' cs_arm arm; // ARM architecture (including Thumb/Thumb2)
' cs_mips mips; // MIPS architecture
' cs_ppc ppc; // PowerPC architecture
' cs_sparc sparc; // Sparc architecture
' cs_sysz sysz; // SystemZ architecture
' cs_xcore xcore; // XCore architecture
' };
'} cs_detail;
Public regRead As New Collection
Public regWritten As New Collection
Public groups As New Collection
Public parent As CDisassembler
'this will be set to a class of the specific instruction info type by architecture..
Public info As Object
Private m_raw() As Byte
Function toString() As String
On Error Resume Next
Dim ret() As String
Dim v, tmp
push ret, "Instruction details: "
push ret, String(40, "-")
If DEBUG_DUMP Then
push ret, "Raw: "
push ret, HexDump(m_raw)
End If
push ret, "Registers Read: " & regRead.count & IIf(regRead.count > 0, " Values: " & col2Str(regRead), Empty)
push ret, "Registers Written: " & regWritten.count & IIf(regWritten.count > 0, " Values: " & col2Str(regWritten), Empty)
push ret, "Groups: " & groups.count & IIf(groups.count > 0, " Values: " & col2Str(groups), Empty)
'it is expected that each CXXInst class implements a toString() method..if not we catch the error anyway..
If Not info Is Nothing Then
push ret, info.toString()
End If
toString = Join(ret, vbCrLf)
End Function
Friend Sub LoadDetails(lpDetails As Long, parent As CDisassembler)
Dim cd As cs_detail
Dim i As Long
Dim x86 As CX86Inst
Set Me.parent = parent
'vbdef only contains up to the groups_count field..
CopyMemory ByVal VarPtr(cd), ByVal lpDetails, LenB(cd)
If DEBUG_DUMP Then
ReDim m_raw(LenB(cd))
CopyMemory ByVal VarPtr(m_raw(0)), ByVal lpDetails, LenB(cd)
End If
For i = 1 To cd.regs_read_count
regRead.Add cd.regs_read(i - 1)
Next
For i = 1 To cd.regs_write_count
regWritten.Add cd.regs_write(i - 1)
Next
For i = 1 To cd.groups_count
groups.Add cd.groups(i - 1)
Next
Const align = 5
'each arch needs its own CxxInstr class implemented here...
If parent.arch = CS_ARCH_X86 Then
Set x86 = New CX86Inst
x86.LoadDetails lpDetails + LenB(cd) + align, parent
Set info = x86
End If
End Sub