00cc9309cb
de6e324bdseparate emu thread10d3daf86Roms List improvements95d202f37Let's make the rom list process on a separate thread so the emulator doesnt take ages to load.fc306967fWow the ROM Header was just completely busted. Game list view works nowbad1691eefuck this shit2b59e5f46game list in progressd26417b83remappable inputs in progressac4af8106inpute72abc240update readme430139dc9Qt6 frontend3080d4d45Fix this small bug too08cd13b85Cop0 unused functions do not actually pose a threat (as per manual). They don't do anything, so shall we.61bb4fb44make idle loop detection a little more specific with where the load goesb037de4c3SAZDFsdff12e81e73eneed to figure out why n64-systemtest loops indefinitely at some address that appears to be valid (i think it's me not invalidating the cache properly)204f0e13bidle skipping seems to work!cb8bb634asdkfjlasdf58e5c89c1Fix compilation issue on my machine (no idea)24fb2898eattempting more serious idle skipping214719577Place rsp.Step inside cached interpreter. Gains about 3 more fpsbb97dcc23mmmmm920b77d38wjkhasdfjhkasdf430ccdab4it's a start...4f42a673aCached interpreter plays Mario 64. Start looking into RSP as wellc9a030787idle skipping works!5fbda03cenew idea366637abaIdle skipping... maybe?609fa2fb0Cache instructions implemented but broken lmao. Commented out for nowe140a6d12- Stop using inheritance for CPU, instead use composition. - Introduce KAIZEN_JIT_ENABLED optional define instead of relying on __aarch64__ and the like. - More cache work68e613057prep cache impl811b4d809fix clang formatfda755f7didkd5024ebbfsmall MI refactor in preparation of (eventually) implementing the RDRAM interface properly694b45341Merge commit '206dcdedf195fb320913584180edb12c7731e396' as 'external/SDL'206dcdedfSquashed 'external/SDL/' content from commit 4d17b99d0a4d16e1cb4need to update sdl848b19920Fix compilation errordb61b5299Merge commit 'e94a94559f28e49678fbcf72199a5258137b0fe9' as 'external/imgui'e94a94559Squashed 'external/imgui/' content from commit 02e9b8cac52edb3757need to update imguic1a705e86Emulate weird JALR behaviour4b4c32f4bFix exception for "unusable COP1" in 4 instructions i missed accidentally (again)df5828142Bug putting 0s in the log everywheref8b580048Make isviewer a sink to file8241e9735Fix exception for "unusable COP1" in 4 instructions i missed accidentallyb29715f20small changesd9a620bc1make use of my new small utility library0d1aa938eAdd 'external/ircolib/' from commit 'ce3cd726c8df8388d554abf8bb55d55020eb4450'e64eb40b3Fuck git git-subtree-dir: external/ircolib git-subtree-split:de6e324bde
120 lines
3.7 KiB
OpenEdge ABL
120 lines
3.7 KiB
OpenEdge ABL
VERSION 1.0 CLASS
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BEGIN
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MultiUse = -1 'True
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Persistable = 0 'NotPersistable
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DataBindingBehavior = 0 'vbNone
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DataSourceBehavior = 0 'vbNone
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MTSTransactionMode = 0 'NotAnMTSObject
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END
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Attribute VB_Name = "CInstDetails"
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Attribute VB_GlobalNameSpace = False
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Attribute VB_Creatable = True
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Attribute VB_PredeclaredId = False
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Attribute VB_Exposed = False
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Option Explicit
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'Capstone Disassembly Engine bindings for VB6
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'Contributed by FireEye FLARE Team
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'Author: David Zimmer <david.zimmer@fireeye.com>, <dzzie@yahoo.com>
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'License: Apache 2.0
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'Copyright: FireEye 2017
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'Public Type cs_detail
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' regs_read(0 To 15) As Byte ' list of implicit registers read by this insn UNSIGNED
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' regs_read_count As Byte ' number of implicit registers read by this insn UNSIGNED
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' regs_write(0 To 19) As Byte ' list of implicit registers modified by this insn UNSIGNED
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' regs_write_count As Byte ' number of implicit registers modified by this insn UNSIGNED
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' groups(0 To 7) As Byte ' list of group this instruction belong to UNSIGNED
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' groups_count As Byte ' number of groups this insn belongs to UNSIGNED
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'
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' // Architecture-specific instruction info
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' union {
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' cs_x86 x86; // X86 architecture, including 16-bit, 32-bit & 64-bit mode
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' cs_arm64 arm64; // ARM64 architecture (aka AArch64)
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' cs_arm arm; // ARM architecture (including Thumb/Thumb2)
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' cs_mips mips; // MIPS architecture
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' cs_ppc ppc; // PowerPC architecture
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' cs_sparc sparc; // Sparc architecture
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' cs_sysz sysz; // SystemZ architecture
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' cs_xcore xcore; // XCore architecture
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' };
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'} cs_detail;
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Public regRead As New Collection
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Public regWritten As New Collection
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Public groups As New Collection
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Public parent As CDisassembler
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'this will be set to a class of the specific instruction info type by architecture..
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Public info As Object
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Private m_raw() As Byte
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Function toString() As String
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On Error Resume Next
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Dim ret() As String
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Dim v, tmp
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push ret, "Instruction details: "
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push ret, String(40, "-")
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If DEBUG_DUMP Then
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push ret, "Raw: "
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push ret, HexDump(m_raw)
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End If
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push ret, "Registers Read: " & regRead.count & IIf(regRead.count > 0, " Values: " & col2Str(regRead), Empty)
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push ret, "Registers Written: " & regWritten.count & IIf(regWritten.count > 0, " Values: " & col2Str(regWritten), Empty)
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push ret, "Groups: " & groups.count & IIf(groups.count > 0, " Values: " & col2Str(groups), Empty)
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'it is expected that each CXXInst class implements a toString() method..if not we catch the error anyway..
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If Not info Is Nothing Then
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push ret, info.toString()
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End If
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toString = Join(ret, vbCrLf)
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End Function
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Friend Sub LoadDetails(lpDetails As Long, parent As CDisassembler)
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Dim cd As cs_detail
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Dim i As Long
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Dim x86 As CX86Inst
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Set Me.parent = parent
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'vbdef only contains up to the groups_count field..
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CopyMemory ByVal VarPtr(cd), ByVal lpDetails, LenB(cd)
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If DEBUG_DUMP Then
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ReDim m_raw(LenB(cd))
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CopyMemory ByVal VarPtr(m_raw(0)), ByVal lpDetails, LenB(cd)
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End If
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For i = 1 To cd.regs_read_count
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regRead.Add cd.regs_read(i - 1)
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Next
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For i = 1 To cd.regs_write_count
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regWritten.Add cd.regs_write(i - 1)
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Next
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For i = 1 To cd.groups_count
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groups.Add cd.groups(i - 1)
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Next
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Const align = 5
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'each arch needs its own CxxInstr class implemented here...
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If parent.arch = CS_ARCH_X86 Then
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Set x86 = New CX86Inst
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x86.LoadDetails lpDetails + LenB(cd) + align, parent
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Set info = x86
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End If
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End Sub
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