Files
kaizen/external/capstone/cs_priv.h
T
iris 00cc9309cb Squashed 'external/ircolib/' changes from ce3cd726c..de6e324bd
de6e324bd separate emu thread
10d3daf86 Roms List improvements
95d202f37 Let's make the rom list process on a separate thread so the emulator doesnt take ages to load.
fc306967f Wow the ROM Header was just completely busted. Game list view works now
bad1691ee fuck this shit
2b59e5f46 game list in progress
d26417b83 remappable inputs in progress
ac4af8106 input
e72abc240 update readme
430139dc9 Qt6 frontend
3080d4d45 Fix this small bug too
08cd13b85 Cop0 unused functions do not actually pose a threat (as per manual). They don't do anything, so shall we.
61bb4fb44 make idle loop detection a little more specific with where the load goes
b037de4c3 SAZDFsdff
12e81e73e need to figure out why n64-systemtest loops indefinitely at some address that appears to be valid (i think it's me not invalidating the cache properly)
204f0e13b idle skipping seems to work!
cb8bb634a sdkfjlasdf
58e5c89c1 Fix compilation issue on my machine (no idea)
24fb2898e attempting more serious idle skipping
214719577 Place rsp.Step inside cached interpreter. Gains about 3 more fps
bb97dcc23 mmmmm
920b77d38 wjkhasdfjhkasdf
430ccdab4 it's a start...
4f42a673a Cached interpreter plays Mario 64. Start looking into RSP as well
c9a030787 idle skipping works!
5fbda03ce new idea
366637aba Idle skipping... maybe?
609fa2fb0 Cache instructions implemented but broken lmao. Commented out for now
e140a6d12 - Stop using inheritance for CPU, instead use composition. - Introduce KAIZEN_JIT_ENABLED optional define instead of relying on __aarch64__ and the like. - More cache work
68e613057 prep cache impl
811b4d809 fix clang format
fda755f7d idk
d5024ebbf small MI refactor in preparation of (eventually) implementing the RDRAM interface properly
694b45341 Merge commit '206dcdedf195fb320913584180edb12c7731e396' as 'external/SDL'
206dcdedf Squashed 'external/SDL/' content from commit 4d17b99d0a
4d16e1cb4 need to update sdl
848b19920 Fix compilation error
db61b5299 Merge commit 'e94a94559f28e49678fbcf72199a5258137b0fe9' as 'external/imgui'
e94a94559 Squashed 'external/imgui/' content from commit 02e9b8cac
52edb3757 need to update imgui
c1a705e86 Emulate weird JALR behaviour
4b4c32f4b Fix exception for "unusable COP1" in 4 instructions i missed accidentally (again)
df5828142 Bug putting 0s in the log everywhere
f8b580048 Make isviewer a sink to file
8241e9735 Fix exception for "unusable COP1" in 4 instructions i missed accidentally
b29715f20 small changes
d9a620bc1 make use of my new small utility library
0d1aa938e Add 'external/ircolib/' from commit 'ce3cd726c8df8388d554abf8bb55d55020eb4450'
e64eb40b3 Fuck git

git-subtree-dir: external/ircolib
git-subtree-split: de6e324bde
2026-06-15 11:56:38 +02:00

153 lines
4.6 KiB
C

/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
#ifndef CS_PRIV_H
#define CS_PRIV_H
#ifdef CAPSTONE_DEBUG
#include <assert.h>
#endif
#include <capstone/capstone.h>
#include "MCInst.h"
#include "SStream.h"
typedef void (*Printer_t)(MCInst *MI, SStream *OS, void *info);
// function to be called after Printer_t
// this is the best time to gather insn's characteristics
typedef void (*PostPrinter_t)(csh handle, cs_insn *, SStream *mnem, MCInst *mci);
typedef bool (*Disasm_t)(csh handle, const uint8_t *code, size_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info);
typedef const char *(*GetName_t)(csh handle, unsigned int id);
typedef void (*GetID_t)(cs_struct *h, cs_insn *insn, unsigned int id);
// return registers accessed by instruction
typedef void (*GetRegisterAccess_t)(const cs_insn *insn,
cs_regs regs_read, uint8_t *regs_read_count,
cs_regs regs_write, uint8_t *regs_write_count);
// for ARM only
typedef struct ARM_ITBlock {
unsigned char ITStates[8];
unsigned int size;
} ARM_ITBlock;
typedef struct ARM_VPTBlock {
unsigned char VPTStates[8];
unsigned int size;
} ARM_VPTBlock;
// Customize mnemonic for instructions with alternative name.
struct customized_mnem {
// ID of instruction to be customized.
unsigned int id;
// Customized instruction mnemonic.
char mnemonic[CS_MNEMONIC_SIZE];
};
struct insn_mnem {
struct customized_mnem insn;
struct insn_mnem *next; // linked list of customized mnemonics
};
struct cs_struct {
cs_arch arch;
cs_mode mode;
Printer_t printer; // asm printer
void *printer_info; // aux info for printer
Disasm_t disasm; // disassembler
void *getinsn_info; // auxiliary info for printer
GetName_t reg_name;
GetName_t insn_name;
GetName_t group_name;
GetID_t insn_id;
PostPrinter_t post_printer;
cs_err errnum;
ARM_ITBlock ITBlock; // for Arm only
ARM_VPTBlock VPTBlock; // for ARM only
bool PrintBranchImmAsAddress;
bool ShowVSRNumsAsVR;
cs_opt_value detail_opt, imm_unsigned;
int syntax; // asm syntax for simple printer such as ARM, Mips & PPC
bool doing_mem; // handling memory operand in InstPrinter code
bool doing_SME_Index; // handling a SME instruction that has index
unsigned short *insn_cache; // index caching for mapping.c
bool skipdata; // set this to True if we skip data when disassembling
uint8_t skipdata_size; // how many bytes to skip
cs_opt_skipdata skipdata_setup; // user-defined skipdata setup
const uint8_t *regsize_map; // map to register size (x86-only for now)
GetRegisterAccess_t reg_access;
struct insn_mnem *mnem_list; // linked list of customized instruction mnemonic
uint32_t LITBASE; ///< The LITBASE register content. Bit 0 (LSB) indicatess if it is set. Bit[23:8] are the literal base address.
};
#define MAX_ARCH CS_ARCH_MAX
// Returns a bool (0 or 1) whether big endian is enabled for a mode
#define MODE_IS_BIG_ENDIAN(mode) (((mode) & CS_MODE_BIG_ENDIAN) != 0)
/// Returns true of the 16bit flag is set.
#define IS_16BIT(mode) ((mode & CS_MODE_16) != 0)
/// Returns true of the 32bit flag is set.
#define IS_32BIT(mode) ((mode & CS_MODE_32) != 0)
/// Returns true of the 64bit flag is set.
#define IS_64BIT(mode) ((mode & CS_MODE_64) != 0)
extern cs_malloc_t cs_mem_malloc;
extern cs_calloc_t cs_mem_calloc;
extern cs_realloc_t cs_mem_realloc;
extern cs_free_t cs_mem_free;
extern cs_vsnprintf_t cs_vsnprintf;
/// By defining CAPSTONE_DEBUG assertions can be used.
/// For the release build the @expr is not included.
#ifdef CAPSTONE_DEBUG
#define CS_ASSERT(expr) assert(expr)
#elif CAPSTONE_ASSERTION_WARNINGS
#define CS_ASSERT(expr) \
do { \
if (!(expr)) { \
fprintf(stderr, "Capstone hit the assert: \"" #expr "\": %s:%" PRIu32 "\n", __FILE__, __LINE__); \
} \
} while(0)
#else
#define CS_ASSERT(expr)
#endif
/// If compiled in debug mode it will assert(@expr).
/// In the release build it will check the @expr and return @val if false.
#ifdef CAPSTONE_DEBUG
#define CS_ASSERT_RET_VAL(expr, val) assert(expr)
#elif CAPSTONE_ASSERTION_WARNINGS
#define CS_ASSERT_RET_VAL(expr, val) \
do { \
if (!(expr)) { \
fprintf(stderr, "Capstone hit the assert: \"" #expr "\": %s:%" PRIu32 "\n", __FILE__, __LINE__); \
return val; \
} \
} while(0)
#else
#define CS_ASSERT_RET_VAL(expr, val)
#endif
/// If compiled in debug mode it will assert(@expr).
/// In the release build it will check the @expr and return if false.
#ifdef CAPSTONE_DEBUG
#define CS_ASSERT_RET(expr) assert(expr)
#elif CAPSTONE_ASSERTION_WARNINGS
#define CS_ASSERT_RET(expr) \
do { \
if (!(expr)) { \
fprintf(stderr, "Capstone hit the assert: \"" #expr "\": %s:%" PRIu32 "\n", __FILE__, __LINE__); \
return; \
} \
} while(0)
#else
#define CS_ASSERT_RET(expr)
#endif
#endif