00cc9309cb
de6e324bdseparate emu thread10d3daf86Roms List improvements95d202f37Let's make the rom list process on a separate thread so the emulator doesnt take ages to load.fc306967fWow the ROM Header was just completely busted. Game list view works nowbad1691eefuck this shit2b59e5f46game list in progressd26417b83remappable inputs in progressac4af8106inpute72abc240update readme430139dc9Qt6 frontend3080d4d45Fix this small bug too08cd13b85Cop0 unused functions do not actually pose a threat (as per manual). They don't do anything, so shall we.61bb4fb44make idle loop detection a little more specific with where the load goesb037de4c3SAZDFsdff12e81e73eneed to figure out why n64-systemtest loops indefinitely at some address that appears to be valid (i think it's me not invalidating the cache properly)204f0e13bidle skipping seems to work!cb8bb634asdkfjlasdf58e5c89c1Fix compilation issue on my machine (no idea)24fb2898eattempting more serious idle skipping214719577Place rsp.Step inside cached interpreter. Gains about 3 more fpsbb97dcc23mmmmm920b77d38wjkhasdfjhkasdf430ccdab4it's a start...4f42a673aCached interpreter plays Mario 64. Start looking into RSP as wellc9a030787idle skipping works!5fbda03cenew idea366637abaIdle skipping... maybe?609fa2fb0Cache instructions implemented but broken lmao. Commented out for nowe140a6d12- Stop using inheritance for CPU, instead use composition. - Introduce KAIZEN_JIT_ENABLED optional define instead of relying on __aarch64__ and the like. - More cache work68e613057prep cache impl811b4d809fix clang formatfda755f7didkd5024ebbfsmall MI refactor in preparation of (eventually) implementing the RDRAM interface properly694b45341Merge commit '206dcdedf195fb320913584180edb12c7731e396' as 'external/SDL'206dcdedfSquashed 'external/SDL/' content from commit 4d17b99d0a4d16e1cb4need to update sdl848b19920Fix compilation errordb61b5299Merge commit 'e94a94559f28e49678fbcf72199a5258137b0fe9' as 'external/imgui'e94a94559Squashed 'external/imgui/' content from commit 02e9b8cac52edb3757need to update imguic1a705e86Emulate weird JALR behaviour4b4c32f4bFix exception for "unusable COP1" in 4 instructions i missed accidentally (again)df5828142Bug putting 0s in the log everywheref8b580048Make isviewer a sink to file8241e9735Fix exception for "unusable COP1" in 4 instructions i missed accidentallyb29715f20small changesd9a620bc1make use of my new small utility library0d1aa938eAdd 'external/ircolib/' from commit 'ce3cd726c8df8388d554abf8bb55d55020eb4450'e64eb40b3Fuck git git-subtree-dir: external/ircolib git-subtree-split:de6e324bde
153 lines
4.6 KiB
C
153 lines
4.6 KiB
C
/* Capstone Disassembly Engine */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
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#ifndef CS_PRIV_H
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#define CS_PRIV_H
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#ifdef CAPSTONE_DEBUG
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#include <assert.h>
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#endif
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#include <capstone/capstone.h>
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#include "MCInst.h"
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#include "SStream.h"
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typedef void (*Printer_t)(MCInst *MI, SStream *OS, void *info);
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// function to be called after Printer_t
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// this is the best time to gather insn's characteristics
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typedef void (*PostPrinter_t)(csh handle, cs_insn *, SStream *mnem, MCInst *mci);
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typedef bool (*Disasm_t)(csh handle, const uint8_t *code, size_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info);
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typedef const char *(*GetName_t)(csh handle, unsigned int id);
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typedef void (*GetID_t)(cs_struct *h, cs_insn *insn, unsigned int id);
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// return registers accessed by instruction
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typedef void (*GetRegisterAccess_t)(const cs_insn *insn,
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cs_regs regs_read, uint8_t *regs_read_count,
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cs_regs regs_write, uint8_t *regs_write_count);
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// for ARM only
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typedef struct ARM_ITBlock {
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unsigned char ITStates[8];
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unsigned int size;
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} ARM_ITBlock;
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typedef struct ARM_VPTBlock {
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unsigned char VPTStates[8];
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unsigned int size;
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} ARM_VPTBlock;
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// Customize mnemonic for instructions with alternative name.
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struct customized_mnem {
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// ID of instruction to be customized.
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unsigned int id;
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// Customized instruction mnemonic.
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char mnemonic[CS_MNEMONIC_SIZE];
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};
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struct insn_mnem {
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struct customized_mnem insn;
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struct insn_mnem *next; // linked list of customized mnemonics
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};
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struct cs_struct {
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cs_arch arch;
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cs_mode mode;
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Printer_t printer; // asm printer
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void *printer_info; // aux info for printer
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Disasm_t disasm; // disassembler
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void *getinsn_info; // auxiliary info for printer
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GetName_t reg_name;
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GetName_t insn_name;
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GetName_t group_name;
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GetID_t insn_id;
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PostPrinter_t post_printer;
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cs_err errnum;
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ARM_ITBlock ITBlock; // for Arm only
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ARM_VPTBlock VPTBlock; // for ARM only
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bool PrintBranchImmAsAddress;
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bool ShowVSRNumsAsVR;
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cs_opt_value detail_opt, imm_unsigned;
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int syntax; // asm syntax for simple printer such as ARM, Mips & PPC
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bool doing_mem; // handling memory operand in InstPrinter code
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bool doing_SME_Index; // handling a SME instruction that has index
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unsigned short *insn_cache; // index caching for mapping.c
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bool skipdata; // set this to True if we skip data when disassembling
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uint8_t skipdata_size; // how many bytes to skip
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cs_opt_skipdata skipdata_setup; // user-defined skipdata setup
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const uint8_t *regsize_map; // map to register size (x86-only for now)
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GetRegisterAccess_t reg_access;
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struct insn_mnem *mnem_list; // linked list of customized instruction mnemonic
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uint32_t LITBASE; ///< The LITBASE register content. Bit 0 (LSB) indicatess if it is set. Bit[23:8] are the literal base address.
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};
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#define MAX_ARCH CS_ARCH_MAX
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// Returns a bool (0 or 1) whether big endian is enabled for a mode
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#define MODE_IS_BIG_ENDIAN(mode) (((mode) & CS_MODE_BIG_ENDIAN) != 0)
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/// Returns true of the 16bit flag is set.
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#define IS_16BIT(mode) ((mode & CS_MODE_16) != 0)
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/// Returns true of the 32bit flag is set.
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#define IS_32BIT(mode) ((mode & CS_MODE_32) != 0)
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/// Returns true of the 64bit flag is set.
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#define IS_64BIT(mode) ((mode & CS_MODE_64) != 0)
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extern cs_malloc_t cs_mem_malloc;
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extern cs_calloc_t cs_mem_calloc;
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extern cs_realloc_t cs_mem_realloc;
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extern cs_free_t cs_mem_free;
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extern cs_vsnprintf_t cs_vsnprintf;
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/// By defining CAPSTONE_DEBUG assertions can be used.
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/// For the release build the @expr is not included.
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#ifdef CAPSTONE_DEBUG
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#define CS_ASSERT(expr) assert(expr)
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#elif CAPSTONE_ASSERTION_WARNINGS
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#define CS_ASSERT(expr) \
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do { \
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if (!(expr)) { \
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fprintf(stderr, "Capstone hit the assert: \"" #expr "\": %s:%" PRIu32 "\n", __FILE__, __LINE__); \
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} \
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} while(0)
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#else
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#define CS_ASSERT(expr)
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#endif
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/// If compiled in debug mode it will assert(@expr).
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/// In the release build it will check the @expr and return @val if false.
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#ifdef CAPSTONE_DEBUG
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#define CS_ASSERT_RET_VAL(expr, val) assert(expr)
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#elif CAPSTONE_ASSERTION_WARNINGS
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#define CS_ASSERT_RET_VAL(expr, val) \
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do { \
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if (!(expr)) { \
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fprintf(stderr, "Capstone hit the assert: \"" #expr "\": %s:%" PRIu32 "\n", __FILE__, __LINE__); \
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return val; \
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} \
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} while(0)
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#else
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#define CS_ASSERT_RET_VAL(expr, val)
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#endif
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/// If compiled in debug mode it will assert(@expr).
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/// In the release build it will check the @expr and return if false.
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#ifdef CAPSTONE_DEBUG
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#define CS_ASSERT_RET(expr) assert(expr)
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#elif CAPSTONE_ASSERTION_WARNINGS
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#define CS_ASSERT_RET(expr) \
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do { \
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if (!(expr)) { \
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fprintf(stderr, "Capstone hit the assert: \"" #expr "\": %s:%" PRIu32 "\n", __FILE__, __LINE__); \
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return; \
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} \
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} while(0)
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#else
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#define CS_ASSERT_RET(expr)
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#endif
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#endif
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