Files
kaizen/external/capstone/cstool/cstool_powerpc.c
T
iris 00cc9309cb Squashed 'external/ircolib/' changes from ce3cd726c..de6e324bd
de6e324bd separate emu thread
10d3daf86 Roms List improvements
95d202f37 Let's make the rom list process on a separate thread so the emulator doesnt take ages to load.
fc306967f Wow the ROM Header was just completely busted. Game list view works now
bad1691ee fuck this shit
2b59e5f46 game list in progress
d26417b83 remappable inputs in progress
ac4af8106 input
e72abc240 update readme
430139dc9 Qt6 frontend
3080d4d45 Fix this small bug too
08cd13b85 Cop0 unused functions do not actually pose a threat (as per manual). They don't do anything, so shall we.
61bb4fb44 make idle loop detection a little more specific with where the load goes
b037de4c3 SAZDFsdff
12e81e73e need to figure out why n64-systemtest loops indefinitely at some address that appears to be valid (i think it's me not invalidating the cache properly)
204f0e13b idle skipping seems to work!
cb8bb634a sdkfjlasdf
58e5c89c1 Fix compilation issue on my machine (no idea)
24fb2898e attempting more serious idle skipping
214719577 Place rsp.Step inside cached interpreter. Gains about 3 more fps
bb97dcc23 mmmmm
920b77d38 wjkhasdfjhkasdf
430ccdab4 it's a start...
4f42a673a Cached interpreter plays Mario 64. Start looking into RSP as well
c9a030787 idle skipping works!
5fbda03ce new idea
366637aba Idle skipping... maybe?
609fa2fb0 Cache instructions implemented but broken lmao. Commented out for now
e140a6d12 - Stop using inheritance for CPU, instead use composition. - Introduce KAIZEN_JIT_ENABLED optional define instead of relying on __aarch64__ and the like. - More cache work
68e613057 prep cache impl
811b4d809 fix clang format
fda755f7d idk
d5024ebbf small MI refactor in preparation of (eventually) implementing the RDRAM interface properly
694b45341 Merge commit '206dcdedf195fb320913584180edb12c7731e396' as 'external/SDL'
206dcdedf Squashed 'external/SDL/' content from commit 4d17b99d0a
4d16e1cb4 need to update sdl
848b19920 Fix compilation error
db61b5299 Merge commit 'e94a94559f28e49678fbcf72199a5258137b0fe9' as 'external/imgui'
e94a94559 Squashed 'external/imgui/' content from commit 02e9b8cac
52edb3757 need to update imgui
c1a705e86 Emulate weird JALR behaviour
4b4c32f4b Fix exception for "unusable COP1" in 4 instructions i missed accidentally (again)
df5828142 Bug putting 0s in the log everywhere
f8b580048 Make isviewer a sink to file
8241e9735 Fix exception for "unusable COP1" in 4 instructions i missed accidentally
b29715f20 small changes
d9a620bc1 make use of my new small utility library
0d1aa938e Add 'external/ircolib/' from commit 'ce3cd726c8df8388d554abf8bb55d55020eb4450'
e64eb40b3 Fuck git

git-subtree-dir: external/ircolib
git-subtree-split: de6e324bde
2026-06-15 11:56:38 +02:00

200 lines
5.0 KiB
C

/* Capstone Disassembler Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
#include <stdio.h>
#include <capstone/capstone.h>
#include "capstone/ppc.h"
#include "cstool.h"
static const char* get_pred_name(ppc_pred pred)
{
switch(pred) {
default:
return ("invalid");
case PPC_PRED_LT:
case PPC_PRED_LT_MINUS:
case PPC_PRED_LT_PLUS:
case PPC_PRED_LT_RESERVED:
return ("lt");
case PPC_PRED_LE:
case PPC_PRED_LE_MINUS:
case PPC_PRED_LE_PLUS:
case PPC_PRED_LE_RESERVED:
return ("le");
case PPC_PRED_EQ:
case PPC_PRED_EQ_MINUS:
case PPC_PRED_EQ_PLUS:
case PPC_PRED_EQ_RESERVED:
return ("eq");
case PPC_PRED_GE:
case PPC_PRED_GE_MINUS:
case PPC_PRED_GE_PLUS:
case PPC_PRED_GE_RESERVED:
return ("ge");
case PPC_PRED_GT:
case PPC_PRED_GT_MINUS:
case PPC_PRED_GT_PLUS:
case PPC_PRED_GT_RESERVED:
return ("gt");
case PPC_PRED_NE:
case PPC_PRED_NE_MINUS:
case PPC_PRED_NE_PLUS:
case PPC_PRED_NE_RESERVED:
return ("ne");
case PPC_PRED_UN: // PPC_PRED_SO
case PPC_PRED_UN_MINUS:
case PPC_PRED_UN_PLUS:
case PPC_PRED_UN_RESERVED:
return ("so/un");
case PPC_PRED_NU: // PPC_PRED_NS
case PPC_PRED_NU_MINUS:
case PPC_PRED_NU_PLUS:
case PPC_PRED_NU_RESERVED:
return ("ns/nu");
case PPC_PRED_NZ:
case PPC_PRED_NZ_MINUS:
case PPC_PRED_NZ_PLUS:
case PPC_PRED_NZ_RESERVED:
return ("nz");
case PPC_PRED_Z:
case PPC_PRED_Z_MINUS:
case PPC_PRED_Z_PLUS:
case PPC_PRED_Z_RESERVED:
return ("z");
case PPC_PRED_BIT_SET:
return "bit-set";
case PPC_PRED_BIT_UNSET:
return "bit-unset";
}
}
static const char *get_pred_hint(ppc_br_hint at) {
switch (at) {
default:
return "invalid";
case PPC_BR_NOT_GIVEN:
return "not-given";
case PPC_BR_TAKEN:
return "likely-taken";
case PPC_BR_NOT_TAKEN:
return "likely-not-taken";
case PPC_BR_RESERVED:
return "reserved";
}
}
void print_insn_detail_ppc(csh handle, cs_insn *ins)
{
cs_ppc *ppc;
int i;
// detail can be NULL on "data" instruction if SKIPDATA option is turned ON
if (ins->detail == NULL)
return;
ppc = &(ins->detail->ppc);
if (ppc->op_count)
printf("\top_count: %u\n", ppc->op_count);
for (i = 0; i < ppc->op_count; i++) {
cs_ppc_op *op = &(ppc->operands[i]);
switch((int)op->type) {
default:
break;
case PPC_OP_REG:
printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg));
break;
case PPC_OP_IMM:
printf("\t\toperands[%u].type: IMM = 0x%"PRIx64"\n", i, op->imm);
break;
case PPC_OP_MEM:
printf("\t\toperands[%u].type: MEM\n", i);
if (op->mem.base != PPC_REG_INVALID)
printf("\t\t\toperands[%u].mem.base: REG = %s\n",
i, cs_reg_name(handle, op->mem.base));
if (op->mem.offset != PPC_REG_INVALID)
printf("\t\t\toperands[%u].mem.offset: REG = %s\n", i,
cs_reg_name(handle, op->mem.offset));
if (op->mem.disp != 0)
printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i, op->mem.disp);
break;
}
switch(op->access) {
default:
break;
case CS_AC_READ:
printf("\t\toperands[%u].access: READ\n", i);
break;
case CS_AC_WRITE:
printf("\t\toperands[%u].access: WRITE\n", i);
break;
case CS_AC_READ_WRITE:
printf("\t\toperands[%u].access: READ | WRITE\n", i);
break;
}
}
if (ppc->bc.pred_cr != PPC_PRED_INVALID ||
ppc->bc.pred_ctr != PPC_PRED_INVALID) {
printf("\tBranch:\n");
printf("\t\tbi: %u\n", ppc->bc.bi);
printf("\t\tbo: %u\n", ppc->bc.bo);
if (ppc->bc.bh != PPC_BH_INVALID) {
char const* msg = NULL;
switch(ppc->bc.bh) {
case PPC_BH_SUBROUTINE_RET:
msg = "subroutine return";
break;
case PPC_BH_NO_SUBROUTINE_RET:
msg = "not a subroutine return";
break;
case PPC_BH_NOT_PREDICTABLE:
msg = "unpredictable";
break;
case PPC_BH_RESERVED:
msg = "reserved";
break;
case PPC_BH_INVALID: break;
}
printf("\t\tbh: %s\n", msg);
}
if (ppc->bc.pred_cr != PPC_PRED_INVALID) {
printf("\t\tcrX: %s\n", cs_reg_name(handle, ppc->bc.crX));
printf("\t\tpred CR-bit: %s\n", get_pred_name(ppc->bc.pred_cr));
}
if (ppc->bc.pred_ctr != PPC_PRED_INVALID)
printf("\t\tpred CTR: %s\n", get_pred_name(ppc->bc.pred_ctr));
if (ppc->bc.hint != PPC_BR_NOT_GIVEN)
printf("\t\thint: %s\n", get_pred_hint(ppc->bc.hint));
}
if (ppc->bc.hint != PPC_BR_NOT_GIVEN)
printf("\tBranch hint (at bits): %u\n", ppc->bc.hint);
if (ppc->update_cr0)
printf("\tUpdate-CR0: True\n");
uint16_t *regs_read = ins->detail->regs_read;
uint16_t *regs_write = ins->detail->regs_write;
uint8_t regs_read_count = ins->detail->regs_read_count;
uint8_t regs_write_count = ins->detail->regs_write_count;
// Print out all registers accessed by this instruction (either implicit or explicit)
if (regs_read_count) {
printf("\tImplicit registers read:");
for(i = 0; i < regs_read_count; i++) {
printf(" %s", cs_reg_name(handle, regs_read[i]));
}
printf("\n");
}
if (regs_write_count) {
printf("\tImplicit registers modified:");
for(i = 0; i < regs_write_count; i++) {
printf(" %s", cs_reg_name(handle, regs_write[i]));
}
printf("\n");
}
}