iris
00cc9309cb
de6e324bdseparate emu thread10d3daf86Roms List improvements95d202f37Let's make the rom list process on a separate thread so the emulator doesnt take ages to load.fc306967fWow the ROM Header was just completely busted. Game list view works nowbad1691eefuck this shit2b59e5f46game list in progressd26417b83remappable inputs in progressac4af8106inpute72abc240update readme430139dc9Qt6 frontend3080d4d45Fix this small bug too08cd13b85Cop0 unused functions do not actually pose a threat (as per manual). They don't do anything, so shall we.61bb4fb44make idle loop detection a little more specific with where the load goesb037de4c3SAZDFsdff12e81e73eneed to figure out why n64-systemtest loops indefinitely at some address that appears to be valid (i think it's me not invalidating the cache properly)204f0e13bidle skipping seems to work!cb8bb634asdkfjlasdf58e5c89c1Fix compilation issue on my machine (no idea)24fb2898eattempting more serious idle skipping214719577Place rsp.Step inside cached interpreter. Gains about 3 more fpsbb97dcc23mmmmm920b77d38wjkhasdfjhkasdf430ccdab4it's a start...4f42a673aCached interpreter plays Mario 64. Start looking into RSP as wellc9a030787idle skipping works!5fbda03cenew idea366637abaIdle skipping... maybe?609fa2fb0Cache instructions implemented but broken lmao. Commented out for nowe140a6d12- Stop using inheritance for CPU, instead use composition. - Introduce KAIZEN_JIT_ENABLED optional define instead of relying on __aarch64__ and the like. - More cache work68e613057prep cache impl811b4d809fix clang formatfda755f7didkd5024ebbfsmall MI refactor in preparation of (eventually) implementing the RDRAM interface properly694b45341Merge commit '206dcdedf195fb320913584180edb12c7731e396' as 'external/SDL'206dcdedfSquashed 'external/SDL/' content from commit 4d17b99d0a4d16e1cb4need to update sdl848b19920Fix compilation errordb61b5299Merge commit 'e94a94559f28e49678fbcf72199a5258137b0fe9' as 'external/imgui'e94a94559Squashed 'external/imgui/' content from commit 02e9b8cac52edb3757need to update imguic1a705e86Emulate weird JALR behaviour4b4c32f4bFix exception for "unusable COP1" in 4 instructions i missed accidentally (again)df5828142Bug putting 0s in the log everywheref8b580048Make isviewer a sink to file8241e9735Fix exception for "unusable COP1" in 4 instructions i missed accidentallyb29715f20small changesd9a620bc1make use of my new small utility library0d1aa938eAdd 'external/ircolib/' from commit 'ce3cd726c8df8388d554abf8bb55d55020eb4450'e64eb40b3Fuck git git-subtree-dir: external/ircolib git-subtree-split:de6e324bde
524 lines
13 KiB
C
524 lines
13 KiB
C
/* CpuArch.h -- CPU specific code
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2023-04-02 : Igor Pavlov : Public domain */
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#ifndef ZIP7_INC_CPU_ARCH_H
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#define ZIP7_INC_CPU_ARCH_H
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#include "7zTypes.h"
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EXTERN_C_BEGIN
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/*
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MY_CPU_LE means that CPU is LITTLE ENDIAN.
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MY_CPU_BE means that CPU is BIG ENDIAN.
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If MY_CPU_LE and MY_CPU_BE are not defined, we don't know about ENDIANNESS of platform.
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MY_CPU_LE_UNALIGN means that CPU is LITTLE ENDIAN and CPU supports unaligned memory accesses.
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MY_CPU_64BIT means that processor can work with 64-bit registers.
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MY_CPU_64BIT can be used to select fast code branch
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MY_CPU_64BIT doesn't mean that (sizeof(void *) == 8)
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*/
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#if defined(_M_X64) \
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|| defined(_M_AMD64) \
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|| defined(__x86_64__) \
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|| defined(__AMD64__) \
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|| defined(__amd64__)
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#define MY_CPU_AMD64
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#ifdef __ILP32__
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#define MY_CPU_NAME "x32"
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#define MY_CPU_SIZEOF_POINTER 4
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#else
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#define MY_CPU_NAME "x64"
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#define MY_CPU_SIZEOF_POINTER 8
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#endif
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#define MY_CPU_64BIT
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#endif
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#if defined(_M_IX86) \
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|| defined(__i386__)
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#define MY_CPU_X86
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#define MY_CPU_NAME "x86"
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/* #define MY_CPU_32BIT */
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#define MY_CPU_SIZEOF_POINTER 4
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#endif
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#if defined(_M_ARM64) \
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|| defined(__AARCH64EL__) \
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|| defined(__AARCH64EB__) \
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|| defined(__aarch64__)
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#define MY_CPU_ARM64
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#ifdef __ILP32__
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#define MY_CPU_NAME "arm64-32"
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#define MY_CPU_SIZEOF_POINTER 4
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#else
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#define MY_CPU_NAME "arm64"
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#define MY_CPU_SIZEOF_POINTER 8
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#endif
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#define MY_CPU_64BIT
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#endif
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#if defined(_M_ARM) \
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|| defined(_M_ARM_NT) \
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|| defined(_M_ARMT) \
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|| defined(__arm__) \
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|| defined(__thumb__) \
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|| defined(__ARMEL__) \
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|| defined(__ARMEB__) \
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|| defined(__THUMBEL__) \
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|| defined(__THUMBEB__)
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#define MY_CPU_ARM
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#if defined(__thumb__) || defined(__THUMBEL__) || defined(_M_ARMT)
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#define MY_CPU_ARMT
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#define MY_CPU_NAME "armt"
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#else
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#define MY_CPU_ARM32
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#define MY_CPU_NAME "arm"
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#endif
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/* #define MY_CPU_32BIT */
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#define MY_CPU_SIZEOF_POINTER 4
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#endif
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#if defined(_M_IA64) \
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|| defined(__ia64__)
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#define MY_CPU_IA64
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#define MY_CPU_NAME "ia64"
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#define MY_CPU_64BIT
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#endif
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#if defined(__mips64) \
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|| defined(__mips64__) \
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|| (defined(__mips) && (__mips == 64 || __mips == 4 || __mips == 3))
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#define MY_CPU_NAME "mips64"
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#define MY_CPU_64BIT
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#elif defined(__mips__)
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#define MY_CPU_NAME "mips"
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/* #define MY_CPU_32BIT */
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#endif
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#if defined(__ppc64__) \
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|| defined(__powerpc64__) \
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|| defined(__ppc__) \
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|| defined(__powerpc__) \
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|| defined(__PPC__) \
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|| defined(_POWER)
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#define MY_CPU_PPC_OR_PPC64
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#if defined(__ppc64__) \
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|| defined(__powerpc64__) \
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|| defined(_LP64) \
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|| defined(__64BIT__)
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#ifdef __ILP32__
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#define MY_CPU_NAME "ppc64-32"
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#define MY_CPU_SIZEOF_POINTER 4
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#else
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#define MY_CPU_NAME "ppc64"
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#define MY_CPU_SIZEOF_POINTER 8
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#endif
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#define MY_CPU_64BIT
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#else
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#define MY_CPU_NAME "ppc"
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#define MY_CPU_SIZEOF_POINTER 4
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/* #define MY_CPU_32BIT */
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#endif
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#endif
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#if defined(__riscv) \
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|| defined(__riscv__)
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#if __riscv_xlen == 32
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#define MY_CPU_NAME "riscv32"
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#elif __riscv_xlen == 64
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#define MY_CPU_NAME "riscv64"
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#else
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#define MY_CPU_NAME "riscv"
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#endif
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#endif
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#if defined(MY_CPU_X86) || defined(MY_CPU_AMD64)
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#define MY_CPU_X86_OR_AMD64
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#endif
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#if defined(MY_CPU_ARM) || defined(MY_CPU_ARM64)
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#define MY_CPU_ARM_OR_ARM64
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#endif
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#ifdef _WIN32
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#ifdef MY_CPU_ARM
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#define MY_CPU_ARM_LE
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#endif
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#ifdef MY_CPU_ARM64
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#define MY_CPU_ARM64_LE
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#endif
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#ifdef _M_IA64
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#define MY_CPU_IA64_LE
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#endif
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#endif
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#if defined(MY_CPU_X86_OR_AMD64) \
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|| defined(MY_CPU_ARM_LE) \
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|| defined(MY_CPU_ARM64_LE) \
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|| defined(MY_CPU_IA64_LE) \
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|| defined(__LITTLE_ENDIAN__) \
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|| defined(__ARMEL__) \
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|| defined(__THUMBEL__) \
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|| defined(__AARCH64EL__) \
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|| defined(__MIPSEL__) \
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|| defined(__MIPSEL) \
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|| defined(_MIPSEL) \
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|| defined(__BFIN__) \
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|| (defined(__BYTE_ORDER__) && (__BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__))
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#define MY_CPU_LE
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#endif
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#if defined(__BIG_ENDIAN__) \
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|| defined(__ARMEB__) \
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|| defined(__THUMBEB__) \
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|| defined(__AARCH64EB__) \
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|| defined(__MIPSEB__) \
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|| defined(__MIPSEB) \
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|| defined(_MIPSEB) \
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|| defined(__m68k__) \
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|| defined(__s390__) \
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|| defined(__s390x__) \
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|| defined(__zarch__) \
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|| (defined(__BYTE_ORDER__) && (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__))
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#define MY_CPU_BE
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#endif
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#if defined(MY_CPU_LE) && defined(MY_CPU_BE)
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#error Stop_Compiling_Bad_Endian
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#endif
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#if !defined(MY_CPU_LE) && !defined(MY_CPU_BE)
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#error Stop_Compiling_CPU_ENDIAN_must_be_detected_at_compile_time
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#endif
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#if defined(MY_CPU_32BIT) && defined(MY_CPU_64BIT)
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#error Stop_Compiling_Bad_32_64_BIT
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#endif
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#ifdef __SIZEOF_POINTER__
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#ifdef MY_CPU_SIZEOF_POINTER
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#if MY_CPU_SIZEOF_POINTER != __SIZEOF_POINTER__
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#error Stop_Compiling_Bad_MY_CPU_PTR_SIZE
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#endif
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#else
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#define MY_CPU_SIZEOF_POINTER __SIZEOF_POINTER__
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#endif
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#endif
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#if defined(MY_CPU_SIZEOF_POINTER) && (MY_CPU_SIZEOF_POINTER == 4)
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#if defined (_LP64)
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#error Stop_Compiling_Bad_MY_CPU_PTR_SIZE
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#endif
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#endif
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#ifdef _MSC_VER
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#if _MSC_VER >= 1300
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#define MY_CPU_pragma_pack_push_1 __pragma(pack(push, 1))
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#define MY_CPU_pragma_pop __pragma(pack(pop))
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#else
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#define MY_CPU_pragma_pack_push_1
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#define MY_CPU_pragma_pop
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#endif
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#else
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#ifdef __xlC__
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#define MY_CPU_pragma_pack_push_1 _Pragma("pack(1)")
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#define MY_CPU_pragma_pop _Pragma("pack()")
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#else
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#define MY_CPU_pragma_pack_push_1 _Pragma("pack(push, 1)")
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#define MY_CPU_pragma_pop _Pragma("pack(pop)")
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#endif
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#endif
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#ifndef MY_CPU_NAME
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#ifdef MY_CPU_LE
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#define MY_CPU_NAME "LE"
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#elif defined(MY_CPU_BE)
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#define MY_CPU_NAME "BE"
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#else
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/*
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#define MY_CPU_NAME ""
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*/
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#endif
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#endif
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#ifdef __has_builtin
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#define Z7_has_builtin(x) __has_builtin(x)
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#else
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#define Z7_has_builtin(x) 0
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#endif
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#define Z7_BSWAP32_CONST(v) \
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( (((UInt32)(v) << 24) ) \
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| (((UInt32)(v) << 8) & (UInt32)0xff0000) \
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| (((UInt32)(v) >> 8) & (UInt32)0xff00 ) \
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| (((UInt32)(v) >> 24) ))
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#if defined(_MSC_VER) && (_MSC_VER >= 1300)
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#include <stdlib.h>
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/* Note: these macros will use bswap instruction (486), that is unsupported in 386 cpu */
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#pragma intrinsic(_byteswap_ushort)
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#pragma intrinsic(_byteswap_ulong)
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#pragma intrinsic(_byteswap_uint64)
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#define Z7_BSWAP16(v) _byteswap_ushort(v)
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#define Z7_BSWAP32(v) _byteswap_ulong (v)
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#define Z7_BSWAP64(v) _byteswap_uint64(v)
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#define Z7_CPU_FAST_BSWAP_SUPPORTED
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#elif (defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 3))) \
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|| (defined(__clang__) && Z7_has_builtin(__builtin_bswap16))
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#define Z7_BSWAP16(v) __builtin_bswap16(v)
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#define Z7_BSWAP32(v) __builtin_bswap32(v)
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#define Z7_BSWAP64(v) __builtin_bswap64(v)
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#define Z7_CPU_FAST_BSWAP_SUPPORTED
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#else
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#define Z7_BSWAP16(v) ((UInt16) \
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( ((UInt32)(v) << 8) \
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| ((UInt32)(v) >> 8) \
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))
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#define Z7_BSWAP32(v) Z7_BSWAP32_CONST(v)
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#define Z7_BSWAP64(v) \
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( ( ( (UInt64)(v) ) << 8 * 7 ) \
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| ( ( (UInt64)(v) & ((UInt32)0xff << 8 * 1) ) << 8 * 5 ) \
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| ( ( (UInt64)(v) & ((UInt32)0xff << 8 * 2) ) << 8 * 3 ) \
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| ( ( (UInt64)(v) & ((UInt32)0xff << 8 * 3) ) << 8 * 1 ) \
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| ( ( (UInt64)(v) >> 8 * 1 ) & ((UInt32)0xff << 8 * 3) ) \
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| ( ( (UInt64)(v) >> 8 * 3 ) & ((UInt32)0xff << 8 * 2) ) \
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| ( ( (UInt64)(v) >> 8 * 5 ) & ((UInt32)0xff << 8 * 1) ) \
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| ( ( (UInt64)(v) >> 8 * 7 ) ) \
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)
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#endif
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#ifdef MY_CPU_LE
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#if defined(MY_CPU_X86_OR_AMD64) \
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|| defined(MY_CPU_ARM64)
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#define MY_CPU_LE_UNALIGN
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#define MY_CPU_LE_UNALIGN_64
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#elif defined(__ARM_FEATURE_UNALIGNED)
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/* gcc9 for 32-bit arm can use LDRD instruction that requires 32-bit alignment.
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So we can't use unaligned 64-bit operations. */
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#define MY_CPU_LE_UNALIGN
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#endif
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#endif
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#ifdef MY_CPU_LE_UNALIGN
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#define GetUi16(p) (*(const UInt16 *)(const void *)(p))
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#define GetUi32(p) (*(const UInt32 *)(const void *)(p))
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#ifdef MY_CPU_LE_UNALIGN_64
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#define GetUi64(p) (*(const UInt64 *)(const void *)(p))
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#define SetUi64(p, v) { *(UInt64 *)(void *)(p) = (v); }
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#endif
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#define SetUi16(p, v) { *(UInt16 *)(void *)(p) = (v); }
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#define SetUi32(p, v) { *(UInt32 *)(void *)(p) = (v); }
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#else
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#define GetUi16(p) ( (UInt16) ( \
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((const Byte *)(p))[0] | \
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((UInt16)((const Byte *)(p))[1] << 8) ))
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#define GetUi32(p) ( \
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((const Byte *)(p))[0] | \
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((UInt32)((const Byte *)(p))[1] << 8) | \
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((UInt32)((const Byte *)(p))[2] << 16) | \
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((UInt32)((const Byte *)(p))[3] << 24))
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#define SetUi16(p, v) { Byte *_ppp_ = (Byte *)(p); UInt32 _vvv_ = (v); \
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_ppp_[0] = (Byte)_vvv_; \
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_ppp_[1] = (Byte)(_vvv_ >> 8); }
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#define SetUi32(p, v) { Byte *_ppp_ = (Byte *)(p); UInt32 _vvv_ = (v); \
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_ppp_[0] = (Byte)_vvv_; \
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_ppp_[1] = (Byte)(_vvv_ >> 8); \
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_ppp_[2] = (Byte)(_vvv_ >> 16); \
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_ppp_[3] = (Byte)(_vvv_ >> 24); }
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#endif
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#ifndef GetUi64
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#define GetUi64(p) (GetUi32(p) | ((UInt64)GetUi32(((const Byte *)(p)) + 4) << 32))
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#endif
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#ifndef SetUi64
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#define SetUi64(p, v) { Byte *_ppp2_ = (Byte *)(p); UInt64 _vvv2_ = (v); \
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SetUi32(_ppp2_ , (UInt32)_vvv2_) \
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SetUi32(_ppp2_ + 4, (UInt32)(_vvv2_ >> 32)) }
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#endif
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#if defined(MY_CPU_LE_UNALIGN) && defined(Z7_CPU_FAST_BSWAP_SUPPORTED)
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#define GetBe32(p) Z7_BSWAP32 (*(const UInt32 *)(const void *)(p))
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#define SetBe32(p, v) { (*(UInt32 *)(void *)(p)) = Z7_BSWAP32(v); }
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#if defined(MY_CPU_LE_UNALIGN_64)
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#define GetBe64(p) Z7_BSWAP64 (*(const UInt64 *)(const void *)(p))
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#endif
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#else
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#define GetBe32(p) ( \
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((UInt32)((const Byte *)(p))[0] << 24) | \
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((UInt32)((const Byte *)(p))[1] << 16) | \
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((UInt32)((const Byte *)(p))[2] << 8) | \
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((const Byte *)(p))[3] )
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#define SetBe32(p, v) { Byte *_ppp_ = (Byte *)(p); UInt32 _vvv_ = (v); \
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_ppp_[0] = (Byte)(_vvv_ >> 24); \
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_ppp_[1] = (Byte)(_vvv_ >> 16); \
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_ppp_[2] = (Byte)(_vvv_ >> 8); \
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_ppp_[3] = (Byte)_vvv_; }
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#endif
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#ifndef GetBe64
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#define GetBe64(p) (((UInt64)GetBe32(p) << 32) | GetBe32(((const Byte *)(p)) + 4))
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#endif
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#ifndef GetBe16
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#define GetBe16(p) ( (UInt16) ( \
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((UInt16)((const Byte *)(p))[0] << 8) | \
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((const Byte *)(p))[1] ))
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#endif
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#if defined(MY_CPU_BE)
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#define Z7_CONV_BE_TO_NATIVE_CONST32(v) (v)
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#define Z7_CONV_LE_TO_NATIVE_CONST32(v) Z7_BSWAP32_CONST(v)
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#define Z7_CONV_NATIVE_TO_BE_32(v) (v)
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#elif defined(MY_CPU_LE)
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#define Z7_CONV_BE_TO_NATIVE_CONST32(v) Z7_BSWAP32_CONST(v)
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#define Z7_CONV_LE_TO_NATIVE_CONST32(v) (v)
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#define Z7_CONV_NATIVE_TO_BE_32(v) Z7_BSWAP32(v)
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#else
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#error Stop_Compiling_Unknown_Endian_CONV
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#endif
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#if defined(MY_CPU_BE)
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#define GetBe32a(p) (*(const UInt32 *)(const void *)(p))
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#define GetBe16a(p) (*(const UInt16 *)(const void *)(p))
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#define SetBe32a(p, v) { *(UInt32 *)(void *)(p) = (v); }
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#define SetBe16a(p, v) { *(UInt16 *)(void *)(p) = (v); }
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#define GetUi32a(p) GetUi32(p)
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#define GetUi16a(p) GetUi16(p)
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#define SetUi32a(p, v) SetUi32(p, v)
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#define SetUi16a(p, v) SetUi16(p, v)
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#elif defined(MY_CPU_LE)
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#define GetUi32a(p) (*(const UInt32 *)(const void *)(p))
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#define GetUi16a(p) (*(const UInt16 *)(const void *)(p))
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#define SetUi32a(p, v) { *(UInt32 *)(void *)(p) = (v); }
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#define SetUi16a(p, v) { *(UInt16 *)(void *)(p) = (v); }
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#define GetBe32a(p) GetBe32(p)
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#define GetBe16a(p) GetBe16(p)
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#define SetBe32a(p, v) SetBe32(p, v)
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#define SetBe16a(p, v) SetBe16(p, v)
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#else
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#error Stop_Compiling_Unknown_Endian_CPU_a
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#endif
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#if defined(MY_CPU_X86_OR_AMD64) \
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|| defined(MY_CPU_ARM_OR_ARM64) \
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|| defined(MY_CPU_PPC_OR_PPC64)
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#define Z7_CPU_FAST_ROTATE_SUPPORTED
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#endif
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#ifdef MY_CPU_X86_OR_AMD64
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void Z7_FASTCALL z7_x86_cpuid(UInt32 a[4], UInt32 function);
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UInt32 Z7_FASTCALL z7_x86_cpuid_GetMaxFunc(void);
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|
#if defined(MY_CPU_AMD64)
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#define Z7_IF_X86_CPUID_SUPPORTED
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#else
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#define Z7_IF_X86_CPUID_SUPPORTED if (z7_x86_cpuid_GetMaxFunc())
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#endif
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BoolInt CPU_IsSupported_AES(void);
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|
BoolInt CPU_IsSupported_AVX(void);
|
|
BoolInt CPU_IsSupported_AVX2(void);
|
|
BoolInt CPU_IsSupported_VAES_AVX2(void);
|
|
BoolInt CPU_IsSupported_CMOV(void);
|
|
BoolInt CPU_IsSupported_SSE(void);
|
|
BoolInt CPU_IsSupported_SSE2(void);
|
|
BoolInt CPU_IsSupported_SSSE3(void);
|
|
BoolInt CPU_IsSupported_SSE41(void);
|
|
BoolInt CPU_IsSupported_SHA(void);
|
|
BoolInt CPU_IsSupported_PageGB(void);
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|
|
|
#elif defined(MY_CPU_ARM_OR_ARM64)
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|
|
BoolInt CPU_IsSupported_CRC32(void);
|
|
BoolInt CPU_IsSupported_NEON(void);
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|
|
|
#if defined(_WIN32)
|
|
BoolInt CPU_IsSupported_CRYPTO(void);
|
|
#define CPU_IsSupported_SHA1 CPU_IsSupported_CRYPTO
|
|
#define CPU_IsSupported_SHA2 CPU_IsSupported_CRYPTO
|
|
#define CPU_IsSupported_AES CPU_IsSupported_CRYPTO
|
|
#else
|
|
BoolInt CPU_IsSupported_SHA1(void);
|
|
BoolInt CPU_IsSupported_SHA2(void);
|
|
BoolInt CPU_IsSupported_AES(void);
|
|
#endif
|
|
|
|
#endif
|
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|
#if defined(__APPLE__)
|
|
int z7_sysctlbyname_Get(const char *name, void *buf, size_t *bufSize);
|
|
int z7_sysctlbyname_Get_UInt32(const char *name, UInt32 *val);
|
|
#endif
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EXTERN_C_END
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|
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|
#endif
|