16a2cf3873
5af28808 Update Auto-Sync to Python 3.13 and tree-sitter-py 24.0 (#2705) 99f018ac Python binding: (#2742) a07baf83 Auto-Sync update Sparc LLVM-18 (#2704) 81c5c93d Enable to generate legacy MC tests for the fuzzer. (#2733) a25d4980 Add warning about naive search and replace to patch reg names. (#2728) 7ac87d17 Print immediate only memory operands for AArch64. (#2732) c34034c8 Add x30 implicit read to the RET alias. (#2739) 95a4ca3e Update source list before installing valgrind. (#2730) 6909724e Make assertion hit warnings optional in release builds. (#2729) fe6bdc6e Make SStream respect the CS_OPT_UNSIGNED flag. (#2723) 21ce3624 Use cs_ac_type for operand access mode in all arches and use cs_xtensa_op_type for Xtensa operand type (#2721) df26583f clang-format: change license to BSD-3-Clause (#2724) 280b749e Remove unused files. (#2709) 87908ece Add flag for the SoftFail case of the LLVM disassembler. (#2707) efc0ba44 Fix missing operand for smstart, due to space replaced by tab (#2720) 2ae64133 Fix missing sp register read in ret instruction (#2719) 8df252a6 Fix arm pop reg access (#2718) 14612272 ARM: fix typo, cspr -> cpsr (#2716) f2f0a3c3 Fix LoongArch ld/st instructions register info (#2701) 829be2bf LoongArch: Compute absolute address for address operand (#2699) 42fbce6c Add jump group for generic jirl (#2698) fc525c73 Apple AArch64 proprietary (#2692) 895f2f2e Build PDB for debugging on Windows (#2685) 5c3aef03 Version: Update to v6.0.0-alpha4 (#2682) 106f7d3b Update read/written registers for x87 comparison instructions (#2680) ebe3ef2a Add workflow for building on Windows (#2675) 72f7d305 Revert "Add a script to compare the inc file content with the latest generate…" (#2678) 5b5c5ed8 Fix nanomips decoding of jalrc (#2672) ae03cca4 Mips32r6_64r632 is for both mips32r6 and mips64r6 (#2673) 21178aea Add a script to compare the inc file content with the latest generated ones. (#2667) 81a6ba03 MIPS: Fix MIPS16 decoding, wrong flags and ghost registers (#2665) 98a393e3 Stringify BH fields when printing ppc details (#2663) 2607d0f3 Remove undefined constants in riscv_const.py (#2660) (#2661) 5058c634 Decode BH field in print_insn_detail_ppc (#2662) 6461ed08 Add Call group to svc, smc and hvc. (#2651) e2f1dc8d Tms32c64x Little Endian (#2648) 5464c91d Fix build for compilers requiring explicit static for inline functions.. (#2645) bb2f6579 Enhance shift value and types of shift instructions. (#2638) cd282ef5 Update operand type enums of all arch modules to the one in `capstone.h` (#2633) dc0c0909 cmake: Fix building capstone as sub-project (#2629) cd8dd20c - Added missing files for sdist archive (#2624) 9affd99b Give the user some guidance where to add missing enumeration values. (#2639) 1bea3fab Add checks for MIPS details on cstest_py (#2640) ace8056c Add aliases mapping for MIPS & test for id, alias_id (#2635) 1abe1868 Build Tarball before DEB/RPM package. (#2627) 0a012190 Switch to ubuntu-24.04-arm runner image (#2625) 4e0b8c48 Fix wrong version requirement of tricore instructions: (#2620) 8ac2843b chore(version): Update Version to 6.0.0-Alpha3 (#2616) d7ef910b Rebased #2570 (#2614) c831cd5e Fix SystemZ macro in Makefile (#2603) 30601176 Apply new EVM opcode updates (#2602) 3c4d7fc8 Add tricore tc1.8 instructions (#2595) 5f290cad Create debian and rpm package on releases (#2590) 0f09210a delete travis (#2600) 5c5f756f Downgrade labeler to v4 due to https://github.com/actions/labeler/issues/710. (#2598) git-subtree-dir: external/capstone git-subtree-split: 5af288083e9f03e32723f9708c305692f866b666
153 lines
3.3 KiB
Python
153 lines
3.3 KiB
Python
from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX, UINT8_MAX
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# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [mos65xx_const.py]
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MOS65XX_REG_INVALID = 0
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MOS65XX_REG_ACC = 1
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MOS65XX_REG_X = 2
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MOS65XX_REG_Y = 3
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MOS65XX_REG_P = 4
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MOS65XX_REG_SP = 5
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MOS65XX_REG_DP = 6
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MOS65XX_REG_B = 7
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MOS65XX_REG_K = 8
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MOS65XX_REG_ENDING = 9
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MOS65XX_AM_NONE = 0
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MOS65XX_AM_IMP = 1
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MOS65XX_AM_ACC = 2
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MOS65XX_AM_IMM = 3
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MOS65XX_AM_REL = 4
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MOS65XX_AM_INT = 5
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MOS65XX_AM_BLOCK = 6
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MOS65XX_AM_ZP = 7
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MOS65XX_AM_ZP_X = 8
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MOS65XX_AM_ZP_Y = 9
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MOS65XX_AM_ZP_REL = 10
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MOS65XX_AM_ZP_IND = 11
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MOS65XX_AM_ZP_X_IND = 12
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MOS65XX_AM_ZP_IND_Y = 13
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MOS65XX_AM_ZP_IND_LONG = 14
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MOS65XX_AM_ZP_IND_LONG_Y = 15
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MOS65XX_AM_ABS = 16
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MOS65XX_AM_ABS_X = 17
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MOS65XX_AM_ABS_Y = 18
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MOS65XX_AM_ABS_IND = 19
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MOS65XX_AM_ABS_X_IND = 20
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MOS65XX_AM_ABS_IND_LONG = 21
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MOS65XX_AM_ABS_LONG = 22
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MOS65XX_AM_ABS_LONG_X = 23
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MOS65XX_AM_SR = 24
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MOS65XX_AM_SR_IND_Y = 25
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MOS65XX_INS_INVALID = 0
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MOS65XX_INS_ADC = 1
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MOS65XX_INS_AND = 2
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MOS65XX_INS_ASL = 3
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MOS65XX_INS_BBR = 4
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MOS65XX_INS_BBS = 5
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MOS65XX_INS_BCC = 6
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MOS65XX_INS_BCS = 7
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MOS65XX_INS_BEQ = 8
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MOS65XX_INS_BIT = 9
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MOS65XX_INS_BMI = 10
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MOS65XX_INS_BNE = 11
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MOS65XX_INS_BPL = 12
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MOS65XX_INS_BRA = 13
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MOS65XX_INS_BRK = 14
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MOS65XX_INS_BRL = 15
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MOS65XX_INS_BVC = 16
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MOS65XX_INS_BVS = 17
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MOS65XX_INS_CLC = 18
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MOS65XX_INS_CLD = 19
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MOS65XX_INS_CLI = 20
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MOS65XX_INS_CLV = 21
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MOS65XX_INS_CMP = 22
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MOS65XX_INS_COP = 23
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MOS65XX_INS_CPX = 24
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MOS65XX_INS_CPY = 25
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MOS65XX_INS_DEC = 26
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MOS65XX_INS_DEX = 27
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MOS65XX_INS_DEY = 28
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MOS65XX_INS_EOR = 29
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MOS65XX_INS_INC = 30
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MOS65XX_INS_INX = 31
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MOS65XX_INS_INY = 32
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MOS65XX_INS_JML = 33
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MOS65XX_INS_JMP = 34
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MOS65XX_INS_JSL = 35
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MOS65XX_INS_JSR = 36
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MOS65XX_INS_LDA = 37
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MOS65XX_INS_LDX = 38
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MOS65XX_INS_LDY = 39
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MOS65XX_INS_LSR = 40
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MOS65XX_INS_MVN = 41
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MOS65XX_INS_MVP = 42
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MOS65XX_INS_NOP = 43
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MOS65XX_INS_ORA = 44
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MOS65XX_INS_PEA = 45
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MOS65XX_INS_PEI = 46
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MOS65XX_INS_PER = 47
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MOS65XX_INS_PHA = 48
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MOS65XX_INS_PHB = 49
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MOS65XX_INS_PHD = 50
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MOS65XX_INS_PHK = 51
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MOS65XX_INS_PHP = 52
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MOS65XX_INS_PHX = 53
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MOS65XX_INS_PHY = 54
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MOS65XX_INS_PLA = 55
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MOS65XX_INS_PLB = 56
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MOS65XX_INS_PLD = 57
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MOS65XX_INS_PLP = 58
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MOS65XX_INS_PLX = 59
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MOS65XX_INS_PLY = 60
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MOS65XX_INS_REP = 61
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MOS65XX_INS_RMB = 62
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MOS65XX_INS_ROL = 63
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MOS65XX_INS_ROR = 64
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MOS65XX_INS_RTI = 65
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MOS65XX_INS_RTL = 66
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MOS65XX_INS_RTS = 67
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MOS65XX_INS_SBC = 68
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MOS65XX_INS_SEC = 69
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MOS65XX_INS_SED = 70
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MOS65XX_INS_SEI = 71
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MOS65XX_INS_SEP = 72
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MOS65XX_INS_SMB = 73
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MOS65XX_INS_STA = 74
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MOS65XX_INS_STP = 75
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MOS65XX_INS_STX = 76
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MOS65XX_INS_STY = 77
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MOS65XX_INS_STZ = 78
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MOS65XX_INS_TAX = 79
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MOS65XX_INS_TAY = 80
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MOS65XX_INS_TCD = 81
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MOS65XX_INS_TCS = 82
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MOS65XX_INS_TDC = 83
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MOS65XX_INS_TRB = 84
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MOS65XX_INS_TSB = 85
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MOS65XX_INS_TSC = 86
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MOS65XX_INS_TSX = 87
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MOS65XX_INS_TXA = 88
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MOS65XX_INS_TXS = 89
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MOS65XX_INS_TXY = 90
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MOS65XX_INS_TYA = 91
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MOS65XX_INS_TYX = 92
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MOS65XX_INS_WAI = 93
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MOS65XX_INS_WDM = 94
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MOS65XX_INS_XBA = 95
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MOS65XX_INS_XCE = 96
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MOS65XX_INS_ENDING = 97
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MOS65XX_GRP_INVALID = 0
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MOS65XX_GRP_JUMP = 1
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MOS65XX_GRP_CALL = 2
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MOS65XX_GRP_RET = 3
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MOS65XX_GRP_INT = 4
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MOS65XX_GRP_IRET = 5
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MOS65XX_GRP_BRANCH_RELATIVE = 6
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MOS65XX_GRP_ENDING = 7
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MOS65XX_OP_INVALID = CS_OP_INVALID
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MOS65XX_OP_REG = CS_OP_REG
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MOS65XX_OP_IMM = CS_OP_IMM
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MOS65XX_OP_MEM = CS_OP_MEM
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