b102f1b8 Update Actions (#2593) 86293136 Fix LoongArch aliases and CS_OPT_SYNTAX_NO_DOLLAR support (#2594) 27da950c Clarify between machine used vs. Capstone module affected. (#2586) 186f7aa0 Fix linking issue on Windows. (#2587) e160cbc5 Fix complex atomic instructions handling (#2584) 9907b22d Update v6 to have Debian Packages (#2579) efbbc3bb cstest: use DOWNLOAD_EXTRACT_TIMESTAMP conditionally (#2581) be6be784 x86: update read/write registers for transfer instructions (#2578) 812e654c Update BPF arch (#2568) 2c4b05f6 Clean up the cstest documentation and build instructions. (#2580) 4dc14ba1 Fix 2572 (#2574) b25aa841 PPC regressions (#2575) 0a29bf80 Small arm64 compat header fixes (#2563) b42e0903 Make thumb, v8 and m-class positional cstool arguments. (#2557) 89aee400 Add arm64 and sysz compatibility layer to Python bindings (#2559) a4281337 Python bindings: Enable more archs + bump cibuildwheel action to the v2.22.0 (#2558) ef74d449 Arm regressions (#2556) 93a104c0 PPC LLVM 18 (#2540) e46838ed Merge branch 'v6' into next cf3600e7 Update Changelog Version to 6.0.0-Alpha2 (#2553) b295cf57 Prepare for update (#2552) fc59da4d fix xtensa DecodeMR23RegisterClass and add tests for MAC16 instru… (#2551) 7d01d7e7 Auto-Sync reproducability + ARM update (#2532) 6ad2608d Python package building rework (#2538) e3bc578d Move debian package generation to a dispatch only workflow (#2543) abbf32b4 fix coverity (#2546) 1ecfb5b0 xtensa: update to espressif/llvm-project (#2533) 379e2a41 Rename build arguments: (#2534) d7be5f9f Change CI to create Debian Package to Release (#2521) f6f96796 tricore: fixes #2474 (#2523) 09f35961 This time actually fix big endian issue. (#2530) 306d5716 Fix endianess issue during assignment. (#2528) 2cfca35e Add CC and VAS compatibility macros (#2525) 32519c01 Fix stringop-truncation warning some compilers raise. (#2522) 5026c2c4 Merge pull request #2507 from thestr4ng3r/no-varargs-aarch64 cecb5ede Fix #2509. (#2510) f97e2705 xtensa: Fix Branch Target (#2516) 1d13a12f AArch64: Replace vararg add_cs_detail by multiple concrete functions 8b618528 Update libcyaml dependency in cstest to 1.4.2 (#2508) ea081286 Tricore EA calculation (#2504) 7db9a080 Fix cstest build with Ninja (#2506) 76242699 Only trigger on released action. (#2497) 981d648b Add hard asserts to all SStream functions and memset MCInst. (#2501) d667a627 Update labeler with Xtensa and v6 files. (#2500) 52b54ee3 Fixing UB santizer, `LITBASE` and assert errors. (#2499) 97db712c Remove irrelevant changes. (#2496) 5bd05e34 Remove irrelevant changes. (#2495) 616488c7 Update changelog for V6.0.0-Alpha1 (#2493) (#2494) c5955b92 Update changelog for V6.0.0-Alpha1 (#2493) a424e709 Be ready for V6-Alpha1 (#2492) 235ba8e0 SystemZ fixes (#2488) 5dffa75b Fix LDR not assigning immediate as memory offset. (#2487) 21f7bc85 Xtensa Support (#2380) 29d87734 Several small fixups (#2489) a34901e9 Update sponsors and remove empty file. (#2485) 3120932d Fix Coverity CID 509730: overflow before widen (#2486) 1014864d Rename CS_OPT_NO_BRANCH_OFFSET and corresponding flag to better name. (#2482) 0c90fe13 Replace `assert` with `CS_ASSERT` in modules (#2478) 823bfd53 AArch64 issues (#2473) git-subtree-dir: external/capstone git-subtree-split: b102f1b89e0455c072a751d287ab64378c14205f
110 lines
2.6 KiB
Python
110 lines
2.6 KiB
Python
# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
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import ctypes
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from . import copy_ctypes_list
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from .arm_const import *
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# define the API
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class ArmOpMem(ctypes.Structure):
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_fields_ = (
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('base', ctypes.c_int),
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('index', ctypes.c_int),
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('scale', ctypes.c_int),
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('disp', ctypes.c_int),
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('align', ctypes.c_uint),
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)
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class ArmOpShift(ctypes.Structure):
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_fields_ = (
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('type', ctypes.c_uint),
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('value', ctypes.c_uint),
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)
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class ArmSysopReg(ctypes.Union):
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_fields_ = (
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('mclasssysreg', ctypes.c_uint),
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('bankedreg', ctypes.c_uint),
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('raw_val', ctypes.c_int),
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)
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class ArmOpSysop(ctypes.Structure):
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_fields_ = (
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('reg', ArmSysopReg),
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('psr_bits', ctypes.c_uint),
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('sysm', ctypes.c_uint16),
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('msr_mask', ctypes.c_uint8),
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)
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class ArmOpValue(ctypes.Union):
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_fields_ = (
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('reg', ctypes.c_uint),
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('sysop', ArmOpSysop),
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('imm', ctypes.c_int64),
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('pred', ctypes.c_int),
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('fp', ctypes.c_double),
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('mem', ArmOpMem),
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('setend', ctypes.c_int),
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)
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class ArmOp(ctypes.Structure):
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_fields_ = (
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('vector_index', ctypes.c_int),
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('shift', ArmOpShift),
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('type', ctypes.c_uint),
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('value', ArmOpValue),
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('subtracted', ctypes.c_bool),
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('access', ctypes.c_uint8),
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('neon_lane', ctypes.c_int8),
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)
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@property
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def reg(self):
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return self.value.reg
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@property
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def sysop(self):
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return self.value.sysop
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@property
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def imm(self):
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return self.value.imm
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@property
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def pred(self):
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return self.value.pred
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@property
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def fp(self):
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return self.value.fp
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@property
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def mem(self):
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return self.value.mem
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@property
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def setend(self):
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return self.value.setend
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class CsArm(ctypes.Structure):
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_fields_ = (
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('usermode', ctypes.c_bool),
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('vector_size', ctypes.c_int),
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('vector_data', ctypes.c_int),
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('cps_mode', ctypes.c_int),
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('cps_flag', ctypes.c_int),
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('cc', ctypes.c_uint),
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('vcc', ctypes.c_uint),
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('update_flags', ctypes.c_bool),
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('post_index', ctypes.c_bool),
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('mem_barrier', ctypes.c_int),
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('pred_mask', ctypes.c_uint8),
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('op_count', ctypes.c_uint8),
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('operands', ArmOp * 36),
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)
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def get_arch_info(a):
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return (a.usermode, a.vector_size, a.vector_data, a.cps_mode, a.cps_flag, a.cc, a.vcc, a.update_flags, \
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a.post_index, a.mem_barrier, a.pred_mask, copy_ctypes_list(a.operands[:a.op_count]))
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