191 lines
4.2 KiB
C
191 lines
4.2 KiB
C
//===- MipsCP0RegisterMap.h - Co-processor register names for Mips/nanoMIPS -===//
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// This has been created by hand.
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#ifndef LLVM_LIB_TARGET_MIPS_NANOMIPSCP0REGMAP_H
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#define LLVM_LIB_TARGET_MIPS_NANOMIPSCP0REGMAP_H
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struct CP0SelRegister_t {
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const char *Name;
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int RegNum;
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int Select;
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int Index;
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};
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static const struct CP0SelRegister_t CP0SelRegs[] = {
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{"index", 0, 0},
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{"mvpcontrol", 0, 1},
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{"mvpconf0", 0, 2},
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{"mvpconf1", 0, 3},
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{"vpcontrol", 0, 4},
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{"random", 1, 0},
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{"vpecontrol", 1, 1},
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{"vpeconf0", 1, 2},
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{"vpeconf1", 1, 3},
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{"yqmask", 1, 4},
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{"vpeschedule", 1, 5},
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{"vpeschefback", 1, 6},
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{"vpeopt", 1, 7},
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{"entrylo0", 2, 0},
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{"tcstatus", 2, 1},
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{"tcbind", 2, 2},
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{"tcrestart", 2, 3},
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{"tchalt", 2, 4},
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{"tccontext", 2, 5},
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{"tcschedule", 2, 6},
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{"tcschefback", 2, 7},
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{"entrylo1", 3, 0},
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{"globalnumber", 3, 1},
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{"tcopt", 3, 7},
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{"context", 4, 0},
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{"contextconfig", 4, 1},
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{"userlocal", 4, 2},
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{"xcontextconfig", 4, 3},
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{"debugcontextid", 4, 4},
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{"memorymapid", 4, 5},
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{"pagemask", 5, 0},
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{"pagegrain", 5, 1},
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{"segctl0", 5, 2},
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{"segctl1", 5, 3},
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{"segctl2", 5, 4},
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{"pwbase", 5, 5},
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{"pwfield", 5, 6},
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{"pwsize", 5, 7},
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{"wired", 6, 0},
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{"srsconf0", 6, 1},
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{"srsconf1", 6, 2},
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{"srsconf2", 6, 3},
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{"srsconf3", 6, 4},
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{"srsconf4", 6, 5},
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{"pwctl", 6, 6},
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{"hwrena", 7, 0},
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{"badvaddr", 8, 0},
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{"badinst", 8, 1},
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{"badinstrp", 8, 2},
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{"badinstrx", 8, 3},
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{"count", 9, 0},
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{"entryhi", 10, 0},
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{"guestctl1", 10, 4},
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{"guestctl2", 10, 5},
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{"guestctl3", 10, 6},
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{"compare", 11, 0},
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{"guestctl0ext", 11, 4},
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{"status", 12, 0},
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{"intctl", 12, 1},
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{"srsctl", 12, 2},
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{"srsmap", 12, 3},
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{"view_ipl", 12, 4},
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{"srsmap2", 12, 5},
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{"guestctl0", 12, 6},
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{"gtoffset", 12, 7},
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{"cause", 13, 0},
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{"view_ripl", 13, 4},
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{"nestedexc", 13, 5},
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{"epc", 14, 0},
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{"nestedepc", 14, 2},
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{"prid", 15, 0},
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{"ebase", 15, 1},
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{"cdmmbase", 15, 2},
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{"cmgcrbase", 15, 3},
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{"bevva", 15, 4},
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{"config", 16, 0},
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{"config1", 16, 1},
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{"config2", 16, 2},
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{"config3", 16, 3},
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{"config4", 16, 4},
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{"config5", 16, 5},
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{"lladdr", 17, 0},
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{"maar", 17, 1},
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{"maari", 17, 2},
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{"watchlo0", 18, 0},
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{"watchlo1", 18, 1},
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{"watchlo2", 18, 2},
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{"watchlo3", 18, 3},
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{"watchlo4", 18, 4},
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{"watchlo5", 18, 5},
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{"watchlo6", 18, 6},
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{"watchlo7", 18, 7},
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{"watchlo8", 18, 8},
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{"watchlo9", 18, 9},
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{"watchlo10", 18,10},
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{"watchlo11", 18,11},
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{"watchlo12", 18,12},
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{"watchlo13", 18,13},
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{"watchlo14", 18,14},
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{"watchlo15", 18,15},
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{"watchhi0", 19, 0},
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{"watchhi1", 19, 1},
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{"watchhi2", 19, 2},
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{"watchhi3", 19, 3},
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{"watchhi4", 19, 4},
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{"watchhi5", 19, 5},
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{"watchhi6", 19, 6},
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{"watchhi7", 19, 7},
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{"watchhi8", 19, 8},
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{"watchhi9", 19, 9},
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{"watchhi10", 19,10},
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{"watchhi11", 19,11},
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{"watchhi12", 19,12},
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{"watchhi13", 19,13},
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{"watchhi14", 19,14},
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{"watchhi15", 19,15},
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{"xcontext", 20, 0},
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{"debug", 23, 0},
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{"tracecontrol", 23, 1},
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{"tracecontrol2", 23, 2},
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{"usertracedata1", 23, 3},
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{"traceibpc", 23, 4},
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{"tracedbpc", 23, 5},
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{"debug2", 23, 6},
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{"depc", 24, 0},
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{"tracecontrol3", 24, 2},
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{"usertracedata2", 24, 3},
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{"perfctl0", 25, 0},
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{"perfcnt0", 25, 1},
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{"perfctl1", 25, 2},
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{"perfcnt1", 25, 3},
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{"perfctl2", 25, 4},
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{"perfcnt2", 25, 5},
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{"perfctl3", 25, 6},
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{"perfcnt3", 25, 7},
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{"perfctl4", 25, 8},
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{"perfcnt4", 25, 9},
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{"perfctl5", 25,10},
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{"perfcnt5", 25,11},
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{"perfctl6", 25,12},
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{"perfcnt6", 25,13},
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{"perfctl7", 25,14},
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{"perfcnt7", 25,15},
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{"errctl", 26, 0},
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{"cacheerr", 27, 0},
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{"itaglo", 28, 0},
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{"idatalo", 28, 1},
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{"dtaglo", 28, 2},
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{"ddatalo", 28, 3},
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{"itaghi", 29, 0},
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{"idatahi", 29, 1},
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{"dtaghi", 29, 2},
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{"ddatahi", 29, 3},
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{"errorepc", 30, 0},
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{"desave", 31, 0},
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{"kscratch1", 31, 2},
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{"kscratch2", 31, 3},
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{"kscratch3", 31, 4},
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{"kscratch4", 31, 5},
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{"kscratch5", 31, 6},
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{"kscratch6", 31, 7}
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};
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inline static int COP0Map_getEncIndexMap(int RegNo)
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{
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int i;
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for (i = 0; i < (sizeof(CP0SelRegs) / sizeof(CP0SelRegs[0])); ++i) {
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unsigned RegEnc = (CP0SelRegs[i].RegNum << 5) | CP0SelRegs[i].Select;
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if (RegEnc == RegNo) {
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return i;
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}
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}
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return -1;
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}
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#endif // LLVM_LIB_TARGET_MIPS_NANOMIPSCP0REGMAP_H
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