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Fix RDRAM masking

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SimoneN64
2024-07-14 03:49:58 +02:00
parent 81cab7182d
commit c9ab6b358c
2 changed files with 6 additions and 6 deletions
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8
src/backend/core/RSP.cpp
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@@ -130,7 +130,7 @@ template <> void RSP::DMA<true>() {
int skip = i == spDMALen.count ? 0 : spDMALen.skip;
dram_address += (length + skip);
dram_address &= 0xFFFFFC;
dram_address &= 0xFFFFFE;
mem_address += length;
mem_address &= 0xFF8;
}
@@ -150,7 +150,7 @@ template <> void RSP::DMA<false>() {
std::array<u8, DMEM_SIZE>& dst = spDMASPAddr.bank ? imem : dmem;
u32 mem_address = spDMASPAddr.address & 0xFF8;
u32 dram_address = spDMADRAMAddr.address & 0xFFFFFC;
u32 dram_address = spDMADRAMAddr.address & 0xFFFFFE;
Util::trace("SP DMA from RDRAM to RSP (size: {} B, {:08X} to {:08X})", length, dram_address, mem_address);
for (u32 i = 0; i < spDMALen.count + 1; i++) {
@@ -161,7 +161,7 @@ template <> void RSP::DMA<false>() {
int skip = i == spDMALen.count ? 0 : spDMALen.skip;
dram_address += (length + skip);
dram_address &= 0xFFFFFC;
dram_address &= 0xFFFFFE;
mem_address += length;
mem_address &= 0xFF8;
}
@@ -176,7 +176,7 @@ template <> void RSP::DMA<false>() {
void RSP::Write(u32 addr, u32 val) {
switch (addr) {
case 0x04040000: spDMASPAddr.raw = val & 0x1FF8; break;
case 0x04040004: spDMADRAMAddr.raw = val & 0xFFFFFC; break;
case 0x04040004: spDMADRAMAddr.raw = val & 0xFFFFFE; break;
case 0x04040008: {
spDMALen.raw = val;
DMA<false>();

2
src/backend/core/mmio/PI.cpp
View File

@@ -468,7 +468,7 @@ template <> void PI::DMA<true>() {
void PI::Write(u32 addr, u32 val) {
MI& mi = mem.mmio.mi;
switch(addr) {
case 0x04600000: dramAddr = val & 0x00FFFFFC; break;
case 0x04600000: dramAddr = val & 0x00FFFFFE; break;
case 0x04600004: cartAddr = val & 0xFFFFFFFE; break;
case 0x04600008: {
rdLen = val & 0x00FFFFFF;