Squashed 'external/capstone/' changes from b102f1b8..5af28808

5af28808 Update Auto-Sync to Python 3.13 and tree-sitter-py 24.0 (#2705)
99f018ac Python binding: (#2742)
a07baf83 Auto-Sync update Sparc LLVM-18 (#2704)
81c5c93d Enable to generate legacy MC tests for the fuzzer. (#2733)
a25d4980 Add warning about naive search and replace to patch reg names. (#2728)
7ac87d17 Print immediate only memory operands for AArch64. (#2732)
c34034c8 Add x30 implicit read to the RET alias. (#2739)
95a4ca3e Update source list before installing valgrind. (#2730)
6909724e Make assertion hit warnings optional in release builds. (#2729)
fe6bdc6e Make SStream respect the CS_OPT_UNSIGNED flag. (#2723)
21ce3624 Use cs_ac_type for operand access mode in all arches and use cs_xtensa_op_type for Xtensa operand type (#2721)
df26583f clang-format: change license to BSD-3-Clause (#2724)
280b749e Remove unused files. (#2709)
87908ece Add flag for the SoftFail case of the LLVM disassembler. (#2707)
efc0ba44 Fix missing operand for smstart, due to space replaced by tab (#2720)
2ae64133 Fix missing sp register read in ret instruction (#2719)
8df252a6 Fix arm pop reg access (#2718)
14612272 ARM: fix typo, cspr -> cpsr (#2716)
f2f0a3c3 Fix LoongArch ld/st instructions register info (#2701)
829be2bf LoongArch: Compute absolute address for address operand (#2699)
42fbce6c Add jump group for generic jirl (#2698)
fc525c73 Apple AArch64 proprietary (#2692)
895f2f2e Build PDB for debugging on Windows (#2685)
5c3aef03 Version: Update to v6.0.0-alpha4 (#2682)
106f7d3b Update read/written registers for x87 comparison instructions (#2680)
ebe3ef2a Add workflow for building on Windows (#2675)
72f7d305 Revert "Add a script to compare the inc file content with the latest generate…" (#2678)
5b5c5ed8 Fix nanomips decoding of jalrc (#2672)
ae03cca4 Mips32r6_64r632 is for both mips32r6 and mips64r6 (#2673)
21178aea Add a script to compare the inc file content with the latest generated ones. (#2667)
81a6ba03 MIPS: Fix MIPS16 decoding, wrong flags and ghost registers (#2665)
98a393e3 Stringify BH fields when printing ppc details (#2663)
2607d0f3 Remove undefined constants in riscv_const.py (#2660) (#2661)
5058c634 Decode BH field in print_insn_detail_ppc (#2662)
6461ed08 Add Call group to svc, smc and hvc. (#2651)
e2f1dc8d Tms32c64x Little Endian (#2648)
5464c91d Fix build for compilers requiring explicit static for inline functions.. (#2645)
bb2f6579 Enhance shift value and types of shift instructions. (#2638)
cd282ef5 Update operand type enums of all arch modules to the one in `capstone.h` (#2633)
dc0c0909 cmake: Fix building capstone as sub-project (#2629)
cd8dd20c - Added missing files for sdist archive (#2624)
9affd99b Give the user some guidance where to add missing enumeration values. (#2639)
1bea3fab Add checks for MIPS details on cstest_py (#2640)
ace8056c Add aliases mapping for MIPS & test for id, alias_id (#2635)
1abe1868 Build Tarball before DEB/RPM package. (#2627)
0a012190 Switch to ubuntu-24.04-arm runner image (#2625)
4e0b8c48 Fix wrong version requirement of tricore instructions: (#2620)
8ac2843b chore(version): Update Version to 6.0.0-Alpha3 (#2616)
d7ef910b Rebased #2570 (#2614)
c831cd5e Fix SystemZ macro in Makefile (#2603)
30601176 Apply new EVM opcode updates (#2602)
3c4d7fc8 Add tricore tc1.8 instructions (#2595)
5f290cad Create debian and rpm package on releases (#2590)
0f09210a delete travis (#2600)
5c5f756f Downgrade labeler to v4 due to https://github.com/actions/labeler/issues/710. (#2598)

git-subtree-dir: external/capstone
git-subtree-split: 5af288083e9f03e32723f9708c305692f866b666

bindings/python/capstone/__init__.py

@@ -42,6 +42,7 @@ __all__ = [
     'CS_ARCH_HPPA',
     'CS_ARCH_LOONGARCH',
     'CS_ARCH_XTENSA',
+    'CS_ARCH_ARC',
     'CS_ARCH_ALL',
 
     'CS_MODE_LITTLE_ENDIAN',
@@ -53,6 +54,7 @@ __all__ = [
     'CS_MODE_THUMB',
     'CS_MODE_MCLASS',
     'CS_MODE_V8',
+	'CS_MODE_APPLE_PROPRIETARY',
     'CS_MODE_V9',
     'CS_MODE_QPX',
     'CS_MODE_SPE',
@@ -126,6 +128,7 @@ __all__ = [
     'CS_MODE_TRICORE_160',
     'CS_MODE_TRICORE_161',
     'CS_MODE_TRICORE_162',
+    "CS_MODE_TRICORE_180",
     'CS_MODE_HPPA_11',
     'CS_MODE_HPPA_20',
     'CS_MODE_HPPA_20W',
@@ -269,9 +272,13 @@ CS_ARCH_ALPHA = 18
 CS_ARCH_HPPA = 19
 CS_ARCH_LOONGARCH = 20
 CS_ARCH_XTENSA = 21
-CS_ARCH_MAX = 21
+CS_ARCH_ARC = 22
+CS_ARCH_MAX = 22
 CS_ARCH_ALL = 0xFFFF
 
+CS_MODE_AARCH64_ISA_BITS = 0x00fffff8
+CS_MODE_VENDOR_AARCH64_BIT0 = 30
+
 # disasm mode
 CS_MODE_LITTLE_ENDIAN = 0      # little-endian mode (default mode)
 CS_MODE_ARM = 0                # ARM mode
@@ -281,6 +288,7 @@ CS_MODE_64 = (1 << 3)          # 64-bit mode (for X86, PPC)
 CS_MODE_THUMB = (1 << 4)       # ARM's Thumb mode, including Thumb-2
 CS_MODE_MCLASS = (1 << 5)      # ARM's Cortex-M series
 CS_MODE_V8 = (1 << 6)          # ARMv8 A32 encodings for ARM
+CS_MODE_APPLE_PROPRIETARY = (1 << CS_MODE_VENDOR_AARCH64_BIT0)  # Apple proprietary AArch64 instructions like AMX, MUL53, and others.
 CS_MODE_MICRO = (1 << 4)       # MicroMips mode (MIPS architecture)
 CS_MODE_MIPS3 = (1 << 5)       # Mips III ISA
 CS_MODE_MIPS32R6 = (1 << 6)    # Mips32r6 ISA
@@ -367,6 +375,7 @@ CS_MODE_TRICORE_131 = 1 << 4 # Tricore 1.3.1
 CS_MODE_TRICORE_160 = 1 << 5 # Tricore 1.6
 CS_MODE_TRICORE_161 = 1 << 6 # Tricore 1.6.1
 CS_MODE_TRICORE_162 = 1 << 7 # Tricore 1.6.2
+CS_MODE_TRICORE_180 = 1 << 8 # Tricore 1.8.0
 CS_MODE_HPPA_11 = 1 << 1 # HPPA 1.1
 CS_MODE_HPPA_20 = 1 << 2 # HPPA 2.0
 CS_MODE_HPPA_20W = CS_MODE_HPPA_20 | (1 << 3) # HPPA 2.0 wide
@@ -561,7 +570,7 @@ def copy_ctypes_list(src):
 
 # Weird import placement because these modules are needed by the below code but need the above functions
 from . import arm, aarch64, m68k, mips, ppc, sparc, systemz, x86, xcore, tms320c64x, m680x, evm, mos65xx, wasm, bpf, \
-    riscv, sh, tricore, alpha, hppa, loongarch, xtensa
+    riscv, sh, tricore, alpha, hppa, loongarch, arc, xtensa
 
 
 class _cs_arch(ctypes.Union):
@@ -588,6 +597,7 @@ class _cs_arch(ctypes.Union):
         ('hppa', hppa.CsHPPA),
         ('loongarch', loongarch.CsLoongArch),
         ('xtensa', xtensa.CsXtensa),
+        ('arc', arc.CsARC),
     )
 
 
@@ -615,6 +625,7 @@ class _cs_insn(ctypes.Structure):
         ('op_str', ctypes.c_char * 160),
         ('is_alias', ctypes.c_bool),
         ('usesAliasDetails', ctypes.c_bool),
+        ('illegal', ctypes.c_bool),
         ('detail', ctypes.POINTER(_cs_detail)),
     )
 
@@ -786,7 +797,7 @@ class CsInsn(object):
     def __init__(self, cs, all_info):
         self._raw = copy_ctypes(all_info)
         self._cs = cs
-        if self._cs._detail and self._raw.id != 0:
+        if self._cs._detail and not self.is_invalid_insn():
             # save detail
             self._raw.detail = ctypes.pointer(all_info.detail._type_())
             ctypes.memmove(ctypes.byref(self._raw.detail[0]), ctypes.byref(all_info.detail[0]),
@@ -795,6 +806,14 @@ class CsInsn(object):
     def __repr__(self):
         return '<CsInsn 0x%x [%s]: %s %s>' % (self.address, self.bytes.hex(), self.mnemonic, self.op_str)
 
+    # return if the instruction is invalid
+    def is_invalid_insn(self):
+        arch = self._cs.arch
+        if arch == CS_ARCH_EVM:
+            return self.id == evm.EVM_INS_INVALID
+        else:
+            return self.id == 0
+
     # return instruction's ID.
     @property
     def id(self):
@@ -815,6 +834,13 @@ class CsInsn(object):
     def is_alias(self):
         return self._raw.is_alias
 
+    # return instruction's illegal flag
+    # Set if instruction can be decoded but is invalid
+    # due to context or illegal operands.
+    @property
+    def illegal(self):
+        return self._raw.illegal
+
     # return instruction's alias_id
     @property
     def alias_id(self):
@@ -851,7 +877,7 @@ class CsInsn(object):
     # return list of all implicit registers being read.
     @property
     def regs_read(self):
-        if self._raw.id == 0:
+        if self.is_invalid_insn():
             raise CsError(CS_ERR_SKIPDATA)
 
         if self._cs._diet:
@@ -866,7 +892,7 @@ class CsInsn(object):
     # return list of all implicit registers being modified
     @property
     def regs_write(self):
-        if self._raw.id == 0:
+        if self.is_invalid_insn():
             raise CsError(CS_ERR_SKIPDATA)
 
         if self._cs._diet:
@@ -881,7 +907,7 @@ class CsInsn(object):
     # return list of semantic groups this instruction belongs to.
     @property
     def groups(self):
-        if self._raw.id == 0:
+        if self.is_invalid_insn():
             raise CsError(CS_ERR_SKIPDATA)
 
         if self._cs._diet:
@@ -896,7 +922,7 @@ class CsInsn(object):
     # return whether instruction has writeback operands.
     @property
     def writeback(self):
-        if self._raw.id == 0:
+        if self.is_invalid_insn():
             raise CsError(CS_ERR_SKIPDATA)
 
         if self._cs._diet:
@@ -909,7 +935,7 @@ class CsInsn(object):
         raise CsError(CS_ERR_DETAIL)
 
     def __gen_detail(self):
-        if self._raw.id == 0:
+        if self.is_invalid_insn():
             # do nothing in skipdata mode
             return
 
@@ -935,7 +961,7 @@ class CsInsn(object):
             (self.bc, self.update_cr0, self.format, self.operands) = \
                 ppc.get_arch_info(self._raw.detail.contents.arch.ppc)
         elif arch == CS_ARCH_SPARC:
-            (self.cc, self.hint, self.operands) = sparc.get_arch_info(self._raw.detail.contents.arch.sparc)
+            (self.cc, self.cc_field, self.hint, self.format, self.operands) = sparc.get_arch_info(self._raw.detail.contents.arch.sparc)
         elif arch == CS_ARCH_SYSTEMZ:
             (self.cc, self.format, self.operands) = systemz.get_arch_info(self._raw.detail.contents.arch.systemz)
         elif arch == CS_ARCH_XCORE:
@@ -964,6 +990,8 @@ class CsInsn(object):
             (self.operands) = hppa.get_arch_info(self._raw.detail.contents.arch.hppa)
         elif arch == CS_ARCH_LOONGARCH:
             (self.format, self.operands) = loongarch.get_arch_info(self._raw.detail.contents.arch.loongarch)
+        elif arch == CS_ARCH_ARC:
+            (self.operands) = arc.get_arch_info(self._raw.detail.contents.arch.arc)
         elif arch == CS_ARCH_XTENSA:
             (self.operands) = xtensa.get_arch_info(self._raw.detail.contents.arch.xtensa)
 
@@ -978,7 +1006,7 @@ class CsInsn(object):
         if 'operands' not in _dict:
             self.__gen_detail()
         if name not in _dict:
-            if self._raw.id == 0:
+            if self.is_invalid_insn():
                 raise CsError(CS_ERR_SKIPDATA)
             raise AttributeError(f"'CsInsn' has no attribute '{name}'")
         return _dict[name]
@@ -1001,7 +1029,7 @@ class CsInsn(object):
             # Diet engine cannot provide instruction name
             raise CsError(CS_ERR_DIET)
 
-        if self._raw.id == 0:
+        if self.is_invalid_insn():
             return default
 
         return _ascii_name_or_default(_cs.cs_insn_name(self._cs.csh, self.id), default)
@@ -1016,7 +1044,7 @@ class CsInsn(object):
 
     # verify if this insn belong to group with id as @group_id
     def group(self, group_id):
-        if self._raw.id == 0:
+        if self.is_invalid_insn():
             raise CsError(CS_ERR_SKIPDATA)
 
         if self._cs._diet:
@@ -1027,7 +1055,7 @@ class CsInsn(object):
 
     # verify if this instruction implicitly read register @reg_id
     def reg_read(self, reg_id):
-        if self._raw.id == 0:
+        if self.is_invalid_insn():
             raise CsError(CS_ERR_SKIPDATA)
 
         if self._cs._diet:
@@ -1038,7 +1066,7 @@ class CsInsn(object):
 
     # verify if this instruction implicitly modified register @reg_id
     def reg_write(self, reg_id):
-        if self._raw.id == 0:
+        if self.is_invalid_insn():
             raise CsError(CS_ERR_SKIPDATA)
 
         if self._cs._diet:
@@ -1049,7 +1077,7 @@ class CsInsn(object):
 
     # return number of operands having same operand type @op_type
     def op_count(self, op_type):
-        if self._raw.id == 0:
+        if self.is_invalid_insn():
             raise CsError(CS_ERR_SKIPDATA)
 
         c = 0
@@ -1060,7 +1088,7 @@ class CsInsn(object):
 
     # get the operand at position @position of all operands having the same type @op_type
     def op_find(self, op_type, position):
-        if self._raw.id == 0:
+        if self.is_invalid_insn():
             raise CsError(CS_ERR_SKIPDATA)
 
         c = 0
@@ -1073,7 +1101,7 @@ class CsInsn(object):
     # Return (list-of-registers-read, list-of-registers-modified) by this instructions.
     # This includes all the implicit & explicit registers.
     def regs_access(self):
-        if self._raw.id == 0:
+        if self.is_invalid_insn():
             raise CsError(CS_ERR_SKIPDATA)
 
         regs_read = (ctypes.c_uint16 * 64)()
@@ -1440,7 +1468,8 @@ def debug():
         "m680x": CS_ARCH_M680X, 'evm': CS_ARCH_EVM, 'mos65xx': CS_ARCH_MOS65XX,
         'bpf': CS_ARCH_BPF, 'riscv': CS_ARCH_RISCV, 'tricore': CS_ARCH_TRICORE,
         'wasm': CS_ARCH_WASM, 'sh': CS_ARCH_SH, 'alpha': CS_ARCH_ALPHA,
-        'hppa': CS_ARCH_HPPA, 'loongarch': CS_ARCH_LOONGARCH, 'xtensa': CS_ARCH_XTENSA
+        'hppa': CS_ARCH_HPPA, 'loongarch': CS_ARCH_LOONGARCH, 'xtensa': CS_ARCH_XTENSA, 
+        'arc': CS_ARCH_ARC
     }
 
     all_archs = ""

bindings/python/capstone/aarch64.py

@@ -110,7 +110,7 @@ class AArch64Op(ctypes.Structure):
         ('is_vreg', ctypes.c_bool),
         ('value', AArch64OpValue),
         ('sysop', AArch64SysOp),
-        ('access', ctypes.c_uint8),
+        ('access', ctypes.c_uint),
         ('is_list_member', ctypes.c_bool),
     )
 

bindings/python/capstone/alpha.py

@@ -20,7 +20,7 @@ class AlphaOp(ctypes.Structure):
     _fields_ = (
         ('type', ctypes.c_uint),
         ('value', AlphaOpValue),
-        ('access', ctypes.c_uint8)
+        ('access', ctypes.c_uint)
     )
 
     @property

bindings/python/capstone/arc.py

@@ -0,0 +1,39 @@
+# Capstone Python bindings, by R33v0LT <sibirtsevdl@gmail.com>
+
+import ctypes
+from . import copy_ctypes_list
+from .arc_const import *
+
+
+class ARCOpValue(ctypes.Union):
+    _fields_ = (
+        ('reg', ctypes.c_uint),
+        ('imm', ctypes.c_int64)
+    )
+
+
+class ARCOp(ctypes.Structure):
+    _fields_ = (
+        ('type', ctypes.c_int),
+        ('value', ARCOpValue),
+        ('access', ctypes.c_uint)
+    )
+
+    @property
+    def imm(self):
+        return self.value.imm
+
+    @property
+    def reg(self):
+        return self.value.reg
+
+
+# Instruction structure
+class CsARC(ctypes.Structure):
+    _fields_ = (
+        ('op_count', ctypes.c_uint8),
+        ('operands', ARCOp * 8),
+    )
+
+def get_arch_info(a):
+    return (copy_ctypes_list(a.operands[:a.op_count]))

bindings/python/capstone/arc_const.py

@@ -0,0 +1,274 @@
+from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX, UINT8_MAX
+# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [arc_const.py]
+ARC_OP_INVALID = CS_OP_INVALID
+ARC_OP_REG = CS_OP_REG
+ARC_OP_IMM = CS_OP_IMM
+
+ARC_REG_INVALID = 0
+ARC_REG_BLINK = 1
+ARC_REG_FP = 2
+ARC_REG_GP = 3
+ARC_REG_ILINK = 4
+ARC_REG_SP = 5
+ARC_REG_R0 = 6
+ARC_REG_R1 = 7
+ARC_REG_R2 = 8
+ARC_REG_R3 = 9
+ARC_REG_R4 = 10
+ARC_REG_R5 = 11
+ARC_REG_R6 = 12
+ARC_REG_R7 = 13
+ARC_REG_R8 = 14
+ARC_REG_R9 = 15
+ARC_REG_R10 = 16
+ARC_REG_R11 = 17
+ARC_REG_R12 = 18
+ARC_REG_R13 = 19
+ARC_REG_R14 = 20
+ARC_REG_R15 = 21
+ARC_REG_R16 = 22
+ARC_REG_R17 = 23
+ARC_REG_R18 = 24
+ARC_REG_R19 = 25
+ARC_REG_R20 = 26
+ARC_REG_R21 = 27
+ARC_REG_R22 = 28
+ARC_REG_R23 = 29
+ARC_REG_R24 = 30
+ARC_REG_R25 = 31
+ARC_REG_R30 = 32
+ARC_REG_R32 = 33
+ARC_REG_R33 = 34
+ARC_REG_R34 = 35
+ARC_REG_R35 = 36
+ARC_REG_R36 = 37
+ARC_REG_R37 = 38
+ARC_REG_R38 = 39
+ARC_REG_R39 = 40
+ARC_REG_R40 = 41
+ARC_REG_R41 = 42
+ARC_REG_R42 = 43
+ARC_REG_R43 = 44
+ARC_REG_R44 = 45
+ARC_REG_R45 = 46
+ARC_REG_R46 = 47
+ARC_REG_R47 = 48
+ARC_REG_R48 = 49
+ARC_REG_R49 = 50
+ARC_REG_R50 = 51
+ARC_REG_R51 = 52
+ARC_REG_R52 = 53
+ARC_REG_R53 = 54
+ARC_REG_R54 = 55
+ARC_REG_R55 = 56
+ARC_REG_R56 = 57
+ARC_REG_R57 = 58
+ARC_REG_R58 = 59
+ARC_REG_R59 = 60
+ARC_REG_R60 = 61
+ARC_REG_R61 = 62
+ARC_REG_R62 = 63
+ARC_REG_R63 = 64
+ARC_REG_STATUS32 = 65
+ARC_REG_ENDING = 66
+
+ARC_INS_INVALID = 0
+ARC_INS_h = 1
+ARC_INS_PBR = 2
+ARC_INS_ERROR_FLS = 3
+ARC_INS_ERROR_FFS = 4
+ARC_INS_PLDFI = 5
+ARC_INS_STB_FAR = 6
+ARC_INS_STH_FAR = 7
+ARC_INS_ST_FAR = 8
+ARC_INS_ADC = 9
+ARC_INS_ADC_F = 10
+ARC_INS_ADD_S = 11
+ARC_INS_ADD = 12
+ARC_INS_ADD_F = 13
+ARC_INS_AND = 14
+ARC_INS_AND_F = 15
+ARC_INS_ASL_S = 16
+ARC_INS_ASL = 17
+ARC_INS_ASL_F = 18
+ARC_INS_ASR_S = 19
+ARC_INS_ASR = 20
+ARC_INS_ASR_F = 21
+ARC_INS_BCLR_S = 22
+ARC_INS_BEQ_S = 23
+ARC_INS_BGE_S = 24
+ARC_INS_BGT_S = 25
+ARC_INS_BHI_S = 26
+ARC_INS_BHS_S = 27
+ARC_INS_BL = 28
+ARC_INS_BLE_S = 29
+ARC_INS_BLO_S = 30
+ARC_INS_BLS_S = 31
+ARC_INS_BLT_S = 32
+ARC_INS_BL_S = 33
+ARC_INS_BMSK_S = 34
+ARC_INS_BNE_S = 35
+ARC_INS_B = 36
+ARC_INS_BREQ_S = 37
+ARC_INS_BRNE_S = 38
+ARC_INS_BR = 39
+ARC_INS_BSET_S = 40
+ARC_INS_BTST_S = 41
+ARC_INS_B_S = 42
+ARC_INS_CMP_S = 43
+ARC_INS_CMP = 44
+ARC_INS_LD_S = 45
+ARC_INS_MOV_S = 46
+ARC_INS_EI_S = 47
+ARC_INS_ENTER_S = 48
+ARC_INS_FFS_F = 49
+ARC_INS_FFS = 50
+ARC_INS_FLS_F = 51
+ARC_INS_FLS = 52
+ARC_INS_ABS_S = 53
+ARC_INS_ADD1_S = 54
+ARC_INS_ADD2_S = 55
+ARC_INS_ADD3_S = 56
+ARC_INS_AND_S = 57
+ARC_INS_BIC_S = 58
+ARC_INS_BRK_S = 59
+ARC_INS_EXTB_S = 60
+ARC_INS_EXTH_S = 61
+ARC_INS_JEQ_S = 62
+ARC_INS_JL_S = 63
+ARC_INS_JL_S_D = 64
+ARC_INS_JNE_S = 65
+ARC_INS_J_S = 66
+ARC_INS_J_S_D = 67
+ARC_INS_LSR_S = 68
+ARC_INS_MPYUW_S = 69
+ARC_INS_MPYW_S = 70
+ARC_INS_MPY_S = 71
+ARC_INS_NEG_S = 72
+ARC_INS_NOP_S = 73
+ARC_INS_NOT_S = 74
+ARC_INS_OR_S = 75
+ARC_INS_SEXB_S = 76
+ARC_INS_SEXH_S = 77
+ARC_INS_SUB_S = 78
+ARC_INS_SUB_S_NE = 79
+ARC_INS_SWI_S = 80
+ARC_INS_TRAP_S = 81
+ARC_INS_TST_S = 82
+ARC_INS_UNIMP_S = 83
+ARC_INS_XOR_S = 84
+ARC_INS_LDB_S = 85
+ARC_INS_LDH_S = 86
+ARC_INS_J = 87
+ARC_INS_JL = 88
+ARC_INS_JLI_S = 89
+ARC_INS_LDB_AB = 90
+ARC_INS_LDB_AW = 91
+ARC_INS_LDB_DI_AB = 92
+ARC_INS_LDB_DI_AW = 93
+ARC_INS_LDB_DI = 94
+ARC_INS_LDB_X_AB = 95
+ARC_INS_LDB_X_AW = 96
+ARC_INS_LDB_X_DI_AB = 97
+ARC_INS_LDB_X_DI_AW = 98
+ARC_INS_LDB_X_DI = 99
+ARC_INS_LDB_X = 100
+ARC_INS_LDB = 101
+ARC_INS_LDH_AB = 102
+ARC_INS_LDH_AW = 103
+ARC_INS_LDH_DI_AB = 104
+ARC_INS_LDH_DI_AW = 105
+ARC_INS_LDH_DI = 106
+ARC_INS_LDH_S_X = 107
+ARC_INS_LDH_X_AB = 108
+ARC_INS_LDH_X_AW = 109
+ARC_INS_LDH_X_DI_AB = 110
+ARC_INS_LDH_X_DI_AW = 111
+ARC_INS_LDH_X_DI = 112
+ARC_INS_LDH_X = 113
+ARC_INS_LDH = 114
+ARC_INS_LDI_S = 115
+ARC_INS_LD_AB = 116
+ARC_INS_LD_AW = 117
+ARC_INS_LD_DI_AB = 118
+ARC_INS_LD_DI_AW = 119
+ARC_INS_LD_DI = 120
+ARC_INS_LD_S_AS = 121
+ARC_INS_LD = 122
+ARC_INS_LEAVE_S = 123
+ARC_INS_LR = 124
+ARC_INS_LSR = 125
+ARC_INS_LSR_F = 126
+ARC_INS_MAX = 127
+ARC_INS_MAX_F = 128
+ARC_INS_MIN = 129
+ARC_INS_MIN_F = 130
+ARC_INS_MOV_S_NE = 131
+ARC_INS_MOV = 132
+ARC_INS_MOV_F = 133
+ARC_INS_MPYMU = 134
+ARC_INS_MPYMU_F = 135
+ARC_INS_MPYM = 136
+ARC_INS_MPYM_F = 137
+ARC_INS_MPY = 138
+ARC_INS_MPY_F = 139
+ARC_INS_NORMH_F = 140
+ARC_INS_NORMH = 141
+ARC_INS_NORM_F = 142
+ARC_INS_NORM = 143
+ARC_INS_OR = 144
+ARC_INS_OR_F = 145
+ARC_INS_POP_S = 146
+ARC_INS_PUSH_S = 147
+ARC_INS_ROR = 148
+ARC_INS_ROR_F = 149
+ARC_INS_RSUB = 150
+ARC_INS_RSUB_F = 151
+ARC_INS_SBC = 152
+ARC_INS_SBC_F = 153
+ARC_INS_SETEQ = 154
+ARC_INS_SETEQ_F = 155
+ARC_INS_SEXB_F = 156
+ARC_INS_SEXB = 157
+ARC_INS_SEXH_F = 158
+ARC_INS_SEXH = 159
+ARC_INS_STB_S = 160
+ARC_INS_ST_S = 161
+ARC_INS_STB_AB = 162
+ARC_INS_STB_AW = 163
+ARC_INS_STB_DI_AB = 164
+ARC_INS_STB_DI_AW = 165
+ARC_INS_STB_DI = 166
+ARC_INS_STB = 167
+ARC_INS_STH_AB = 168
+ARC_INS_STH_AW = 169
+ARC_INS_STH_DI_AB = 170
+ARC_INS_STH_DI_AW = 171
+ARC_INS_STH_DI = 172
+ARC_INS_STH_S = 173
+ARC_INS_STH = 174
+ARC_INS_ST_AB = 175
+ARC_INS_ST_AW = 176
+ARC_INS_ST_DI_AB = 177
+ARC_INS_ST_DI_AW = 178
+ARC_INS_ST_DI = 179
+ARC_INS_ST = 180
+ARC_INS_SUB1 = 181
+ARC_INS_SUB1_F = 182
+ARC_INS_SUB2 = 183
+ARC_INS_SUB2_F = 184
+ARC_INS_SUB3 = 185
+ARC_INS_SUB3_F = 186
+ARC_INS_SUB = 187
+ARC_INS_SUB_F = 188
+ARC_INS_XOR = 189
+ARC_INS_XOR_F = 190
+
+# Group of ARC instructions
+
+ARC_GRP_INVALID = 0
+ARC_GRP_JUMP = 1
+ARC_GRP_CALL = 2
+ARC_GRP_RET = 3
+ARC_GRP_BRANCH_RELATIVE = 4
+ARC_GRP_ENDING = 5

bindings/python/capstone/arm.py

@@ -53,7 +53,7 @@ class ArmOp(ctypes.Structure):
         ('type', ctypes.c_uint),
         ('value', ArmOpValue),
         ('subtracted', ctypes.c_bool),
-        ('access', ctypes.c_uint8),
+        ('access', ctypes.c_uint),
         ('neon_lane', ctypes.c_int8),
     )
 

bindings/python/capstone/arm_const.py

@@ -1114,7 +1114,7 @@ ARM_INS_VRSQRTE = 562
 ARM_INS_VRSQRTS = 563
 ARM_INS_VRSRA = 564
 ARM_INS_VRSUBHN = 565
-ARM_INS_VSCCLRM_ = 566
+ARM_INS_VSCCLRM = 566
 ARM_INS_VSDOT = 567
 ARM_INS_VSELEQ = 568
 ARM_INS_VSELGE = 569
@@ -1145,98 +1145,97 @@ ARM_INS_VUSMMLA = 593
 ARM_INS_VUZP = 594
 ARM_INS_VZIP = 595
 ARM_INS_ADDW = 596
-ARM_INS_ADR_ = 597
-ARM_INS_AUT = 598
-ARM_INS_AUTG = 599
-ARM_INS_BFL = 600
-ARM_INS_BFLX = 601
-ARM_INS_BF = 602
-ARM_INS_BFCSEL = 603
-ARM_INS_BFX = 604
-ARM_INS_BTI = 605
-ARM_INS_BXAUT = 606
-ARM_INS_CLRM = 607
-ARM_INS_CSEL = 608
-ARM_INS_CSINC = 609
-ARM_INS_CSINV = 610
-ARM_INS_CSNEG = 611
-ARM_INS_DCPS1 = 612
-ARM_INS_DCPS2 = 613
-ARM_INS_DCPS3 = 614
-ARM_INS_DLS = 615
-ARM_INS_LE = 616
-ARM_INS_ORN = 617
-ARM_INS_PAC = 618
-ARM_INS_PACBTI = 619
-ARM_INS_PACG = 620
-ARM_INS_SG = 621
-ARM_INS_SUBS = 622
-ARM_INS_SUBW = 623
-ARM_INS_TBB = 624
-ARM_INS_TBH = 625
-ARM_INS_TT = 626
-ARM_INS_TTA = 627
-ARM_INS_TTAT = 628
-ARM_INS_TTT = 629
-ARM_INS_WLS = 630
-ARM_INS_BLXNS = 631
-ARM_INS_BXNS = 632
-ARM_INS_CBNZ = 633
-ARM_INS_CBZ = 634
-ARM_INS_POP = 635
-ARM_INS_PUSH = 636
-ARM_INS___BRKDIV0 = 637
-ARM_INS_ENDING = 638
-ARM_INS_ALIAS_BEGIN = 639
-ARM_INS_ALIAS_VMOV = 640
-ARM_INS_ALIAS_NOP = 641
-ARM_INS_ALIAS_YIELD = 642
-ARM_INS_ALIAS_WFE = 643
-ARM_INS_ALIAS_WFI = 644
-ARM_INS_ALIAS_SEV = 645
-ARM_INS_ALIAS_SEVL = 646
-ARM_INS_ALIAS_ESB = 647
-ARM_INS_ALIAS_CSDB = 648
-ARM_INS_ALIAS_CLRBHB = 649
-ARM_INS_ALIAS_PACBTI = 650
-ARM_INS_ALIAS_BTI = 651
-ARM_INS_ALIAS_PAC = 652
-ARM_INS_ALIAS_AUT = 653
-ARM_INS_ALIAS_SSBB = 654
-ARM_INS_ALIAS_PSSBB = 655
-ARM_INS_ALIAS_DFB = 656
-ARM_INS_ALIAS_CSETM = 657
-ARM_INS_ALIAS_CSET = 658
-ARM_INS_ALIAS_CINC = 659
-ARM_INS_ALIAS_CINV = 660
-ARM_INS_ALIAS_CNEG = 661
-ARM_INS_ALIAS_VMLAV = 662
-ARM_INS_ALIAS_VMLAVA = 663
-ARM_INS_ALIAS_VRMLALVH = 664
-ARM_INS_ALIAS_VRMLALVHA = 665
-ARM_INS_ALIAS_VMLALV = 666
-ARM_INS_ALIAS_VMLALVA = 667
-ARM_INS_ALIAS_VBIC = 668
-ARM_INS_ALIAS_VEOR = 669
-ARM_INS_ALIAS_VORN = 670
-ARM_INS_ALIAS_VORR = 671
-ARM_INS_ALIAS_VAND = 672
-ARM_INS_ALIAS_VPSEL = 673
-ARM_INS_ALIAS_ERET = 674
-ARM_INS_ALIAS_ASR = 675
-ARM_INS_ALIAS_LSL = 676
-ARM_INS_ALIAS_LSR = 677
-ARM_INS_ALIAS_ROR = 678
-ARM_INS_ALIAS_RRX = 679
-ARM_INS_ALIAS_UXTW = 680
-ARM_INS_ALIAS_LDM = 681
-ARM_INS_ALIAS_POP = 682
-ARM_INS_ALIAS_PUSH = 683
-ARM_INS_ALIAS_POPW = 684
-ARM_INS_ALIAS_PUSHW = 685
-ARM_INS_ALIAS_VPOP = 686
-ARM_INS_ALIAS_VPUSH = 687
-ARM_INS_ALIAS_END = 688
+ARM_INS_AUT = 597
+ARM_INS_AUTG = 598
+ARM_INS_BFL = 599
+ARM_INS_BFLX = 600
+ARM_INS_BF = 601
+ARM_INS_BFCSEL = 602
+ARM_INS_BFX = 603
+ARM_INS_BTI = 604
+ARM_INS_BXAUT = 605
+ARM_INS_CLRM = 606
+ARM_INS_CSEL = 607
+ARM_INS_CSINC = 608
+ARM_INS_CSINV = 609
+ARM_INS_CSNEG = 610
+ARM_INS_DCPS1 = 611
+ARM_INS_DCPS2 = 612
+ARM_INS_DCPS3 = 613
+ARM_INS_DLS = 614
+ARM_INS_LE = 615
+ARM_INS_ORN = 616
+ARM_INS_PAC = 617
+ARM_INS_PACBTI = 618
+ARM_INS_PACG = 619
+ARM_INS_SG = 620
+ARM_INS_SUBS = 621
+ARM_INS_SUBW = 622
+ARM_INS_TBB = 623
+ARM_INS_TBH = 624
+ARM_INS_TT = 625
+ARM_INS_TTA = 626
+ARM_INS_TTAT = 627
+ARM_INS_TTT = 628
+ARM_INS_WLS = 629
+ARM_INS_BLXNS = 630
+ARM_INS_BXNS = 631
+ARM_INS_CBNZ = 632
+ARM_INS_CBZ = 633
+ARM_INS_POP = 634
+ARM_INS_PUSH = 635
+ARM_INS___BRKDIV0 = 636
+ARM_INS_ENDING = 637
+ARM_INS_ALIAS_BEGIN = 638
+ARM_INS_ALIAS_VMOV = 639
+ARM_INS_ALIAS_NOP = 640
+ARM_INS_ALIAS_YIELD = 641
+ARM_INS_ALIAS_WFE = 642
+ARM_INS_ALIAS_WFI = 643
+ARM_INS_ALIAS_SEV = 644
+ARM_INS_ALIAS_SEVL = 645
+ARM_INS_ALIAS_ESB = 646
+ARM_INS_ALIAS_CSDB = 647
+ARM_INS_ALIAS_CLRBHB = 648
+ARM_INS_ALIAS_PACBTI = 649
+ARM_INS_ALIAS_BTI = 650
+ARM_INS_ALIAS_PAC = 651
+ARM_INS_ALIAS_AUT = 652
+ARM_INS_ALIAS_SSBB = 653
+ARM_INS_ALIAS_PSSBB = 654
+ARM_INS_ALIAS_DFB = 655
+ARM_INS_ALIAS_CSETM = 656
+ARM_INS_ALIAS_CSET = 657
+ARM_INS_ALIAS_CINC = 658
+ARM_INS_ALIAS_CINV = 659
+ARM_INS_ALIAS_CNEG = 660
+ARM_INS_ALIAS_VMLAV = 661
+ARM_INS_ALIAS_VMLAVA = 662
+ARM_INS_ALIAS_VRMLALVH = 663
+ARM_INS_ALIAS_VRMLALVHA = 664
+ARM_INS_ALIAS_VMLALV = 665
+ARM_INS_ALIAS_VMLALVA = 666
+ARM_INS_ALIAS_VBIC = 667
+ARM_INS_ALIAS_VEOR = 668
+ARM_INS_ALIAS_VORN = 669
+ARM_INS_ALIAS_VORR = 670
+ARM_INS_ALIAS_VAND = 671
+ARM_INS_ALIAS_VPSEL = 672
+ARM_INS_ALIAS_ERET = 673
+ARM_INS_ALIAS_ASR = 674
+ARM_INS_ALIAS_LSL = 675
+ARM_INS_ALIAS_LSR = 676
+ARM_INS_ALIAS_ROR = 677
+ARM_INS_ALIAS_RRX = 678
+ARM_INS_ALIAS_UXTW = 679
+ARM_INS_ALIAS_LDM = 680
+ARM_INS_ALIAS_POP = 681
+ARM_INS_ALIAS_PUSH = 682
+ARM_INS_ALIAS_POPW = 683
+ARM_INS_ALIAS_PUSHW = 684
+ARM_INS_ALIAS_VPOP = 685
+ARM_INS_ALIAS_VPUSH = 686
+ARM_INS_ALIAS_END = 687
 
 ARM_GRP_INVALID = 0
 ARM_GRP_JUMP = 1

bindings/python/capstone/bpf.py

@@ -28,7 +28,7 @@ class BPFOp(ctypes.Structure):
         ('value', BPFOpValue),
         ('is_signed', ctypes.c_bool),
         ('is_pkt', ctypes.c_bool),
-        ('access', ctypes.c_uint8),
+        ('access', ctypes.c_uint),
     )
 
     @property

bindings/python/capstone/bpf_const.py

@@ -1,14 +1,13 @@
 from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX, UINT8_MAX
 # For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [bpf_const.py]
-
-BPF_OP_INVALID = 0
-BPF_OP_REG = 1
-BPF_OP_IMM = 2
-BPF_OP_OFF = 3
-BPF_OP_MEM = 4
-BPF_OP_MMEM = 5
-BPF_OP_MSH = 6
-BPF_OP_EXT = 7
+BPF_OP_INVALID = CS_OP_INVALID
+BPF_OP_REG = CS_OP_REG
+BPF_OP_IMM = CS_OP_IMM
+BPF_OP_OFF = CS_OP_SPECIAL+0
+BPF_OP_MSH = CS_OP_SPECIAL+1
+BPF_OP_EXT = CS_OP_SPECIAL+2
+BPF_OP_MMEM = CS_OP_MEM|(CS_OP_SPECIAL+3)
+BPF_OP_MEM = CS_OP_MEM
 
 BPF_REG_INVALID = 0
 BPF_REG_A = 1
@@ -34,74 +33,119 @@ BPF_INS_ADD = 1
 BPF_INS_SUB = 2
 BPF_INS_MUL = 3
 BPF_INS_DIV = 4
-BPF_INS_OR = 5
-BPF_INS_AND = 6
-BPF_INS_LSH = 7
-BPF_INS_RSH = 8
-BPF_INS_NEG = 9
-BPF_INS_MOD = 10
-BPF_INS_XOR = 11
-BPF_INS_MOV = 12
-BPF_INS_ARSH = 13
-BPF_INS_ADD64 = 14
-BPF_INS_SUB64 = 15
-BPF_INS_MUL64 = 16
-BPF_INS_DIV64 = 17
-BPF_INS_OR64 = 18
-BPF_INS_AND64 = 19
-BPF_INS_LSH64 = 20
-BPF_INS_RSH64 = 21
-BPF_INS_NEG64 = 22
-BPF_INS_MOD64 = 23
-BPF_INS_XOR64 = 24
-BPF_INS_MOV64 = 25
-BPF_INS_ARSH64 = 26
-BPF_INS_LE16 = 27
-BPF_INS_LE32 = 28
-BPF_INS_LE64 = 29
-BPF_INS_BE16 = 30
-BPF_INS_BE32 = 31
-BPF_INS_BE64 = 32
-BPF_INS_BSWAP16 = 33
-BPF_INS_BSWAP32 = 34
-BPF_INS_BSWAP64 = 35
-BPF_INS_LDW = 36
-BPF_INS_LDH = 37
-BPF_INS_LDB = 38
-BPF_INS_LDDW = 39
-BPF_INS_LDXW = 40
-BPF_INS_LDXH = 41
-BPF_INS_LDXB = 42
-BPF_INS_LDXDW = 43
-BPF_INS_STW = 44
-BPF_INS_STH = 45
-BPF_INS_STB = 46
-BPF_INS_STDW = 47
-BPF_INS_STXW = 48
-BPF_INS_STXH = 49
-BPF_INS_STXB = 50
-BPF_INS_STXDW = 51
-BPF_INS_XADDW = 52
-BPF_INS_XADDDW = 53
-BPF_INS_JA = 54
-BPF_INS_JEQ = 55
-BPF_INS_JGT = 56
-BPF_INS_JGE = 57
-BPF_INS_JSET = 58
-BPF_INS_JNE = 59
-BPF_INS_JSGT = 60
-BPF_INS_JSGE = 61
-BPF_INS_CALL = 62
-BPF_INS_CALLX = 63
-BPF_INS_EXIT = 64
-BPF_INS_JLT = 65
-BPF_INS_JLE = 66
-BPF_INS_JSLT = 67
-BPF_INS_JSLE = 68
-BPF_INS_RET = 69
-BPF_INS_TAX = 70
-BPF_INS_TXA = 71
-BPF_INS_ENDING = 72
+BPF_INS_SDIV = 5
+BPF_INS_OR = 6
+BPF_INS_AND = 7
+BPF_INS_LSH = 8
+BPF_INS_RSH = 9
+BPF_INS_NEG = 10
+BPF_INS_MOD = 11
+BPF_INS_SMOD = 12
+BPF_INS_XOR = 13
+BPF_INS_MOV = 14
+BPF_INS_MOVSB = 15
+BPF_INS_MOVSH = 16
+BPF_INS_ARSH = 17
+BPF_INS_ADD64 = 18
+BPF_INS_SUB64 = 19
+BPF_INS_MUL64 = 20
+BPF_INS_DIV64 = 21
+BPF_INS_SDIV64 = 22
+BPF_INS_OR64 = 23
+BPF_INS_AND64 = 24
+BPF_INS_LSH64 = 25
+BPF_INS_RSH64 = 26
+BPF_INS_NEG64 = 27
+BPF_INS_MOD64 = 28
+BPF_INS_SMOD64 = 29
+BPF_INS_XOR64 = 30
+BPF_INS_MOV64 = 31
+BPF_INS_MOVSB64 = 32
+BPF_INS_MOVSH64 = 33
+BPF_INS_MOVSW64 = 34
+BPF_INS_ARSH64 = 35
+BPF_INS_LE16 = 36
+BPF_INS_LE32 = 37
+BPF_INS_LE64 = 38
+BPF_INS_BE16 = 39
+BPF_INS_BE32 = 40
+BPF_INS_BE64 = 41
+BPF_INS_BSWAP16 = 42
+BPF_INS_BSWAP32 = 43
+BPF_INS_BSWAP64 = 44
+BPF_INS_LDW = 45
+BPF_INS_LDH = 46
+BPF_INS_LDB = 47
+BPF_INS_LDDW = 48
+BPF_INS_LDXW = 49
+BPF_INS_LDXH = 50
+BPF_INS_LDXB = 51
+BPF_INS_LDXDW = 52
+BPF_INS_LDABSW = 53
+BPF_INS_LDABSH = 54
+BPF_INS_LDABSB = 55
+BPF_INS_LDINDW = 56
+BPF_INS_LDINDH = 57
+BPF_INS_LDINDB = 58
+BPF_INS_STW = 59
+BPF_INS_STH = 60
+BPF_INS_STB = 61
+BPF_INS_STDW = 62
+BPF_INS_STXW = 63
+BPF_INS_STXH = 64
+BPF_INS_STXB = 65
+BPF_INS_STXDW = 66
+BPF_INS_XADDW = 67
+BPF_INS_XADDDW = 68
+BPF_INS_JA = 69
+BPF_INS_JEQ = 70
+BPF_INS_JGT = 71
+BPF_INS_JGE = 72
+BPF_INS_JSET = 73
+BPF_INS_JNE = 74
+BPF_INS_JSGT = 75
+BPF_INS_JSGE = 76
+BPF_INS_CALL = 77
+BPF_INS_CALLX = 78
+BPF_INS_EXIT = 79
+BPF_INS_JLT = 80
+BPF_INS_JLE = 81
+BPF_INS_JSLT = 82
+BPF_INS_JSLE = 83
+BPF_INS_JAL = 84
+BPF_INS_JEQ32 = 85
+BPF_INS_JGT32 = 86
+BPF_INS_JGE32 = 87
+BPF_INS_JSET32 = 88
+BPF_INS_JNE32 = 89
+BPF_INS_JSGT32 = 90
+BPF_INS_JSGE32 = 91
+BPF_INS_JLT32 = 92
+BPF_INS_JLE32 = 93
+BPF_INS_JSLT32 = 94
+BPF_INS_JSLE32 = 95
+BPF_INS_RET = 96
+BPF_INS_AADD = 97
+BPF_INS_AOR = 98
+BPF_INS_AAND = 99
+BPF_INS_AXOR = 100
+BPF_INS_AFADD = 101
+BPF_INS_AFOR = 102
+BPF_INS_AFAND = 103
+BPF_INS_AFXOR = 104
+BPF_INS_AXCHG64 = 105
+BPF_INS_ACMPXCHG64 = 106
+BPF_INS_AADD64 = 107
+BPF_INS_AOR64 = 108
+BPF_INS_AAND64 = 109
+BPF_INS_AXOR64 = 110
+BPF_INS_AFADD64 = 111
+BPF_INS_AFOR64 = 112
+BPF_INS_AFAND64 = 113
+BPF_INS_AFXOR64 = 114
+BPF_INS_TAX = 115
+BPF_INS_TXA = 116
+BPF_INS_ENDING = 117
 BPF_INS_LD = BPF_INS_LDW
 BPF_INS_LDX = BPF_INS_LDXW
 BPF_INS_ST = BPF_INS_STW

bindings/python/capstone/evm_const.py

@@ -24,6 +24,9 @@ EVM_INS_OR = 23
 EVM_INS_XOR = 24
 EVM_INS_NOT = 25
 EVM_INS_BYTE = 26
+EVM_INS_SHL = 27
+EVM_INS_SHR = 28
+EVM_INS_SAR = 29
 EVM_INS_SHA3 = 32
 EVM_INS_ADDRESS = 48
 EVM_INS_BALANCE = 49
@@ -46,6 +49,11 @@ EVM_INS_TIMESTAMP = 66
 EVM_INS_NUMBER = 67
 EVM_INS_DIFFICULTY = 68
 EVM_INS_GASLIMIT = 69
+EVM_INS_CHAINID = 70
+EVM_INS_SELFBALANCE = 71
+EVM_INS_BASEFEE = 72
+EVM_INS_BLOBHASH = 73
+EVM_INS_BLOBBASEFEE = 74
 EVM_INS_POP = 80
 EVM_INS_MLOAD = 81
 EVM_INS_MSTORE = 82
@@ -58,6 +66,10 @@ EVM_INS_PC = 88
 EVM_INS_MSIZE = 89
 EVM_INS_GAS = 90
 EVM_INS_JUMPDEST = 91
+EVM_INS_TLOAD = 92
+EVM_INS_TSTORE = 93
+EVM_INS_MCOPY = 94
+EVM_INS_PUSH0 = 95
 EVM_INS_PUSH1 = 96
 EVM_INS_PUSH2 = 97
 EVM_INS_PUSH3 = 98
@@ -132,12 +144,12 @@ EVM_INS_CALL = 241
 EVM_INS_CALLCODE = 242
 EVM_INS_RETURN = 243
 EVM_INS_DELEGATECALL = 244
-EVM_INS_CALLBLACKBOX = 245
+EVM_INS_CREATE2 = 245
 EVM_INS_STATICCALL = 250
 EVM_INS_REVERT = 253
-EVM_INS_SUICIDE = 255
-EVM_INS_INVALID = 512
-EVM_INS_ENDING = 513
+EVM_INS_INVALID = 254
+EVM_INS_SELFDESTRUCT = 255
+EVM_INS_ENDING = 256
 
 EVM_GRP_INVALID = 0
 EVM_GRP_JUMP = 1

bindings/python/capstone/hppa.py

@@ -45,7 +45,7 @@ class HPPAOp(ctypes.Structure):
     _fields_ = (
         ('type', ctypes.c_uint8),
         ('value', HPPAOpValue),
-        ('access', ctypes.c_uint8)
+        ('access', ctypes.c_uint)
     )
 
     @property

bindings/python/capstone/hppa_const.py

@@ -2,14 +2,13 @@ from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_S
 # For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [hppa_const.py]
 HPPA_STR_MODIFIER_LEN = 8
 HPPA_MAX_MODIFIERS_LEN = 5
-
-HPPA_OP_INVALID = 0
-HPPA_OP_REG = 1
-HPPA_OP_IMM = 2
-HPPA_OP_IDX_REG = 3
-HPPA_OP_DISP = 4
-HPPA_OP_MEM = 5
-HPPA_OP_TARGET = 6
+HPPA_OP_INVALID = CS_OP_INVALID
+HPPA_OP_REG = CS_OP_REG
+HPPA_OP_IMM = CS_OP_IMM
+HPPA_OP_IDX_REG = CS_OP_SPECIAL+0
+HPPA_OP_DISP = CS_OP_SPECIAL+1
+HPPA_OP_TARGET = CS_OP_SPECIAL+2
+HPPA_OP_MEM = CS_OP_MEM
 
 # HPPA registers
 

bindings/python/capstone/m680x.py

@@ -44,7 +44,7 @@ class M680xOp(ctypes.Structure):
         ('type', ctypes.c_uint),
         ('value', M680xOpValue),
         ('size', ctypes.c_uint8),
-        ('access', ctypes.c_uint8),
+        ('access', ctypes.c_uint),
     )
 
     @property

bindings/python/capstone/m680x_const.py

@@ -25,15 +25,14 @@ M680X_REG_PC = 19
 M680X_REG_TMP2 = 20
 M680X_REG_TMP3 = 21
 M680X_REG_ENDING = 22
-
-M680X_OP_INVALID = 0
-M680X_OP_REGISTER = 1
-M680X_OP_IMMEDIATE = 2
-M680X_OP_INDEXED = 3
-M680X_OP_EXTENDED = 4
-M680X_OP_DIRECT = 5
-M680X_OP_RELATIVE = 6
-M680X_OP_CONSTANT = 7
+M680X_OP_INVALID = CS_OP_INVALID
+M680X_OP_REGISTER = CS_OP_REG
+M680X_OP_IMMEDIATE = CS_OP_IMM
+M680X_OP_INDEXED = CS_OP_SPECIAL+0
+M680X_OP_EXTENDED = CS_OP_SPECIAL+1
+M680X_OP_DIRECT = CS_OP_SPECIAL+2
+M680X_OP_RELATIVE = CS_OP_SPECIAL+3
+M680X_OP_CONSTANT = CS_OP_SPECIAL+4
 
 M680X_OFFSET_NONE = 0
 M680X_OFFSET_BITS_5 = 5

bindings/python/capstone/m68k_const.py

@@ -71,16 +71,15 @@ M68K_AM_ABSOLUTE_DATA_SHORT = 16
 M68K_AM_ABSOLUTE_DATA_LONG = 17
 M68K_AM_IMMEDIATE = 18
 M68K_AM_BRANCH_DISPLACEMENT = 19
-
-M68K_OP_INVALID = 0
-M68K_OP_REG = 1
-M68K_OP_IMM = 2
-M68K_OP_MEM = 3
-M68K_OP_FP_SINGLE = 4
-M68K_OP_FP_DOUBLE = 5
-M68K_OP_REG_BITS = 6
-M68K_OP_REG_PAIR = 7
-M68K_OP_BR_DISP = 8
+M68K_OP_INVALID = CS_OP_INVALID
+M68K_OP_REG = CS_OP_REG
+M68K_OP_IMM = CS_OP_IMM
+M68K_OP_FP_SINGLE = CS_OP_SPECIAL+0
+M68K_OP_FP_DOUBLE = CS_OP_SPECIAL+1
+M68K_OP_REG_BITS = CS_OP_SPECIAL+2
+M68K_OP_REG_PAIR = CS_OP_SPECIAL+3
+M68K_OP_BR_DISP = CS_OP_SPECIAL+4
+M68K_OP_MEM = CS_OP_MEM
 
 M68K_OP_BR_DISP_SIZE_INVALID = 0
 M68K_OP_BR_DISP_SIZE_BYTE = 1

bindings/python/capstone/mips.py

@@ -25,7 +25,7 @@ class MipsOp(ctypes.Structure):
         ('value', MipsOpValue),
         ('is_reglist', ctypes.c_bool),
         ('is_unsigned', ctypes.c_bool),
-        ('access', ctypes.c_uint8),
+        ('access', ctypes.c_uint),
     )
 
     @property

bindings/python/capstone/mips_const.py

@@ -1,10 +1,9 @@
 from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX, UINT8_MAX
 # For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [mips_const.py]
-
-MIPS_OP_INVALID = 0
-MIPS_OP_REG = 1
-MIPS_OP_IMM = 2
-MIPS_OP_MEM = 3
+MIPS_OP_INVALID = CS_OP_INVALID
+MIPS_OP_REG = CS_OP_REG
+MIPS_OP_IMM = CS_OP_IMM
+MIPS_OP_MEM = CS_OP_MEM
 
 MIPS_REG_INVALID = 0
 MIPS_REG_AT = 1
@@ -2111,7 +2110,11 @@ MIPS_INS_ALIAS_MTTC0 = 1464
 MIPS_INS_ALIAS_MTTLO = 1465
 MIPS_INS_ALIAS_MTTHI = 1466
 MIPS_INS_ALIAS_MTTACX = 1467
-MIPS_INS_ALIAS_END = 1468
+MIPS_INS_ALIAS_B = 1468
+MIPS_INS_ALIAS_BEQZ = 1469
+MIPS_INS_ALIAS_BNEZ = 1470
+MIPS_INS_ALIAS_LI = 1471
+MIPS_INS_ALIAS_END = 1472
 
 MIPS_GRP_INVALID = 0
 MIPS_GRP_JUMP = 1

bindings/python/capstone/mos65xx_const.py

@@ -146,8 +146,7 @@ MOS65XX_GRP_INT = 4
 MOS65XX_GRP_IRET = 5
 MOS65XX_GRP_BRANCH_RELATIVE = 6
 MOS65XX_GRP_ENDING = 7
-
-MOS65XX_OP_INVALID = 0
-MOS65XX_OP_REG = 1
-MOS65XX_OP_IMM = 2
-MOS65XX_OP_MEM = 3
+MOS65XX_OP_INVALID = CS_OP_INVALID
+MOS65XX_OP_REG = CS_OP_REG
+MOS65XX_OP_IMM = CS_OP_IMM
+MOS65XX_OP_MEM = CS_OP_MEM

bindings/python/capstone/riscv.py

@@ -22,7 +22,7 @@ class RISCVOp(ctypes.Structure):
     _fields_ = (
         ('type', ctypes.c_uint),
         ('value', RISCVOpValue),
-        ('access', ctypes.c_uint8),
+        ('access', ctypes.c_uint),
     )
 
     @property

bindings/python/capstone/riscv_const.py

@@ -2,11 +2,10 @@ from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_S
 # For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [riscv_const.py]
 
 # Operand type for instruction's operands
-
-RISCV_OP_INVALID = 0
-RISCV_OP_REG = 1
-RISCV_OP_IMM = 2
-RISCV_OP_MEM = 3
+RISCV_OP_INVALID = CS_OP_INVALID
+RISCV_OP_REG = CS_OP_REG
+RISCV_OP_IMM = CS_OP_IMM
+RISCV_OP_MEM = CS_OP_MEM
 
 # RISCV registers
 
@@ -440,17 +439,4 @@ RISCV_GRP_HASSTDEXTC = 131
 RISCV_GRP_HASSTDEXTD = 132
 RISCV_GRP_HASSTDEXTF = 133
 RISCV_GRP_HASSTDEXTM = 134
-RISCV_GRP_ISRVA = 135
-RISCV_GRP_ISRVC = 136
-RISCV_GRP_ISRVD = 137
-RISCV_GRP_ISRVCD = 138
-RISCV_GRP_ISRVF = 139
-RISCV_GRP_ISRV32C = 140
-RISCV_GRP_ISRV32CF = 141
-RISCV_GRP_ISRVM = 142
-RISCV_GRP_ISRV64A = 143
-RISCV_GRP_ISRV64C = 144
-RISCV_GRP_ISRV64D = 145
-RISCV_GRP_ISRV64F = 146
-RISCV_GRP_ISRV64M = 147
-RISCV_GRP_ENDING = 148
+RISCV_GRP_ENDING = 135

bindings/python/capstone/sh_const.py

@@ -124,11 +124,10 @@ SH_REG_DSP_RSVD = 119
 SH_REG_DSP_RSVE = 120
 SH_REG_DSP_RSVF = 121
 SH_REG_ENDING = 122
-
-SH_OP_INVALID = 0
-SH_OP_REG = 1
-SH_OP_IMM = 2
-SH_OP_MEM = 3
+SH_OP_INVALID = CS_OP_INVALID
+SH_OP_REG = CS_OP_REG
+SH_OP_IMM = CS_OP_IMM
+SH_OP_MEM = CS_OP_MEM
 
 SH_OP_MEM_INVALID = 0
 SH_OP_MEM_REG_IND = 1

bindings/python/capstone/sparc.py

@@ -7,8 +7,8 @@ from .sparc_const import *
 # define the API
 class SparcOpMem(ctypes.Structure):
     _fields_ = (
-        ('base', ctypes.c_uint8),
-        ('index', ctypes.c_uint8),
+        ('base', ctypes.c_uint),
+        ('index', ctypes.c_uint),
         ('disp', ctypes.c_int32),
     )
 
@@ -17,12 +17,15 @@ class SparcOpValue(ctypes.Union):
         ('reg', ctypes.c_uint),
         ('imm', ctypes.c_int64),
         ('mem', SparcOpMem),
+        ('membar_tag', ctypes.c_uint),
+        ('asi', ctypes.c_uint),
     )
 
 class SparcOp(ctypes.Structure):
     _fields_ = (
         ('type', ctypes.c_uint),
         ('value', SparcOpValue),
+        ('access', ctypes.c_uint8),
     )
 
     @property
@@ -37,15 +40,25 @@ class SparcOp(ctypes.Structure):
     def mem(self):
         return self.value.mem
 
+    @property
+    def asi(self):
+        return self.value.asi
+
+    @property
+    def membar_tag(self):
+        return self.value.membar_tag
+
 
 class CsSparc(ctypes.Structure):
     _fields_ = (
         ('cc', ctypes.c_uint),
+        ('cc_field', ctypes.c_uint),
         ('hint', ctypes.c_uint),
+        ('format', ctypes.c_uint),
         ('op_count', ctypes.c_uint8),
         ('operands', SparcOp * 4),
     )
 
 def get_arch_info(a):
-    return (a.cc, a.hint, copy_ctypes_list(a.operands[:a.op_count]))
+    return (a.cc, a.cc_field, a.hint, a.format, copy_ctypes_list(a.operands[:a.op_count]))
 

bindings/python/capstone/systemz.py

@@ -25,7 +25,7 @@ class SystemZOp(ctypes.Structure):
     _fields_ = (
         ('type', ctypes.c_uint),
         ('value', SystemZOpValue),
-        ('access', ctypes.c_int),
+        ('access', ctypes.c_uint),
         ('imm_width', ctypes.c_uint8),
     )
 

bindings/python/capstone/tms320c64x_const.py

@@ -1,11 +1,10 @@
 from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX, UINT8_MAX
 # For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [tms320c64x_const.py]
-
-TMS320C64X_OP_INVALID = 0
-TMS320C64X_OP_REG = 1
-TMS320C64X_OP_IMM = 2
-TMS320C64X_OP_MEM = 3
-TMS320C64X_OP_REGPAIR = 64
+TMS320C64X_OP_INVALID = CS_OP_INVALID
+TMS320C64X_OP_REG = CS_OP_REG
+TMS320C64X_OP_IMM = CS_OP_IMM
+TMS320C64X_OP_REGPAIR = CS_OP_SPECIAL+0
+TMS320C64X_OP_MEM = CS_OP_MEM
 
 TMS320C64X_MEM_DISP_INVALID = 0
 TMS320C64X_MEM_DISP_CONSTANT = 1

bindings/python/capstone/tricore.py

@@ -23,7 +23,7 @@ class TriCoreOp(ctypes.Structure):
     _fields_ = (
         ('type', ctypes.c_uint),
         ('value', TriCoreOpValue),
-        ('access', ctypes.c_uint8)
+        ('access', ctypes.c_uint)
     )
 
     @property

bindings/python/capstone/tricore_const.py

@@ -79,387 +79,423 @@ TRICORE_INS_ABSS_B = 7
 TRICORE_INS_ABSS_H = 8
 TRICORE_INS_ABSS = 9
 TRICORE_INS_ABS_B = 10
-TRICORE_INS_ABS_H = 11
-TRICORE_INS_ABS = 12
-TRICORE_INS_ADDC = 13
-TRICORE_INS_ADDIH_A = 14
-TRICORE_INS_ADDIH = 15
-TRICORE_INS_ADDI = 16
-TRICORE_INS_ADDSC_AT = 17
-TRICORE_INS_ADDSC_A = 18
-TRICORE_INS_ADDS_BU = 19
-TRICORE_INS_ADDS_B = 20
-TRICORE_INS_ADDS_H = 21
-TRICORE_INS_ADDS_HU = 22
-TRICORE_INS_ADDS_U = 23
-TRICORE_INS_ADDS = 24
-TRICORE_INS_ADDX = 25
-TRICORE_INS_ADD_A = 26
-TRICORE_INS_ADD_B = 27
-TRICORE_INS_ADD_F = 28
-TRICORE_INS_ADD_H = 29
-TRICORE_INS_ADD = 30
-TRICORE_INS_ANDN_T = 31
-TRICORE_INS_ANDN = 32
-TRICORE_INS_AND_ANDN_T = 33
-TRICORE_INS_AND_AND_T = 34
-TRICORE_INS_AND_EQ = 35
-TRICORE_INS_AND_GE_U = 36
-TRICORE_INS_AND_GE = 37
-TRICORE_INS_AND_LT_U = 38
-TRICORE_INS_AND_LT = 39
-TRICORE_INS_AND_NE = 40
-TRICORE_INS_AND_NOR_T = 41
-TRICORE_INS_AND_OR_T = 42
-TRICORE_INS_AND_T = 43
-TRICORE_INS_AND = 44
-TRICORE_INS_BISR = 45
-TRICORE_INS_BMERGE = 46
-TRICORE_INS_BSPLIT = 47
-TRICORE_INS_CACHEA_I = 48
-TRICORE_INS_CACHEA_WI = 49
-TRICORE_INS_CACHEA_W = 50
-TRICORE_INS_CACHEI_I = 51
-TRICORE_INS_CACHEI_WI = 52
-TRICORE_INS_CACHEI_W = 53
-TRICORE_INS_CADDN_A = 54
-TRICORE_INS_CADDN = 55
-TRICORE_INS_CADD_A = 56
-TRICORE_INS_CADD = 57
-TRICORE_INS_CALLA = 58
-TRICORE_INS_CALLI = 59
-TRICORE_INS_CALL = 60
-TRICORE_INS_CLO_B = 61
-TRICORE_INS_CLO_H = 62
-TRICORE_INS_CLO = 63
-TRICORE_INS_CLS_B = 64
-TRICORE_INS_CLS_H = 65
-TRICORE_INS_CLS = 66
-TRICORE_INS_CLZ_B = 67
-TRICORE_INS_CLZ_H = 68
-TRICORE_INS_CLZ = 69
-TRICORE_INS_CMOVN = 70
-TRICORE_INS_CMOV = 71
-TRICORE_INS_CMPSWAP_W = 72
-TRICORE_INS_CMP_F = 73
-TRICORE_INS_CRC32B_W = 74
-TRICORE_INS_CRC32L_W = 75
-TRICORE_INS_CRC32_B = 76
-TRICORE_INS_CRCN = 77
-TRICORE_INS_CSUBN_A = 78
-TRICORE_INS_CSUBN = 79
-TRICORE_INS_CSUB_A = 80
-TRICORE_INS_CSUB = 81
-TRICORE_INS_DEBUG = 82
-TRICORE_INS_DEXTR = 83
-TRICORE_INS_DIFSC_A = 84
-TRICORE_INS_DISABLE = 85
-TRICORE_INS_DIV_F = 86
-TRICORE_INS_DIV_U = 87
-TRICORE_INS_DIV = 88
-TRICORE_INS_DSYNC = 89
-TRICORE_INS_DVADJ = 90
-TRICORE_INS_DVINIT_BU = 91
-TRICORE_INS_DVINIT_B = 92
-TRICORE_INS_DVINIT_HU = 93
-TRICORE_INS_DVINIT_H = 94
-TRICORE_INS_DVINIT_U = 95
-TRICORE_INS_DVINIT = 96
-TRICORE_INS_DVSTEP_U = 97
-TRICORE_INS_DVSTEP = 98
-TRICORE_INS_ENABLE = 99
-TRICORE_INS_EQANY_B = 100
-TRICORE_INS_EQANY_H = 101
-TRICORE_INS_EQZ_A = 102
-TRICORE_INS_EQ_A = 103
-TRICORE_INS_EQ_B = 104
-TRICORE_INS_EQ_H = 105
-TRICORE_INS_EQ_W = 106
-TRICORE_INS_EQ = 107
-TRICORE_INS_EXTR_U = 108
-TRICORE_INS_EXTR = 109
-TRICORE_INS_FCALLA = 110
-TRICORE_INS_FCALLI = 111
-TRICORE_INS_FCALL = 112
-TRICORE_INS_FRET = 113
-TRICORE_INS_FTOHP = 114
-TRICORE_INS_FTOIZ = 115
-TRICORE_INS_FTOI = 116
-TRICORE_INS_FTOQ31Z = 117
-TRICORE_INS_FTOQ31 = 118
-TRICORE_INS_FTOUZ = 119
-TRICORE_INS_FTOU = 120
-TRICORE_INS_GE_A = 121
-TRICORE_INS_GE_U = 122
-TRICORE_INS_GE = 123
-TRICORE_INS_HPTOF = 124
-TRICORE_INS_IMASK = 125
-TRICORE_INS_INSERT = 126
-TRICORE_INS_INSN_T = 127
-TRICORE_INS_INS_T = 128
-TRICORE_INS_ISYNC = 129
-TRICORE_INS_ITOF = 130
-TRICORE_INS_IXMAX_U = 131
-TRICORE_INS_IXMAX = 132
-TRICORE_INS_IXMIN_U = 133
-TRICORE_INS_IXMIN = 134
-TRICORE_INS_JA = 135
-TRICORE_INS_JEQ_A = 136
-TRICORE_INS_JEQ = 137
-TRICORE_INS_JGEZ = 138
-TRICORE_INS_JGE_U = 139
-TRICORE_INS_JGE = 140
-TRICORE_INS_JGTZ = 141
-TRICORE_INS_JI = 142
-TRICORE_INS_JLA = 143
-TRICORE_INS_JLEZ = 144
-TRICORE_INS_JLI = 145
-TRICORE_INS_JLTZ = 146
-TRICORE_INS_JLT_U = 147
-TRICORE_INS_JLT = 148
-TRICORE_INS_JL = 149
-TRICORE_INS_JNED = 150
-TRICORE_INS_JNEI = 151
-TRICORE_INS_JNE_A = 152
-TRICORE_INS_JNE = 153
-TRICORE_INS_JNZ_A = 154
-TRICORE_INS_JNZ_T = 155
-TRICORE_INS_JNZ = 156
-TRICORE_INS_JZ_A = 157
-TRICORE_INS_JZ_T = 158
-TRICORE_INS_JZ = 159
-TRICORE_INS_J = 160
-TRICORE_INS_LDLCX = 161
-TRICORE_INS_LDMST = 162
-TRICORE_INS_LDUCX = 163
-TRICORE_INS_LD_A = 164
-TRICORE_INS_LD_BU = 165
-TRICORE_INS_LD_B = 166
-TRICORE_INS_LD_DA = 167
-TRICORE_INS_LD_D = 168
-TRICORE_INS_LD_HU = 169
-TRICORE_INS_LD_H = 170
-TRICORE_INS_LD_Q = 171
-TRICORE_INS_LD_W = 172
-TRICORE_INS_LEA = 173
-TRICORE_INS_LHA = 174
-TRICORE_INS_LOOPU = 175
-TRICORE_INS_LOOP = 176
-TRICORE_INS_LT_A = 177
-TRICORE_INS_LT_B = 178
-TRICORE_INS_LT_BU = 179
-TRICORE_INS_LT_H = 180
-TRICORE_INS_LT_HU = 181
-TRICORE_INS_LT_U = 182
-TRICORE_INS_LT_W = 183
-TRICORE_INS_LT_WU = 184
-TRICORE_INS_LT = 185
-TRICORE_INS_MADDMS_H = 186
-TRICORE_INS_MADDMS_U = 187
-TRICORE_INS_MADDMS = 188
-TRICORE_INS_MADDM_H = 189
-TRICORE_INS_MADDM_Q = 190
-TRICORE_INS_MADDM_U = 191
-TRICORE_INS_MADDM = 192
-TRICORE_INS_MADDRS_H = 193
-TRICORE_INS_MADDRS_Q = 194
-TRICORE_INS_MADDR_H = 195
-TRICORE_INS_MADDR_Q = 196
-TRICORE_INS_MADDSUMS_H = 197
-TRICORE_INS_MADDSUM_H = 198
-TRICORE_INS_MADDSURS_H = 199
-TRICORE_INS_MADDSUR_H = 200
-TRICORE_INS_MADDSUS_H = 201
-TRICORE_INS_MADDSU_H = 202
-TRICORE_INS_MADDS_H = 203
-TRICORE_INS_MADDS_Q = 204
-TRICORE_INS_MADDS_U = 205
-TRICORE_INS_MADDS = 206
-TRICORE_INS_MADD_F = 207
-TRICORE_INS_MADD_H = 208
-TRICORE_INS_MADD_Q = 209
-TRICORE_INS_MADD_U = 210
-TRICORE_INS_MADD = 211
-TRICORE_INS_MAX_B = 212
-TRICORE_INS_MAX_BU = 213
-TRICORE_INS_MAX_H = 214
-TRICORE_INS_MAX_HU = 215
-TRICORE_INS_MAX_U = 216
-TRICORE_INS_MAX = 217
-TRICORE_INS_MFCR = 218
-TRICORE_INS_MIN_B = 219
-TRICORE_INS_MIN_BU = 220
-TRICORE_INS_MIN_H = 221
-TRICORE_INS_MIN_HU = 222
-TRICORE_INS_MIN_U = 223
-TRICORE_INS_MIN = 224
-TRICORE_INS_MOVH_A = 225
-TRICORE_INS_MOVH = 226
-TRICORE_INS_MOVZ_A = 227
-TRICORE_INS_MOV_AA = 228
-TRICORE_INS_MOV_A = 229
-TRICORE_INS_MOV_D = 230
-TRICORE_INS_MOV_U = 231
-TRICORE_INS_MOV = 232
-TRICORE_INS_MSUBADMS_H = 233
-TRICORE_INS_MSUBADM_H = 234
-TRICORE_INS_MSUBADRS_H = 235
-TRICORE_INS_MSUBADR_H = 236
-TRICORE_INS_MSUBADS_H = 237
-TRICORE_INS_MSUBAD_H = 238
-TRICORE_INS_MSUBMS_H = 239
-TRICORE_INS_MSUBMS_U = 240
-TRICORE_INS_MSUBMS = 241
-TRICORE_INS_MSUBM_H = 242
-TRICORE_INS_MSUBM_Q = 243
-TRICORE_INS_MSUBM_U = 244
-TRICORE_INS_MSUBM = 245
-TRICORE_INS_MSUBRS_H = 246
-TRICORE_INS_MSUBRS_Q = 247
-TRICORE_INS_MSUBR_H = 248
-TRICORE_INS_MSUBR_Q = 249
-TRICORE_INS_MSUBS_H = 250
-TRICORE_INS_MSUBS_Q = 251
-TRICORE_INS_MSUBS_U = 252
-TRICORE_INS_MSUBS = 253
-TRICORE_INS_MSUB_F = 254
-TRICORE_INS_MSUB_H = 255
-TRICORE_INS_MSUB_Q = 256
-TRICORE_INS_MSUB_U = 257
-TRICORE_INS_MSUB = 258
-TRICORE_INS_MTCR = 259
-TRICORE_INS_MULMS_H = 260
-TRICORE_INS_MULM_H = 261
-TRICORE_INS_MULM_U = 262
-TRICORE_INS_MULM = 263
-TRICORE_INS_MULR_H = 264
-TRICORE_INS_MULR_Q = 265
-TRICORE_INS_MULS_U = 266
-TRICORE_INS_MULS = 267
-TRICORE_INS_MUL_F = 268
-TRICORE_INS_MUL_H = 269
-TRICORE_INS_MUL_Q = 270
-TRICORE_INS_MUL_U = 271
-TRICORE_INS_MUL = 272
-TRICORE_INS_NAND_T = 273
-TRICORE_INS_NAND = 274
-TRICORE_INS_NEZ_A = 275
-TRICORE_INS_NE_A = 276
-TRICORE_INS_NE = 277
-TRICORE_INS_NOP = 278
-TRICORE_INS_NOR_T = 279
-TRICORE_INS_NOR = 280
-TRICORE_INS_NOT = 281
-TRICORE_INS_ORN_T = 282
-TRICORE_INS_ORN = 283
-TRICORE_INS_OR_ANDN_T = 284
-TRICORE_INS_OR_AND_T = 285
-TRICORE_INS_OR_EQ = 286
-TRICORE_INS_OR_GE_U = 287
-TRICORE_INS_OR_GE = 288
-TRICORE_INS_OR_LT_U = 289
-TRICORE_INS_OR_LT = 290
-TRICORE_INS_OR_NE = 291
-TRICORE_INS_OR_NOR_T = 292
-TRICORE_INS_OR_OR_T = 293
-TRICORE_INS_OR_T = 294
-TRICORE_INS_OR = 295
-TRICORE_INS_PACK = 296
-TRICORE_INS_PARITY = 297
-TRICORE_INS_POPCNT_W = 298
-TRICORE_INS_Q31TOF = 299
-TRICORE_INS_QSEED_F = 300
-TRICORE_INS_RESTORE = 301
-TRICORE_INS_RET = 302
-TRICORE_INS_RFE = 303
-TRICORE_INS_RFM = 304
-TRICORE_INS_RSLCX = 305
-TRICORE_INS_RSTV = 306
-TRICORE_INS_RSUBS_U = 307
-TRICORE_INS_RSUBS = 308
-TRICORE_INS_RSUB = 309
-TRICORE_INS_SAT_BU = 310
-TRICORE_INS_SAT_B = 311
-TRICORE_INS_SAT_HU = 312
-TRICORE_INS_SAT_H = 313
-TRICORE_INS_SELN_A = 314
-TRICORE_INS_SELN = 315
-TRICORE_INS_SEL_A = 316
-TRICORE_INS_SEL = 317
-TRICORE_INS_SHAS = 318
-TRICORE_INS_SHA_B = 319
-TRICORE_INS_SHA_H = 320
-TRICORE_INS_SHA = 321
-TRICORE_INS_SHUFFLE = 322
-TRICORE_INS_SH_ANDN_T = 323
-TRICORE_INS_SH_AND_T = 324
-TRICORE_INS_SH_B = 325
-TRICORE_INS_SH_EQ = 326
-TRICORE_INS_SH_GE_U = 327
-TRICORE_INS_SH_GE = 328
-TRICORE_INS_SH_H = 329
-TRICORE_INS_SH_LT_U = 330
-TRICORE_INS_SH_LT = 331
-TRICORE_INS_SH_NAND_T = 332
-TRICORE_INS_SH_NE = 333
-TRICORE_INS_SH_NOR_T = 334
-TRICORE_INS_SH_ORN_T = 335
-TRICORE_INS_SH_OR_T = 336
-TRICORE_INS_SH_XNOR_T = 337
-TRICORE_INS_SH_XOR_T = 338
-TRICORE_INS_SH = 339
-TRICORE_INS_STLCX = 340
-TRICORE_INS_STUCX = 341
-TRICORE_INS_ST_A = 342
-TRICORE_INS_ST_B = 343
-TRICORE_INS_ST_DA = 344
-TRICORE_INS_ST_D = 345
-TRICORE_INS_ST_H = 346
-TRICORE_INS_ST_Q = 347
-TRICORE_INS_ST_T = 348
-TRICORE_INS_ST_W = 349
-TRICORE_INS_SUBC = 350
-TRICORE_INS_SUBSC_A = 351
-TRICORE_INS_SUBS_BU = 352
-TRICORE_INS_SUBS_B = 353
-TRICORE_INS_SUBS_HU = 354
-TRICORE_INS_SUBS_H = 355
-TRICORE_INS_SUBS_U = 356
-TRICORE_INS_SUBS = 357
-TRICORE_INS_SUBX = 358
-TRICORE_INS_SUB_A = 359
-TRICORE_INS_SUB_B = 360
-TRICORE_INS_SUB_F = 361
-TRICORE_INS_SUB_H = 362
-TRICORE_INS_SUB = 363
-TRICORE_INS_SVLCX = 364
-TRICORE_INS_SWAPMSK_W = 365
-TRICORE_INS_SWAP_A = 366
-TRICORE_INS_SWAP_W = 367
-TRICORE_INS_SYSCALL = 368
-TRICORE_INS_TLBDEMAP = 369
-TRICORE_INS_TLBFLUSH_A = 370
-TRICORE_INS_TLBFLUSH_B = 371
-TRICORE_INS_TLBMAP = 372
-TRICORE_INS_TLBPROBE_A = 373
-TRICORE_INS_TLBPROBE_I = 374
-TRICORE_INS_TRAPSV = 375
-TRICORE_INS_TRAPV = 376
-TRICORE_INS_UNPACK = 377
-TRICORE_INS_UPDFL = 378
-TRICORE_INS_UTOF = 379
-TRICORE_INS_WAIT = 380
-TRICORE_INS_XNOR_T = 381
-TRICORE_INS_XNOR = 382
-TRICORE_INS_XOR_EQ = 383
-TRICORE_INS_XOR_GE_U = 384
-TRICORE_INS_XOR_GE = 385
-TRICORE_INS_XOR_LT_U = 386
-TRICORE_INS_XOR_LT = 387
-TRICORE_INS_XOR_NE = 388
-TRICORE_INS_XOR_T = 389
-TRICORE_INS_XOR = 390
-TRICORE_INS_ENDING = 391
+TRICORE_INS_ABS_DF = 11
+TRICORE_INS_ABS_F = 12
+TRICORE_INS_ABS_H = 13
+TRICORE_INS_ABS = 14
+TRICORE_INS_ADDC = 15
+TRICORE_INS_ADDIH_A = 16
+TRICORE_INS_ADDIH = 17
+TRICORE_INS_ADDI = 18
+TRICORE_INS_ADDSC_AT = 19
+TRICORE_INS_ADDSC_A = 20
+TRICORE_INS_ADDS_BU = 21
+TRICORE_INS_ADDS_B = 22
+TRICORE_INS_ADDS_H = 23
+TRICORE_INS_ADDS_HU = 24
+TRICORE_INS_ADDS_U = 25
+TRICORE_INS_ADDS = 26
+TRICORE_INS_ADDX = 27
+TRICORE_INS_ADD_A = 28
+TRICORE_INS_ADD_B = 29
+TRICORE_INS_ADD_DF = 30
+TRICORE_INS_ADD_F = 31
+TRICORE_INS_ADD_H = 32
+TRICORE_INS_ADD = 33
+TRICORE_INS_ANDN_T = 34
+TRICORE_INS_ANDN = 35
+TRICORE_INS_AND_ANDN_T = 36
+TRICORE_INS_AND_AND_T = 37
+TRICORE_INS_AND_EQ = 38
+TRICORE_INS_AND_GE_U = 39
+TRICORE_INS_AND_GE = 40
+TRICORE_INS_AND_LT_U = 41
+TRICORE_INS_AND_LT = 42
+TRICORE_INS_AND_NE = 43
+TRICORE_INS_AND_NOR_T = 44
+TRICORE_INS_AND_OR_T = 45
+TRICORE_INS_AND_T = 46
+TRICORE_INS_AND = 47
+TRICORE_INS_BISR = 48
+TRICORE_INS_BMERGE = 49
+TRICORE_INS_BSPLIT = 50
+TRICORE_INS_CACHEA_I = 51
+TRICORE_INS_CACHEA_WI = 52
+TRICORE_INS_CACHEA_W = 53
+TRICORE_INS_CACHEI_I = 54
+TRICORE_INS_CACHEI_WI = 55
+TRICORE_INS_CACHEI_W = 56
+TRICORE_INS_CADDN_A = 57
+TRICORE_INS_CADDN = 58
+TRICORE_INS_CADD_A = 59
+TRICORE_INS_CADD = 60
+TRICORE_INS_CALLA = 61
+TRICORE_INS_CALLI = 62
+TRICORE_INS_CALL = 63
+TRICORE_INS_CLO_B = 64
+TRICORE_INS_CLO_H = 65
+TRICORE_INS_CLO = 66
+TRICORE_INS_CLS_B = 67
+TRICORE_INS_CLS_H = 68
+TRICORE_INS_CLS = 69
+TRICORE_INS_CLZ_B = 70
+TRICORE_INS_CLZ_H = 71
+TRICORE_INS_CLZ = 72
+TRICORE_INS_CMOVN = 73
+TRICORE_INS_CMOV = 74
+TRICORE_INS_CMPSWAP_W = 75
+TRICORE_INS_CMP_DF = 76
+TRICORE_INS_CMP_F = 77
+TRICORE_INS_CRC32B_W = 78
+TRICORE_INS_CRC32L_W = 79
+TRICORE_INS_CRC32_B = 80
+TRICORE_INS_CRCN = 81
+TRICORE_INS_CSUBN_A = 82
+TRICORE_INS_CSUBN = 83
+TRICORE_INS_CSUB_A = 84
+TRICORE_INS_CSUB = 85
+TRICORE_INS_DEBUG = 86
+TRICORE_INS_DEXTR = 87
+TRICORE_INS_DFTOF = 88
+TRICORE_INS_DFTOIN = 89
+TRICORE_INS_DFTOIZ = 90
+TRICORE_INS_DFTOI = 91
+TRICORE_INS_DFTOLZ = 92
+TRICORE_INS_DFTOL = 93
+TRICORE_INS_DFTOULZ = 94
+TRICORE_INS_DFTOUL = 95
+TRICORE_INS_DFTOUZ = 96
+TRICORE_INS_DFTOU = 97
+TRICORE_INS_DIFSC_A = 98
+TRICORE_INS_DISABLE = 99
+TRICORE_INS_DIV64_U = 100
+TRICORE_INS_DIV64 = 101
+TRICORE_INS_DIV_DF = 102
+TRICORE_INS_DIV_F = 103
+TRICORE_INS_DIV_U = 104
+TRICORE_INS_DIV = 105
+TRICORE_INS_DSYNC = 106
+TRICORE_INS_DVADJ = 107
+TRICORE_INS_DVINIT_BU = 108
+TRICORE_INS_DVINIT_B = 109
+TRICORE_INS_DVINIT_HU = 110
+TRICORE_INS_DVINIT_H = 111
+TRICORE_INS_DVINIT_U = 112
+TRICORE_INS_DVINIT = 113
+TRICORE_INS_DVSTEP_U = 114
+TRICORE_INS_DVSTEP = 115
+TRICORE_INS_ENABLE = 116
+TRICORE_INS_EQANY_B = 117
+TRICORE_INS_EQANY_H = 118
+TRICORE_INS_EQZ_A = 119
+TRICORE_INS_EQ_A = 120
+TRICORE_INS_EQ_B = 121
+TRICORE_INS_EQ_H = 122
+TRICORE_INS_EQ_W = 123
+TRICORE_INS_EQ = 124
+TRICORE_INS_EXTR_U = 125
+TRICORE_INS_EXTR = 126
+TRICORE_INS_FCALLA = 127
+TRICORE_INS_FCALLI = 128
+TRICORE_INS_FCALL = 129
+TRICORE_INS_FRET = 130
+TRICORE_INS_FTODF = 131
+TRICORE_INS_FTOHP = 132
+TRICORE_INS_FTOIN = 133
+TRICORE_INS_FTOIZ = 134
+TRICORE_INS_FTOI = 135
+TRICORE_INS_FTOQ31Z = 136
+TRICORE_INS_FTOQ31 = 137
+TRICORE_INS_FTOUZ = 138
+TRICORE_INS_FTOU = 139
+TRICORE_INS_GE_A = 140
+TRICORE_INS_GE_U = 141
+TRICORE_INS_GE = 142
+TRICORE_INS_HPTOF = 143
+TRICORE_INS_IMASK = 144
+TRICORE_INS_INSERT = 145
+TRICORE_INS_INSN_T = 146
+TRICORE_INS_INS_T = 147
+TRICORE_INS_ISYNC = 148
+TRICORE_INS_ITODF = 149
+TRICORE_INS_ITOF = 150
+TRICORE_INS_IXMAX_U = 151
+TRICORE_INS_IXMAX = 152
+TRICORE_INS_IXMIN_U = 153
+TRICORE_INS_IXMIN = 154
+TRICORE_INS_JA = 155
+TRICORE_INS_JEQ_A = 156
+TRICORE_INS_JEQ = 157
+TRICORE_INS_JGEZ = 158
+TRICORE_INS_JGE_U = 159
+TRICORE_INS_JGE = 160
+TRICORE_INS_JGTZ = 161
+TRICORE_INS_JI = 162
+TRICORE_INS_JLA = 163
+TRICORE_INS_JLEZ = 164
+TRICORE_INS_JLI = 165
+TRICORE_INS_JLTZ = 166
+TRICORE_INS_JLT_U = 167
+TRICORE_INS_JLT = 168
+TRICORE_INS_JL = 169
+TRICORE_INS_JNED = 170
+TRICORE_INS_JNEI = 171
+TRICORE_INS_JNE_A = 172
+TRICORE_INS_JNE = 173
+TRICORE_INS_JNZ_A = 174
+TRICORE_INS_JNZ_T = 175
+TRICORE_INS_JNZ = 176
+TRICORE_INS_JZ_A = 177
+TRICORE_INS_JZ_T = 178
+TRICORE_INS_JZ = 179
+TRICORE_INS_J = 180
+TRICORE_INS_LDLCX = 181
+TRICORE_INS_LDMST = 182
+TRICORE_INS_LDUCX = 183
+TRICORE_INS_LD_A = 184
+TRICORE_INS_LD_BU = 185
+TRICORE_INS_LD_B = 186
+TRICORE_INS_LD_DA = 187
+TRICORE_INS_LD_D = 188
+TRICORE_INS_LD_HU = 189
+TRICORE_INS_LD_H = 190
+TRICORE_INS_LD_Q = 191
+TRICORE_INS_LD_W = 192
+TRICORE_INS_LEA = 193
+TRICORE_INS_LHA = 194
+TRICORE_INS_LOOPU = 195
+TRICORE_INS_LOOP = 196
+TRICORE_INS_LTODF = 197
+TRICORE_INS_LT_A = 198
+TRICORE_INS_LT_B = 199
+TRICORE_INS_LT_BU = 200
+TRICORE_INS_LT_H = 201
+TRICORE_INS_LT_HU = 202
+TRICORE_INS_LT_U = 203
+TRICORE_INS_LT_W = 204
+TRICORE_INS_LT_WU = 205
+TRICORE_INS_LT = 206
+TRICORE_INS_MADDMS_H = 207
+TRICORE_INS_MADDMS_U = 208
+TRICORE_INS_MADDMS = 209
+TRICORE_INS_MADDM_H = 210
+TRICORE_INS_MADDM_Q = 211
+TRICORE_INS_MADDM_U = 212
+TRICORE_INS_MADDM = 213
+TRICORE_INS_MADDRS_H = 214
+TRICORE_INS_MADDRS_Q = 215
+TRICORE_INS_MADDR_H = 216
+TRICORE_INS_MADDR_Q = 217
+TRICORE_INS_MADDSUMS_H = 218
+TRICORE_INS_MADDSUM_H = 219
+TRICORE_INS_MADDSURS_H = 220
+TRICORE_INS_MADDSUR_H = 221
+TRICORE_INS_MADDSUS_H = 222
+TRICORE_INS_MADDSU_H = 223
+TRICORE_INS_MADDS_H = 224
+TRICORE_INS_MADDS_Q = 225
+TRICORE_INS_MADDS_U = 226
+TRICORE_INS_MADDS = 227
+TRICORE_INS_MADD_DF = 228
+TRICORE_INS_MADD_F = 229
+TRICORE_INS_MADD_H = 230
+TRICORE_INS_MADD_Q = 231
+TRICORE_INS_MADD_U = 232
+TRICORE_INS_MADD = 233
+TRICORE_INS_MAX_B = 234
+TRICORE_INS_MAX_BU = 235
+TRICORE_INS_MAX_DF = 236
+TRICORE_INS_MAX_F = 237
+TRICORE_INS_MAX_H = 238
+TRICORE_INS_MAX_HU = 239
+TRICORE_INS_MAX_U = 240
+TRICORE_INS_MAX = 241
+TRICORE_INS_MFCR = 242
+TRICORE_INS_MIN_B = 243
+TRICORE_INS_MIN_BU = 244
+TRICORE_INS_MIN_DF = 245
+TRICORE_INS_MIN_F = 246
+TRICORE_INS_MIN_H = 247
+TRICORE_INS_MIN_HU = 248
+TRICORE_INS_MIN_U = 249
+TRICORE_INS_MIN = 250
+TRICORE_INS_MOVH_A = 251
+TRICORE_INS_MOVH = 252
+TRICORE_INS_MOVZ_A = 253
+TRICORE_INS_MOV_AA = 254
+TRICORE_INS_MOV_A = 255
+TRICORE_INS_MOV_D = 256
+TRICORE_INS_MOV_U = 257
+TRICORE_INS_MOV = 258
+TRICORE_INS_MSUBADMS_H = 259
+TRICORE_INS_MSUBADM_H = 260
+TRICORE_INS_MSUBADRS_H = 261
+TRICORE_INS_MSUBADR_H = 262
+TRICORE_INS_MSUBADS_H = 263
+TRICORE_INS_MSUBAD_H = 264
+TRICORE_INS_MSUBMS_H = 265
+TRICORE_INS_MSUBMS_U = 266
+TRICORE_INS_MSUBMS = 267
+TRICORE_INS_MSUBM_H = 268
+TRICORE_INS_MSUBM_Q = 269
+TRICORE_INS_MSUBM_U = 270
+TRICORE_INS_MSUBM = 271
+TRICORE_INS_MSUBRS_H = 272
+TRICORE_INS_MSUBRS_Q = 273
+TRICORE_INS_MSUBR_H = 274
+TRICORE_INS_MSUBR_Q = 275
+TRICORE_INS_MSUBS_H = 276
+TRICORE_INS_MSUBS_Q = 277
+TRICORE_INS_MSUBS_U = 278
+TRICORE_INS_MSUBS = 279
+TRICORE_INS_MSUB_DF = 280
+TRICORE_INS_MSUB_F = 281
+TRICORE_INS_MSUB_H = 282
+TRICORE_INS_MSUB_Q = 283
+TRICORE_INS_MSUB_U = 284
+TRICORE_INS_MSUB = 285
+TRICORE_INS_MTCR = 286
+TRICORE_INS_MULMS_H = 287
+TRICORE_INS_MULM_H = 288
+TRICORE_INS_MULM_U = 289
+TRICORE_INS_MULM = 290
+TRICORE_INS_MULR_H = 291
+TRICORE_INS_MULR_Q = 292
+TRICORE_INS_MULS_U = 293
+TRICORE_INS_MULS = 294
+TRICORE_INS_MUL_DF = 295
+TRICORE_INS_MUL_F = 296
+TRICORE_INS_MUL_H = 297
+TRICORE_INS_MUL_Q = 298
+TRICORE_INS_MUL_U = 299
+TRICORE_INS_MUL = 300
+TRICORE_INS_NAND_T = 301
+TRICORE_INS_NAND = 302
+TRICORE_INS_NEG_DF = 303
+TRICORE_INS_NEG_F = 304
+TRICORE_INS_NEZ_A = 305
+TRICORE_INS_NE_A = 306
+TRICORE_INS_NE = 307
+TRICORE_INS_NOP = 308
+TRICORE_INS_NOR_T = 309
+TRICORE_INS_NOR = 310
+TRICORE_INS_NOT = 311
+TRICORE_INS_ORN_T = 312
+TRICORE_INS_ORN = 313
+TRICORE_INS_OR_ANDN_T = 314
+TRICORE_INS_OR_AND_T = 315
+TRICORE_INS_OR_EQ = 316
+TRICORE_INS_OR_GE_U = 317
+TRICORE_INS_OR_GE = 318
+TRICORE_INS_OR_LT_U = 319
+TRICORE_INS_OR_LT = 320
+TRICORE_INS_OR_NE = 321
+TRICORE_INS_OR_NOR_T = 322
+TRICORE_INS_OR_OR_T = 323
+TRICORE_INS_OR_T = 324
+TRICORE_INS_OR = 325
+TRICORE_INS_PACK = 326
+TRICORE_INS_PARITY = 327
+TRICORE_INS_POPCNT_W = 328
+TRICORE_INS_Q31TOF = 329
+TRICORE_INS_QSEED_DF = 330
+TRICORE_INS_QSEED_F = 331
+TRICORE_INS_REM64_U = 332
+TRICORE_INS_REM64 = 333
+TRICORE_INS_RESTORE = 334
+TRICORE_INS_RET = 335
+TRICORE_INS_RFE = 336
+TRICORE_INS_RFM = 337
+TRICORE_INS_RSLCX = 338
+TRICORE_INS_RSTV = 339
+TRICORE_INS_RSUBS_U = 340
+TRICORE_INS_RSUBS = 341
+TRICORE_INS_RSUB = 342
+TRICORE_INS_SAT_BU = 343
+TRICORE_INS_SAT_B = 344
+TRICORE_INS_SAT_HU = 345
+TRICORE_INS_SAT_H = 346
+TRICORE_INS_SELN_A = 347
+TRICORE_INS_SELN = 348
+TRICORE_INS_SEL_A = 349
+TRICORE_INS_SEL = 350
+TRICORE_INS_SHAS = 351
+TRICORE_INS_SHA_B = 352
+TRICORE_INS_SHA_H = 353
+TRICORE_INS_SHA = 354
+TRICORE_INS_SHUFFLE = 355
+TRICORE_INS_SH_ANDN_T = 356
+TRICORE_INS_SH_AND_T = 357
+TRICORE_INS_SH_B = 358
+TRICORE_INS_SH_EQ = 359
+TRICORE_INS_SH_GE_U = 360
+TRICORE_INS_SH_GE = 361
+TRICORE_INS_SH_H = 362
+TRICORE_INS_SH_LT_U = 363
+TRICORE_INS_SH_LT = 364
+TRICORE_INS_SH_NAND_T = 365
+TRICORE_INS_SH_NE = 366
+TRICORE_INS_SH_NOR_T = 367
+TRICORE_INS_SH_ORN_T = 368
+TRICORE_INS_SH_OR_T = 369
+TRICORE_INS_SH_XNOR_T = 370
+TRICORE_INS_SH_XOR_T = 371
+TRICORE_INS_SH = 372
+TRICORE_INS_STLCX = 373
+TRICORE_INS_STUCX = 374
+TRICORE_INS_ST_A = 375
+TRICORE_INS_ST_B = 376
+TRICORE_INS_ST_DA = 377
+TRICORE_INS_ST_D = 378
+TRICORE_INS_ST_H = 379
+TRICORE_INS_ST_Q = 380
+TRICORE_INS_ST_T = 381
+TRICORE_INS_ST_W = 382
+TRICORE_INS_SUBC = 383
+TRICORE_INS_SUBSC_A = 384
+TRICORE_INS_SUBS_BU = 385
+TRICORE_INS_SUBS_B = 386
+TRICORE_INS_SUBS_HU = 387
+TRICORE_INS_SUBS_H = 388
+TRICORE_INS_SUBS_U = 389
+TRICORE_INS_SUBS = 390
+TRICORE_INS_SUBX = 391
+TRICORE_INS_SUB_A = 392
+TRICORE_INS_SUB_B = 393
+TRICORE_INS_SUB_DF = 394
+TRICORE_INS_SUB_F = 395
+TRICORE_INS_SUB_H = 396
+TRICORE_INS_SUB = 397
+TRICORE_INS_SVLCX = 398
+TRICORE_INS_SWAPMSK_W = 399
+TRICORE_INS_SWAP_A = 400
+TRICORE_INS_SWAP_W = 401
+TRICORE_INS_SYSCALL = 402
+TRICORE_INS_TLBDEMAP = 403
+TRICORE_INS_TLBFLUSH_A = 404
+TRICORE_INS_TLBFLUSH_B = 405
+TRICORE_INS_TLBMAP = 406
+TRICORE_INS_TLBPROBE_A = 407
+TRICORE_INS_TLBPROBE_I = 408
+TRICORE_INS_TRAPSV = 409
+TRICORE_INS_TRAPV = 410
+TRICORE_INS_ULTODF = 411
+TRICORE_INS_UNPACK = 412
+TRICORE_INS_UPDFL = 413
+TRICORE_INS_UTODF = 414
+TRICORE_INS_UTOF = 415
+TRICORE_INS_WAIT = 416
+TRICORE_INS_XNOR_T = 417
+TRICORE_INS_XNOR = 418
+TRICORE_INS_XOR_EQ = 419
+TRICORE_INS_XOR_GE_U = 420
+TRICORE_INS_XOR_GE = 421
+TRICORE_INS_XOR_LT_U = 422
+TRICORE_INS_XOR_LT = 423
+TRICORE_INS_XOR_NE = 424
+TRICORE_INS_XOR_T = 425
+TRICORE_INS_XOR = 426
+TRICORE_INS_ENDING = 427
 
 TRICORE_GRP_INVALID = 0
 TRICORE_GRP_CALL = 1
@@ -474,16 +510,19 @@ TRICORE_FEATURE_HASV131 = 131
 TRICORE_FEATURE_HASV160 = 132
 TRICORE_FEATURE_HASV161 = 133
 TRICORE_FEATURE_HASV162 = 134
-TRICORE_FEATURE_HASV120_UP = 135
-TRICORE_FEATURE_HASV130_UP = 136
-TRICORE_FEATURE_HASV131_UP = 137
-TRICORE_FEATURE_HASV160_UP = 138
-TRICORE_FEATURE_HASV161_UP = 139
-TRICORE_FEATURE_HASV162_UP = 140
-TRICORE_FEATURE_HASV120_DN = 141
-TRICORE_FEATURE_HASV130_DN = 142
-TRICORE_FEATURE_HASV131_DN = 143
-TRICORE_FEATURE_HASV160_DN = 144
-TRICORE_FEATURE_HASV161_DN = 145
-TRICORE_FEATURE_HASV162_DN = 146
-TRICORE_FEATURE_ENDING = 147
+TRICORE_FEATURE_HASV180 = 135
+TRICORE_FEATURE_HASV120_UP = 136
+TRICORE_FEATURE_HASV130_UP = 137
+TRICORE_FEATURE_HASV131_UP = 138
+TRICORE_FEATURE_HASV160_UP = 139
+TRICORE_FEATURE_HASV161_UP = 140
+TRICORE_FEATURE_HASV162_UP = 141
+TRICORE_FEATURE_HASV180_UP = 142
+TRICORE_FEATURE_HASV120_DN = 143
+TRICORE_FEATURE_HASV130_DN = 144
+TRICORE_FEATURE_HASV131_DN = 145
+TRICORE_FEATURE_HASV160_DN = 146
+TRICORE_FEATURE_HASV161_DN = 147
+TRICORE_FEATURE_HASV162_DN = 148
+TRICORE_FEATURE_HASV180_DN = 149
+TRICORE_FEATURE_ENDING = 150

bindings/python/capstone/wasm_const.py

@@ -1,15 +1,14 @@
 from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX, UINT8_MAX
 # For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [wasm_const.py]
-
-WASM_OP_INVALID = 0
-WASM_OP_NONE = 1
-WASM_OP_INT7 = 2
-WASM_OP_VARUINT32 = 3
-WASM_OP_VARUINT64 = 4
-WASM_OP_UINT32 = 5
-WASM_OP_UINT64 = 6
-WASM_OP_IMM = 7
-WASM_OP_BRTABLE = 8
+WASM_OP_INVALID = CS_OP_INVALID
+WASM_OP_IMM = CS_OP_IMM
+WASM_OP_NONE = CS_OP_SPECIAL+0
+WASM_OP_INT7 = CS_OP_SPECIAL+1
+WASM_OP_VARUINT32 = CS_OP_SPECIAL+2
+WASM_OP_VARUINT64 = CS_OP_SPECIAL+3
+WASM_OP_UINT32 = CS_OP_SPECIAL+4
+WASM_OP_UINT64 = CS_OP_SPECIAL+5
+WASM_OP_BRTABLE = CS_OP_SPECIAL+6
 WASM_INS_UNREACHABLE = 0x0
 WASM_INS_NOP = 0x1
 WASM_INS_BLOCK = 0x2

bindings/python/capstone/x86.py

@@ -26,7 +26,7 @@ class X86Op(ctypes.Structure):
         ('type', ctypes.c_uint),
         ('value', X86OpValue),
         ('size', ctypes.c_uint8),
-        ('access', ctypes.c_uint8),
+        ('access', ctypes.c_uint),
         ('avx_bcast', ctypes.c_uint),
         ('avx_zero_opmask', ctypes.c_bool),
     )

bindings/python/capstone/x86_const.py

@@ -327,11 +327,10 @@ X86_FPU_FLAGS_TEST_C0 = 1<<16
 X86_FPU_FLAGS_TEST_C1 = 1<<17
 X86_FPU_FLAGS_TEST_C2 = 1<<18
 X86_FPU_FLAGS_TEST_C3 = 1<<19
-
-X86_OP_INVALID = 0
-X86_OP_REG = 1
-X86_OP_IMM = 2
-X86_OP_MEM = 3
+X86_OP_INVALID = CS_OP_INVALID
+X86_OP_REG = CS_OP_REG
+X86_OP_IMM = CS_OP_IMM
+X86_OP_MEM = CS_OP_MEM
 
 X86_XOP_CC_INVALID = 0
 X86_XOP_CC_LT = 1

bindings/python/capstone/xcore_const.py

@@ -1,10 +1,9 @@
 from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX, UINT8_MAX
 # For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [xcore_const.py]
-
-XCORE_OP_INVALID = 0
-XCORE_OP_REG = 1
-XCORE_OP_IMM = 2
-XCORE_OP_MEM = 3
+XCORE_OP_INVALID = CS_OP_INVALID
+XCORE_OP_REG = CS_OP_REG
+XCORE_OP_IMM = CS_OP_IMM
+XCORE_OP_MEM = CS_OP_MEM
 
 XCORE_REG_INVALID = 0
 XCORE_REG_CP = 1

bindings/python/capstone/xtensa_const.py

@@ -1644,4 +1644,4 @@ XTENSA_OP_IMM = CS_OP_IMM
 XTENSA_OP_MEM = CS_OP_MEM
 XTENSA_OP_MEM_REG = CS_OP_MEM_REG
 XTENSA_OP_MEM_IMM = CS_OP_MEM_IMM
-XTENSA_OP_L32R = 14
+XTENSA_OP_L32R = CS_OP_SPECIAL+0